JPH0245922A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an excessive etching from being made to the electrode side surface and improve machining accuracy by providing an area implanted with impurity ions where impurity ions are implanted selectively at one part of a non-doped polycrystal silicon layer. CONSTITUTION:A silicon oxide film 2 is provided on a silicon substrate 1 and a polycrystal silicon layer 3 is accumulated on the silicon film 2. A first photoresist film 4 is applied to the silicon layer 3 for patterning and an opening is provided. Phosphor ions are implanted with a resist film 4 as a mask and an ion implantation area 6 is formed. The resist film 4 is eliminated, a second photoresist film 7 is spread over the entire surface for patterning, and a pattern for forming electrode is formed. The silicon layer 3 is etching-eliminated and an electrode is formed. Annealing is performed and an activation area 8 is formed within the electrode, thus preventing an excessive etching from being made to the side surface of the electrode and improving machining accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an electrode made of a polycrystalline silicon layer.

[Conventional technology]

As shown in FIG. 2(a), the conventional method for manufacturing a semiconductor device involves a silicon oxide film 2 formed on a silicon substrate 1.
A polycrystalline silicon layer 9 doped with phosphorus is deposited thereon.

Next, a photoresist film 7 is applied onto the polycrystalline silicon layer 9 and patterned to form a desired pattern for forming an electrode. Next, as shown in FIG. 2(b), using the photoresist film 7 as a mask, the polycrystalline silicon layer 9 is etched by reactive ion etching using, for example, chlorine-based gas, and the electrode made of the polycrystalline silicon layer 9 is etched. form.

At this time, since the polycrystalline silicon layer 9 is doped with phosphorus, it is easily etched, and a constricted portion 11 is formed at the interface between the inverted tapered portion 10 and the silicon oxide film 2 on the side surface of the electrode.

[Problem to be solved by the invention]

The conventional semiconductor device manufacturing method described above is described in the Proceedings of Symposium on Dry Process by Horie et al.
iumon Dry ProcessH981 year 104
Reactive Ion on pages 39-45 on the 26th and 27th.
Etching of Phosphor Doped Polysilicon Using CF3 Br C1!2 (Re-a
active Ion Etching of P do
ped poly-5t usingCF3Br-CI
As reported in the title of □), the cross-sectional shape of the electrode made of a polycrystalline silicon layer doped with phosphorus becomes an inverted Taber shape due to excessive etching, and there is a problem in that a constriction occurs at the interface with the insulating film. be.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a non-doped polycrystalline silicon layer on an insulating film provided on a semiconductor substrate, and forming a patterned first photoresist film on the polycrystalline silicon layer. a step of implanting impurity ions into the surface of the polycrystalline silicon layer using the first photoresist film as a mask to form an impurity ion implantation region; and a step of removing the first photoresist film and aligning with the impurity ion implantation region. and a step of selectively providing a second photoresist film having a pattern covering the surface of the impurity ion implantation region, and removing the polycrystalline silicon layer by anisotropic etching using the second photoresist film as a mask. The method includes a step of forming an electrode having a pattern and a step of diffusing impurities and activating the electrode by heat treatment.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), a silicon oxide film 2 is provided on a silicon substrate 1, and a polycrystalline silicon layer 3 is deposited on the silicon oxide film 2 to a thickness of 0.6 μm. Next, a first photoresist film 4 is applied onto the polycrystalline silicon layer 3 and patterned to form openings corresponding to the electrode formation patterns. Next, using the photoresist film 4 as a mask, phosphorus ions 5 are implanted at an acceleration energy of about 50 keV and a dose of lXl019 cm-2, and the phosphorus ions are implanted to a depth of 0.15 to 0.2 μm from the surface of the polycrystalline silicon layer 3. Region 6 is formed. Here, the width of the phosphorus ion implantation region 6 is desirably formed to be about 0.3 μm smaller than the required electrode formation width.

Next, as shown in FIG. 1(b), the photoresist film 4 is removed, and a second photoresist film 7 is applied and patterned on the surface including the phosphorus ion implantation region 6. A pattern for forming an electrode is formed to cover the surface of the phosphorus ion implantation region 6.

Next, as shown in FIG. 1(e), the polycrystalline silicon layer 3 is etched and removed by reactive ion etching using a chlorine gas such as CF2Cj72 using the photoresist film 7 as a mask to form a desired pattern. form an electrode with Here, the non-doped polycrystalline silicon layer 3 is less likely to cause undercuts and can be patterned with high precision.

Next, as shown in FIG. 1(d), annealing is performed for 10 minutes at a temperature of 500 to 950 DEG C. to form an activated region 8 within the electrode.

〔Effect of the invention〕

As explained above, the present invention provides an impurity ion implantation region in which impurity ions are selectively implanted into a part of a non-doped polycrystalline silicon layer, and aligns with the impurity ion implantation region and forms a part of the impurity ion implantation region. By anisotropically etching the non-doped portion of the polycrystalline silicon layer using a photoresist film with a pattern for electrode formation covering the surface as a mask, it is possible to prevent excessive etching of the sides of the formed electrode and improve processing accuracy. has.

Note that the electrode can be annealed after removing the photoresist film to diffuse impurities and activate the electrode to obtain the required conductivity.

[Brief explanation of the drawing]

1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) and (b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device. 1... Silicon substrate, 2... Silicon oxide film, 3.
... Polycrystalline silicon layer, 4... Photoresist film, 5.
... Phosphorus ion, 6... Phosphorus ion implantation region, 7...
- Photoresist film, 8... Activated region, 9... Polycrystalline silicon layer, 10... Reverse taper part, 11... Constricted part.

Claims (1)

[Claims] forming a non-doped polycrystalline silicon layer on an insulating film provided on a semiconductor substrate, forming a patterned first photoresist film on the polycrystalline silicon layer and using the first photoresist film as a mask; forming an impurity ion implantation region by implanting impurity ions into the surface of the polycrystalline silicon layer; and removing the first photoresist film to match the impurity ion implantation region and cover the surface of the impurity ion implantation region. a step of selectively providing a second photoresist film having a pattern; and a step of anisotropically etching and removing the polycrystalline silicon layer using the second photoresist film as a mask to form an electrode having a desired pattern. A method for manufacturing a semiconductor device, comprising the steps of: diffusing impurities and activating the electrode by heat treatment.