JP2000188396A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for uniformly etching a gate insulating film and a semiconductor substrate without damaging them and for forming a gate electrode, when regions different in etching rates are given in the same gate polysilicon film by means of introducing different concentration ions or different ion types. SOLUTION: When regions 6a and 6b, where the impurities of different concentration or the impurities of different types are partially implanted, exist in a polysilicon film 6 formed on a semiconductor substrate as shown in Fig. (b), the impurities of high etching rate are implanted (6c) in an etched region after a lithographic process for patterning a gate electrode, and the etching rate is made uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a gate electrode in a semiconductor device, and more particularly, to a method for forming a gate electrode by simultaneously etching polysilicon films having different etching rates.

[0002]

2. Description of the Related Art In order to increase the saturation current and the subthreshold characteristic of a MOSFET, it is necessary to reduce the gate length and simultaneously increase the capacitance of the gate insulating film. For this reason, a thinner gate oxide film has conventionally been used as a means for improving the performance of a MOSFET.

However, in the region where the gate oxide film thickness is extremely thin, the effective film thickness is observed to be larger than the physical film thickness due to the effect of forming a depletion layer in the polysilicon gate electrode (gate electrode depletion effect). Phenomenon becomes apparent, and it becomes difficult to obtain the effect of thinning. Therefore, in order to improve the performance of the MOSFET, it is necessary to take measures to prevent gate electrode depletion at the same time as reducing the thickness of the gate oxide film.

To prevent gate electrode depletion, it is effective to increase the impurity concentration in the gate electrode. For this purpose, impurity ions are implanted immediately after the polysilicon film is deposited,
Increasing the impurity concentration in the gate electrode is an effective means.

On the other hand, when impurity ions are introduced into a polysilicon film, it is known that the etch rate at the time of dry etching changes according to the type and quantity of implanted ions. For example, it is known that when phosphorus ions are implanted into non-doped polysilicon, the etch rate increases, and when boron ions are implanted, the etch rate decreases. Assuming the adoption of the PN gate structure, if ion implantation is performed only in a part of the polysilicon film, or if multiple ion species are introduced into the polysilicon film,
It becomes difficult to uniformly etch and remove polysilicon. Therefore, especially when the gate insulating film is thin, there is a risk that the semiconductor substrate is etched by over-etching.

Therefore, if impurity ions have been introduced only into a part of the polysilicon film in advance, or if different ion species have been introduced depending on the region, a process for uniformly etching and removing these ions is required. Will be needed.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in consideration of the fact that ions of different concentrations or different ion species are introduced into the same polysilicon film. It is an object of the present invention to provide a method for forming a gate electrode by etching simultaneously without damaging a gate insulating film or a semiconductor substrate when regions having different etching rates are provided.

[0008]

SUMMARY OF THE INVENTION According to the present invention, there is provided a step of implanting impurities of different concentrations and / or types into at least two or more regions of a polysilicon film formed on a semiconductor substrate, A second step of forming a mask used for patterning the gate electrode thereon, a third step of implanting an impurity having a high etching rate into a region where the mask is not formed, and
Etching a region where the mask is not formed to form a polysilicon gate electrode.

The impurity having a high etching rate used in the third step is preferably phosphorus.

In the case where the impurities used in the first step include phosphorus, the implantation concentration of phosphorus used in the third step is further increased so that the etching rate in the region where the mask is not formed is increased. Can be made uniform.

The present invention can be used for a method of manufacturing a semiconductor device using a polysilicon film as a gate electrode, and is particularly effective for a method of manufacturing a semiconductor device having a CMOS structure.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view showing a process in which a polysilicon film having regions having different etching rates is simultaneously etched to form a gate electrode as an embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3A shows that a polysilicon film 6 is formed on a gate insulating film 5 provided on a semiconductor substrate.

FIG. 3B shows a state in which impurities having different concentrations or different kinds of impurities are partially implanted into the polysilicon film.

For example, an area A (6a) and an area B (6b)
As an example in which the concentration of the implanted impurities is different, the impurities implanted in the region A (6a) and the region B (6b) are the same species (for example, phosphorus or boron), but the implanted concentrations are different. In some cases, a kind of impurity (for example, phosphorus or boron) is implanted in the region A (6a) and no impurity is implanted in the region B (6b).

For example, a region A (6a) and a region B (6b)
Examples of different types of impurities include the region A (6
This is the case where phosphorus is implanted into a) and boron is implanted into the region B (6b).

Next, as shown in FIG. 3C, for example, a resist pattern 7 is formed on regions where the states of the implanted impurities are different. This resist pattern serves as a mask, and a gate electrode is formed in a later step. As described above, when the etching is performed in the state of FIG. 3C, the etching rate is different between the region A and the region B. Therefore, if the etching condition is adjusted to one region, the remaining etching is not performed in the other region. Occurs, or on the contrary, the gate insulating film is over-etched.

In the present invention, as shown in FIG. 3D, an impurity is implanted to make the etching rate uniform. This impurity implantation is performed, for example, by implanting phosphorus having a high etching rate. Instead of phosphorus,
It is also possible to implant impurities such as Si, As, and Ge.

In this case, in the step shown in FIG. 3B, if phosphorus has already been implanted into a part of the polysilicon film, phosphorus having a higher concentration than the already implanted phosphorus is used. Need to be injected. Regarding the concentration, the higher the concentration, the higher the effect of uniform etching is. However, when the concentration is increased, the concentration may diffuse into the gate electrode. Therefore, it is preferable that the concentration is such that the electrical characteristics of the gate electrode do not significantly change. .

As shown in FIG. 3E, etching is performed uniformly up to the gate insulating film to form a gate electrode structure.

The manufacturing method of the present invention can be used for a method of manufacturing a semiconductor device using a polysilicon film as a gate electrode. For example, it is a very effective manufacturing method for a semiconductor device having a CMOS structure.

Hereinafter, the present invention will be described in more detail with reference to embodiments.

(Embodiment 1) A first embodiment of the present invention will be described with reference to cross-sectional views in respective steps shown in FIG. First, as shown in FIG. 1A, an element isolation region 2 made of a silicon oxide film is formed on a semiconductor substrate 1, and then a P well region 3 is formed by lithography and ion implantation.
And an N well region 4 are formed.

Subsequently, as shown in FIG.
And a 200 nm-thick polycrystalline silicon film 6 is formed.

Subsequently, as shown in FIG. 1C, first phosphorus ions are selectively implanted into the polycrystalline silicon film existing on the region where the NMOSFET is to be formed using the photoresist 7 as a mask (for example, 20 KeV 3 × 10 ¹⁵ / cm ³ ). By this step, a region 8 in which phosphorus is implanted in the polysilicon film is formed.

Subsequently, as shown in FIG. 1D, a photoresist 8 used for patterning the gate electrode is formed on the polycrystalline silicon film 6.

Subsequently, as shown in FIG. 1E, a second phosphorus ion is implanted into the polysilicon film. Since the first phosphorus has already been implanted into the region 8, it is necessary to implant a higher concentration than the first phosphorus, for example, 5 × 10 ¹⁵ / c at 20 KeV.
injecting m ^3.

Subsequently, as shown in FIG. 1F, a gate electrode is formed by etching the polycrystalline silicon film using the resist pattern as a mask.

By the implantation of the second phosphorus ions, the etch rates of the polysilicon on the N well and the polysilicon on the P well become equal. It is possible to perform uniform etching without damaging the gate insulating film 5 and the N well and the P well thereunder.

(Embodiment 2) A second embodiment of the present invention will be described with reference to cross-sectional views in respective steps shown in FIG. According to the first embodiment, as shown in FIG.
First phosphorus ions are implanted into a polysilicon film existing in a region where ET is to be formed (for example, 20 KeV 3 × 10 ¹⁵ / cm ³ ).

Subsequently, as shown in FIG. 2B, boron ions are implanted into the polycrystalline silicon film existing on the region where the PMOSFET is to be formed (for example, 20 KeV 3 × 10 ¹⁵ / cm ³ ).

Subsequently, as shown in FIG. 2C, a resist pattern used for patterning the gate electrode is formed. Subsequently, in order to make the etch rate uniform, a second phosphorus ion implantation is performed (for example, 20 KeV 1 × 10 ¹⁶ / cm ³ ).

Subsequently, the polycrystalline silicon film into which phosphorus has been introduced is etched to form a gate electrode as shown in FIG.

As described above, even when the gate electrode is formed by etching the polysilicon film into which impurities of different types are partially implanted, uniform etching can be performed by implanting impurities having a high etching rate. it can.

[0035]

As described above, the present invention can be applied to a case where impurity ions are previously introduced into a polysilicon film in a part of a region before a gate electrode is formed, or a case where different ion species are simultaneously introduced into a polysilicon film. When introduced, after the lithography step for patterning the gate electrode, the feature is that an impurity having a large etch rate is implanted into a region to be etched, whereby the etching rate in the region where the etching rate was originally different is Can be made uniform, and as a result, a gate electrode can be formed without damaging the gate insulating film below the polysilicon film and the well.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view showing a process according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a case where a polysilicon film having regions having different etching rates is simultaneously etched to form a gate electrode, as one embodiment of the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation 3 P well 4 N well 5 Gate insulating film 6 Polysilicon film 6a, 6b Polysilicon film in which impurities were implanted 6c Polysilicon film in which impurities with a high etching rate were implanted 7 Resist pattern 8 Low concentration Phosphorus-doped polysilicon film 9 Resist pattern 10 High-concentration phosphorus-doped polysilicon film 11 Boron-doped polysilicon film 12 High-concentration phosphorus-doped polysilicon film

Claims (4)

[Claims] 1. A step of implanting impurities of different concentrations and / or types into at least two or more regions of a polysilicon film formed on a semiconductor substrate, and then patterning a gate electrode on the polysilicon film. A second step of forming a mask, a third step of implanting a high etching rate impurity into a region where the mask is not formed, and then etching the region where the mask is not formed, And a fourth step of forming a silicon gate electrode. 2. The method according to claim 1, wherein the impurity having a high etching rate used in the third step is phosphorus. 3. When the impurity used in the first step contains phosphorus, the concentration of phosphorus used in the third step is higher than the concentration of phosphorus used in the first step. 3. The method of manufacturing a semiconductor device according to claim 2, wherein 4. A method for manufacturing a semiconductor device, comprising forming a CMOS structure using the method for manufacturing a semiconductor device according to claim 1.