JPH06120243A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent decrease of operating speed of an LSI and the increase of power consumption in a parasitic capacitance, by eliminating the overlap of a gate electrode and a diffusion layer, and reducing a parasitic capacitance generated between the gate electrode and the diffusion layer. CONSTITUTION:A photoresist film 4 which is formed on a polycrystalline silicon film and has a pattern for forming a gate electrode is used as a mask, and phosphorus ions 5 are implanted in a P-type silicon substrate 1 via the polycrystalline silicon film 3. Thereby an N-type diffusion layer 6 is formed. The photoresist film 4 is used as a mask, and the polycrystalline silicon film 3 is etched and eliminated. Thereby a gate electrode 3a is formed. By adjusting the side etching amount of the gate electrode 3a in the above process, the overlap of the gate electrode 3a and the diffusion layer 6 is eliminated, and a parasitic capacitance is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A conventional semiconductor device manufacturing method is as follows.
As shown in FIG. 2A, a polycrystalline silicon film 3 is deposited on the silicon oxide film 2 provided on the P-type silicon substrate 1, and a photoresist film 4 is applied on the polycrystalline silicon film 3. Then, patterning is performed to form a pattern for forming a gate electrode.

Next, as shown in FIG. 2B, the polycrystalline silicon film 3 is etched using the photoresist film 4 as a mask to form a gate electrode 3a.

Next, as shown in FIG. 2C, after the photoresist film 4 is removed, phosphorus ions 5 are ion-implanted at an acceleration energy of 70 keV using the gate electrode 3a as a mask to form an N-type diffusion layer 6.

Next, as shown in FIG. 2D, heat treatment is performed to activate the N-type diffusion layer 6.

[0006]

In this conventional method of manufacturing a semiconductor device, since the gate electrode of the MOS transistor and the diffusion layer overlap (about 0.2 μm) and parasitic capacitance is generated, the LSI due to the parasitic capacitance is generated. There is a problem that the operation speed of the device decreases and power consumption occurs.

[0007]

A method of manufacturing a semiconductor device according to the present invention comprises a step of depositing a polycrystalline silicon film on an insulating film provided on the surface of a one conductivity type semiconductor substrate, and a step of depositing the polycrystalline silicon film. Forming a pattern for forming a gate electrode by applying a photoresist film thereon and patterning it; and by using the photoresist film as a mask, impurities are ion-implanted into the semiconductor substrate through the polycrystalline silicon film to have a reverse conductivity type. It includes a step of forming a diffusion layer, and a step of etching the polycrystalline silicon film again using the photoresist film as a mask to form a gate electrode.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a polycrystalline silicon film 3 having a thickness of 0.4 μm is formed on a silicon oxide film 2 for a gate oxide film provided by thermally oxidizing the surface of a P-type silicon substrate 1.
Then, a photoresist film 4 having a thickness of 1.5 μm is applied on the polycrystalline silicon film 3 and patterned to form a pattern for forming a gate electrode.

Next, as shown in FIG. 1B, with the photoresist film 4 as a mask, the reion 5 has an acceleration energy of 180 keV and a dose amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-2.
Under these conditions, ions are implanted into the P-type silicon substrate 1 through the polycrystalline silicon film 3 to form the N-type diffusion layer 6.

Next, as shown in FIG. 1C, the polycrystalline silicon film 3 is removed by etching again using the photoresist film 4 as a mask to form a gate electrode 3a. Here, the side surface of the gate electrode 3a is side-etched by a thickness corresponding to the spread by the heat treatment for activating the N-type diffusion layer 6.

Next, as shown in FIG. 1D, after the photoresist film 4 is removed, heat treatment is performed to activate the impurities in the N-type diffusion layer 6 and the ends of the gate electrode 3a and the N-type diffusion layer 6 are separated. Match the parts.

[0014]

As described above, according to the present invention, impurities are ion-implanted into a semiconductor substrate through a polycrystalline silicon film and diffused by using a photoresist film having a pattern for forming a gate electrode of a MOS transistor as a mask. After forming the layer, the photoresist film is used as a mask to etch the polycrystalline silicon film, the gate electrode is formed, and the side surface of the gate electrode is side-etched to match the spread of the diffusion layer due to activation of the diffusion layer. Since the overlap between the gate electrode and the diffusion layer can be eliminated by eliminating the parasitic capacitance due to the overlap between the gate wiring and the diffusion layer, the operation speed of the LSI can be reduced and the power consumption due to the parasitic capacitance can be prevented. is there.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip showing the process sequence for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 P-type silicon substrate 2 Silicon oxide film 3 Polycrystalline silicon film 4 Photoresist film 5 Phosphorus ion 6 N-type diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/302 J 9277-4M

Claims (1)

[Claims] 1. A step of depositing a polycrystalline silicon film on an insulating film provided on the surface of a one-conductivity-type semiconductor substrate, and applying a photoresist film on the polycrystalline silicon film and patterning it to form a gate electrode. Forming a pattern for use, a step of forming an opposite conductivity type diffusion layer by ion-implanting impurities into the semiconductor substrate through the polycrystalline silicon film using the photoresist film as a mask, and the photoresist film again. And a step of etching the polycrystalline silicon film as a mask to form a gate electrode.