JPH05211232A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the extent of a diffusion layer formed by diffusing impurities to a substrate from a polycrystalline silicon wiring, to which impurities are doped, and to improve the element isolation width dependency of element isolation breakdown strength. CONSTITUTION:The ions of impurities having the same type as a P-type semiconductor substrate 1 are implanted by high energy while using a resist pattern 5 for boring a gate oxide film 4 as a mask, and a thick P-type impurity diffusion layer 6 is formed to the deep section of the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a reverse conductivity type polycrystalline silicon formed so as to be in direct contact with a semiconductor substrate of one conductivity type, and impurities formed by diffusing impurities from the polycrystalline silicon. And a diffusion layer of opposite conductivity type.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device of this type has a structure as shown in FIG. 3, and its manufacturing method will be described. First,
On the p-type semiconductor substrate 11, the p-type diffusion layer 12 for element isolation, LO
A COS oxide film 13 and a gate oxide film 14 are formed.
Next, an opening is formed in the gate oxide film by using a lithography technique and an etching solution such as hydrofluoric acid so that the polycrystalline silicon and the semiconductor substrate are in direct contact with each other. After the photoresist is stripped off, polycrystalline silicon is vapor-deposited, n-type impurities (for example, phosphorus) are diffused in this polycrystalline silicon, and then an n-type polycrystalline silicon wiring 17 is formed by using a lithography technique. Further, an n-type impurity (phosphorus) is diffused from the n-type polycrystalline silicon wiring 17 into the p-type semiconductor substrate 11 by heat treatment to form a high concentration n-type diffusion layer 18.

[0003]

In the above-described conventional semiconductor device, since the diffusion of impurities from the polycrystalline silicon wiring into the semiconductor substrate is large, the impurity diffusion layer spreads laterally and downward. For this reason, when the element isolation width becomes smaller (less than about submicron), there is a problem that the isolation breakdown voltage is significantly lowered. On the other hand, in order to improve the isolation breakdown voltage, if the impurity concentration is suppressed or the temperature and time of the heat treatment are suppressed so as to suppress the diffusion of impurities, the polycrystalline silicon wiring and the impurity diffusion layer will be separated. However, there was a problem that the contact resistance of was high.

[0004]

The semiconductor device of the present invention comprises:
Semiconductor device having reverse conductivity type polycrystalline silicon formed on one conductivity type semiconductor substrate so as to be in contact with the semiconductor substrate, and reverse conductivity type semiconductor layer formed by impurity diffusion from the reverse conductivity type polycrystalline silicon In the above, the one-conductivity-type semiconductor layer having a higher concentration than that of the semiconductor substrate is provided at a position in contact with the lower part of the opposite-conductivity-type semiconductor layer.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings. FIG. 1 is a cross-sectional view of essential parts of a semiconductor device according to a first embodiment of the present invention.

First, a dense p-type diffusion layer 2 for element isolation 2, a LOCOS oxide film 3 (about 1 μm in film thickness), and a gate oxide film 4 (about 20 nm in film thickness) are formed on a p-type semiconductor substrate 1. Next, a photoresist pattern 5 is formed to provide an opening in the gate oxide film 4 at a desired location. After that, p with high energy and a dose amount of about 5E12 cm ^-2
-Type impurities (for example, about 200 keV of boron) are implanted through the gate oxide film 4 so that the depth of the p-type semiconductor substrate 1 is 50
A deep p-type impurity diffusion layer 6 is formed in a deep portion of about 0 nm. [FIG. 1 (a)].

Next, etching is performed with hydrofluoric acid or the like to remove the gate oxide film 4 in the opening of the photoresist pattern 5 [FIG. 1 (b)].

Then, the photoresist pattern 5 is peeled off. Next, polycrystalline silicon is chemically vapor-deposited (film thickness 40
To about 0 nm), doped with an n-type impurity (for example, phosphorus), and etched using a lithographic technique to form a polycrystalline silicon wiring 7. Then, heat treatment is performed to diffuse impurities from the polycrystalline silicon wiring 7 to form an n-type high-concentration impurity diffusion layer 8 [FIG. 1 (c)].

In the first embodiment, wiring of polycrystalline silicon was used, but in the second embodiment of the present invention, Ti, Co, W, Mo is formed on the polycrystalline silicon wiring 7 as shown in FIG. , Ta
It is also possible to use a laminated wiring 9 in which an alloy containing, or the like as a main material, a nitride of these, or a silicide of these is laminated.

[0010]

As described above, the present invention is in contact with the lower portion of the dense one conductivity type impurity diffusion layer formed by impurity diffusion from one conductivity type polycrystalline silicon wiring, or
Since the deep opposite conductivity type impurity diffusion layer is formed so as to be bitten in somewhat, it is possible to suppress the spread of the first conductivity type impurity diffusion layer, and the single conductivity type polycrystalline silicon wiring and the deep single conductivity type impurity diffusion layer are formed. Without reducing the contact resistance with
This has an effect that the isolation width dependency of the element isolation breakdown voltage can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 1, 11 p-type semiconductor substrate 2, 12 p-type diffusion layer for element isolation 3, 13 LOCOS oxide film 4, 14 gate oxide film 5 photoresist pattern 6 dark p-type impurity diffusion layer 7, 17 polycrystalline silicon wiring 8, 18 n-type high-concentration impurity diffusion layer 9 Laminated wiring

Claims (1)

[Claims] 1. A reverse-conductivity-type polycrystalline silicon formed on a one-conductivity-type base so as to be in direct contact with the semiconductor base, and impurities diffused from the reverse-conductivity-type polycrystalline silicon to be formed on the surface of the semiconductor base. A semiconductor device having a reverse conductivity type semiconductor layer, the semiconductor device being provided in the semiconductor substrate below the reverse conductivity type semiconductor layer, being in contact with the reverse conductivity type semiconductor layer and having a higher concentration than the one conductivity type semiconductor substrate. A semiconductor device having one conductivity type semiconductor layer.