JPS61202464A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61202464A JPS61202464A JP4304485A JP4304485A JPS61202464A JP S61202464 A JPS61202464 A JP S61202464A JP 4304485 A JP4304485 A JP 4304485A JP 4304485 A JP4304485 A JP 4304485A JP S61202464 A JPS61202464 A JP S61202464A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- mask
- polycrystalline silicon
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 27
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 3
- -1 boron ions Chemical class 0.000 abstract description 2
- 239000007943 implant Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009933 burial Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特Ｋ。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device.
高周波バイポーラ・トランジスタを含む半導体装置のエ
ミッタ領域並びにエミッタおよびベース電極取り出し領
域を形成する方法に関する。The present invention relates to a method of forming an emitter region and an emitter and base electrode extraction region of a semiconductor device including a high frequency bipolar transistor.
近年、集積回路を構成するバイポーラ・トランジスタは
増々高速化が要求され浅い接合と微細パターン化が進ん
できた。その結果、電極金属の侵入から最も浅いエミッ
タ接合を保護する為に１多結晶シリコンを介してエミッ
タへ不純物を拡散し、多結晶シリコン上に金属電極を形
成する方式がとられている。この方式の代表的な例を第
２図（ａ）〜＜ｆ）ｉｆｃ工程断面図として示す。In recent years, the bipolar transistors that make up integrated circuits are required to be faster and faster, and shallower junctions and finer patterns have been developed. As a result, in order to protect the shallowest emitter junction from penetration of electrode metal, a method has been adopted in which impurities are diffused into the emitter through polycrystalline silicon and a metal electrode is formed on the polycrystalline silicon. A typical example of this method is shown in FIGS. 2(a) to <f) as cross-sectional views of the ifc process.
まず、第２図（ａ）に示すように、Ｐ型半導体基板１０
１ＫＮ＋型埋込層１０２を形成した後、Ｎ型エピタキシ
ャル成長層１０３を形成する。次に素子分離絶縁膜１０
７．コレクタ抵抗を下げる為のＮ＋型拡散領域１０４．
Ｐ型具性ペース領域１０５゜ベース抵抗を低下させる目
的のＰ＋拡散領域１０６を形成する。ここで、真性ベー
ス領域１０５の濃度は１０Ｉｌｌ〜１０１７ ｃｍ−ｓ
、 ｐ＋拡散領域ｉ０６は１０２０〜１０１１０１８
Ｃでおる。全面に１０００〜１５００λ程度の絶縁膜層
１０８ｔ−形成し、ベース、エミッタ、コレクタ・コン
タクト領域部に開口を設ける。その後、厚さ１０００〜
３０００λ程度のＮ型不純物を高濃度に含む多結晶シリ
コン膜１０９を形成する。First, as shown in FIG. 2(a), a P-type semiconductor substrate 10
After forming the 1KN+ type buried layer 102, an N type epitaxial growth layer 103 is formed. Next, the element isolation insulating film 10
7. N+ type diffusion region 104 for lowering collector resistance.
P type specific space region 105° forms a P+ diffusion region 106 for the purpose of lowering the base resistance. Here, the concentration of the intrinsic base region 105 is 10Ill to 1017 cm-s
, p+ diffusion region i06 is 1020 to 1011018
It's C. An insulating film layer 108t having a thickness of approximately 1000 to 1500 λ is formed on the entire surface, and openings are provided in the base, emitter, and collector contact regions. After that, the thickness is 1000~
A polycrystalline silicon film 109 containing a high concentration of N-type impurities of about 3000λ is formed.
次に１第２図（ｂ）Ｋ示すように、フォト・レジスト１
１０を選択的に多結晶シリコン膜上に形成する。Next, as shown in FIG. 2(b)K, photoresist 1
10 is selectively formed on the polycrystalline silicon film.
次をこ、第２図（Ｃ）に示すように、このフォト・レジ
ス）１１０をマスクに多結晶シリコン膜１０９をエツチ
ングする。Next, as shown in FIG. 2C, the polycrystalline silicon film 109 is etched using the photoresist 110 as a mask.
次に、第２図（ｄ）に示すように、フォト？レジス）１
１Ｑｌｒ除去した後、窒素雰囲気中で熱処理を行ない多
結晶シリコン膜１０９から真性ベース領域１０５へＮ型
不純物を拡散してＮ 型エミッタ領域１１１を形成する
。同時にコレクタ部にもＮ＋型コレクタ領域１１２が形
成される。その後、不純物を含まない多結晶シリコン膜
１１３．電極用アルミニウム膜１１４を順に形成する。Next, as shown in FIG. 2(d), photo? Regis) 1
After removing 1Qlr, heat treatment is performed in a nitrogen atmosphere to diffuse N type impurities from the polycrystalline silicon film 109 to the intrinsic base region 105 to form an N type emitter region 111. At the same time, an N+ type collector region 112 is also formed in the collector portion. Thereafter, a polycrystalline silicon film 113 containing no impurities is formed. An aluminum film 114 for electrodes is sequentially formed.
多結晶シリコン膜１１３はベース接合を電極用アルミニ
ウムの侵入から防ぐために形成するもので膜厚は１００
０Å以下である。The polycrystalline silicon film 113 is formed to prevent the base junction from entering the electrode aluminum, and has a thickness of 100 mm.
It is 0 Å or less.
次に、第２図（ｅ）に示すように、電極用アルミニウム
膜を選択的に取り除く。Next, as shown in FIG. 2(e), the electrode aluminum film is selectively removed.
そして、最後に、第２図（０に示すように、選択的に残
した電極用アルミニウム膜１１４ｔマスクにエツチング
を行ない多結晶シリコン膜１０９゜１１３を取シ拗く。Finally, as shown in FIG. 2 (0), the selectively left electrode aluminum film 114t mask is etched to remove the polycrystalline silicon film 109° 113.
しかし、以上の様な従来方法には次の様な欠点がある。 However, the conventional methods described above have the following drawbacks.
（１） 多結晶シリコン膜１０９ｙｋエツチングする
工程でドライエツチングを用いるとベース・コンタクト
領域をエツチングしてしまう。(1) If dry etching is used in the step of etching the polycrystalline silicon film 109yk, the base contact region will be etched.
（２）ベース接合部がよシ浅くなった場合、この様な従
来方法ではペース接合を保護できない。(2) If the base joint becomes very shallow, such conventional methods cannot protect the pace joint.
また、多結晶シリコンｐＩｉＩＡ１１３をベース接合保
護の為に厚くするとコンタクト不良の原因になる。Further, if the polycrystalline silicon pIiIA 113 is made thick to protect the base junction, it may cause contact failure.
（３） 多結晶シリコン族１０９による凸凹上でアル
ミニウム膜１１４ｔパターニングしなくてはならない為
に、パターニングが難しい。(3) Patterning is difficult because the aluminum film 114t must be patterned on the unevenness formed by the polycrystalline silicon group 109.
特に、（１）と■の項目はペース接合がさらに浅くなっ
た場合に、また（３）の項目は素子がよシ微細になった
場合に重要になる。In particular, items (1) and (2) become important when the pace junction becomes shallower, and item (3) becomes important when the device becomes finer.
本発明は上記欠点を除去し、パターンの微細化と浅接合
に十分対応可能な多結晶シリコンを用いたトランジスタ
を形成することができる半導体装置の製造方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks and can form a transistor using polycrystalline silicon that can sufficiently cope with miniaturization of patterns and shallow junctions.
本発明の半導体装置の製造方法は、複数の開口を有する
絶縁膜を表面に形成した半導体基板上忙、半導体層を形
成する工程と、該半導体層上に第１酸化膜、窒化膜を順
に形成しその後両者を選択的に除去する工程と、該窒化
膜をマスクに第１導電型不純物を該半導体層に導入する
工程と、前記窒化膜をマスクに前記半導体層の一部を酸
化し、第２叡化膜を形成する工程と、マスクに使用した
前記窒化膜を除去し前記第１酸化膜を除去すると共ｔこ
第２醒化膜を残す工程と、ｉｔ＊第２酸化展をマスクに
第２導電型不純物を導入する工程と、熱処理を行なうこ
とＫよシ前記第２導電型不純物を前記半導体層から前記
半導体基板へ導入する工程と。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a semiconductor layer on a semiconductor substrate having an insulating film formed on the surface thereof, forming a semiconductor layer, and sequentially forming a first oxide film and a nitride film on the semiconductor layer. and then selectively removing both; a step of introducing a first conductivity type impurity into the semiconductor layer using the nitride film as a mask; and a step of oxidizing a part of the semiconductor layer using the nitride film as a mask. a step of forming a nitride film, a step of removing the nitride film used as a mask, removing the first oxide film and leaving a second oxide film, and using the second oxide film as a mask. a step of introducing a second conductivity type impurity; and a step of introducing the second conductivity type impurity from the semiconductor layer into the semiconductor substrate by performing heat treatment.
前記第２酸化膜を除去した後に電極用金属膜を形成する
工程と、該金属膜と前記半導体層の同一部分を選択的に
除去する工程とを含んで構成される。The method includes a step of forming an electrode metal film after removing the second oxide film, and a step of selectively removing the same portion of the metal film and the semiconductor layer.
次に、本発明について、図面を参照して説明する。第１
図（ａ）〜（２）は本発明の一実施例を説明するために
工程順に示した断面図である。Next, the present invention will be explained with reference to the drawings. 1st
Figures (a) to (2) are cross-sectional views shown in order of steps to explain one embodiment of the present invention.
まず、第１図（ａ） Ｋ示す様ＫＰ型半導体基板２０１
ＫＮ＋型埋込層２０２．Ｎ型エピタキシャル層２０３、
素子分離絶縁膜２０７．Ｐ型ペース領域２０５、ペース
抵抗を下げる為のＰＭ拡散領域２０６．コレクタ抵抗を
下げる為のＮ＋型拡散領域２０４を形成した後に、絶縁
膜２０８を形成する。絶縁膜２０８のエミッタ形成領域
、ペース並びにコレクタ電極引き出し領域に選択的に開
口を設ける。First, a KP type semiconductor substrate 201 as shown in FIG.
KN+ type buried layer 202. N-type epitaxial layer 203,
Element isolation insulating film 207. P-type pace region 205, PM diffusion region 206 for lowering pace resistance. After forming an N+ type diffusion region 204 for lowering collector resistance, an insulating film 208 is formed. Openings are selectively provided in the emitter formation region, paste, and collector electrode extraction region of the insulating film 208.
次に、第１図Φ）に示す様に、多結晶シリコン膜２０９
を形成し、さらに酸化膜２１０．窒化膜２１１を順に形
成する。この時の多結晶シリコン膜２０９の膜厚は５０
０〜２０００人、酸化膜２１０の膜厚は１００〜５００
人、窒化膜２１１の膜厚は１０００〜２０００人でおる
。Next, as shown in FIG. 1 Φ), a polycrystalline silicon film 209
is formed, and further an oxide film 210. A nitride film 211 is sequentially formed. The thickness of the polycrystalline silicon film 209 at this time is 50 mm.
0 to 2000 people, the thickness of the oxide film 210 is 100 to 500
The thickness of the nitride film 211 is between 1000 and 2000.
次に、第１図（Ｃ）に示す様に、エミッタ領域及びコレ
クタ電極引き出し領域を残し、それ以外の窒化膜２１１
．酸化ａ２１０を選択的に除去する。Next, as shown in FIG. 1(C), the emitter region and the collector electrode lead-out region are left, and the rest of the nitride film 211 is
．． Selectively remove oxidized A210.
次に、ペース・コンタクトを取るために窒化膜２１１
ｔマスクに全面にホウ素をイオン注入する。Next, a nitride film 211 is formed to make a pace contact.
Boron ions are implanted into the entire surface of the t-mask.
この時の注入エネルギーは、窒化膜２１１がマスクにな
る値、例えば３０〜４ＱＫｅＶ程度でらる。The implantation energy at this time is a value that uses the nitride film 211 as a mask, for example, about 30 to 4 QKeV.
ま九、ドース量は５Ｘ１０〜１×ｌＯＣｍ程度でるる。Also, the dose amount is about 5×10 to 1×1OCm.
次に１第１図（ｄ） Ｋ示すように１窒化膜２１２をマ
スクとして全面を酸化し多結晶シリコン膜２０９を酸化
して酸化膜２１２を形成する。この時、同時にホウ素の
イオン注入のアニールを行なう。また、ペース・コンタ
クト領域上の多結晶シリコン膜には下方のＰ＋領域２０
６からのホウ素の拡散が行なわれ、イオン注入したホウ
素と合わせて、コンタクトを取るに十分な濃度となる。Next, as shown in FIG. 1(d)K, the entire surface is oxidized using the nitride film 212 as a mask, and the polycrystalline silicon film 209 is oxidized to form an oxide film 212. At this time, annealing for boron ion implantation is simultaneously performed. In addition, the polycrystalline silicon film on the space contact region has a lower P+ region 20.
The boron from 6 is diffused, and together with the ion-implanted boron, the concentration becomes sufficient to make contact.
酸化膜２１２の膜厚は１５００人程度にする。The thickness of the oxide film 212 is approximately 1,500.
次に、第１図（ｅ） ＩＣ示す様に、窒化農場２１１を
除去し、その下の酸化膜２１０も除去する。酸化膜２１
２は、酸化膜２１０との膜厚差分だけ残る。Next, as shown in FIG. 1(e) IC, the nitride film 211 is removed, and the oxide film 210 underneath it is also removed. Oxide film 21
2 remains by the difference in thickness from the oxide film 210.
次いで、酸化膜２１２をマスクＶζ全面にヒ素をイオン
注入してエミッタ領域とコレクタ領域の多結晶シリコン
膜２０９ Ｋヒ素を導入する０次いで、窒素雰囲気中で
熱処理を行ない、エミッタ、コレクタ領域のエピタキシ
ャル領域に多結晶シリコン膜２０９からヒ素を導入して
Ｎ＋型エミッタ領域２１３およびＮ＋型拡散領域２１４
を形成する。Next, arsenic is ion-implanted into the entire surface of the oxide film 212 using a mask Vζ to introduce K arsenic into the polycrystalline silicon film 209 in the emitter and collector regions.Next, heat treatment is performed in a nitrogen atmosphere to form the epitaxial regions in the emitter and collector regions. Arsenic is introduced into the polycrystalline silicon film 209 to form an N+ type emitter region 213 and an N+ type diffusion region 214.
form.
次に、第１図（０に示す様に、酸化膜２１２を取シ除い
た後、電極用金属２１５を設ける。Next, as shown in FIG. 1 (0), after the oxide film 212 is removed, an electrode metal 215 is provided.
最後に、第１図（２）に示す様に１電極用金属２１５を
マスクに不要な多結晶シリコン膜２０９を取シ除き素子
が完成する。Finally, as shown in FIG. 1(2), the unnecessary polycrystalline silicon film 209 is removed using the metal 215 for one electrode as a mask to complete the device.
以上、説明したように本実施例によれば多結晶シリコン
膜２０９をパターニングする工程で従来方法の様にペー
ス・コンタクト領域２０６がエツチングされることがな
い。また、ペース・コンタクト部上にも、多結晶シリコ
ン膜が存在しているので、浅接合に対しても電極金属の
侵入を防止できる。さらに、電極金属は、はぼ平坦な面
上でバターニングが行なえる。As described above, according to this embodiment, the space contact region 206 is not etched in the step of patterning the polycrystalline silicon film 209 unlike in the conventional method. Further, since the polycrystalline silicon film is also present on the space contact portion, it is possible to prevent the electrode metal from penetrating into the shallow junction. Furthermore, the electrode metal can be patterned on a substantially flat surface.
なお、以上はＮＰＮトランジスタについて説明したが、
これに限定されるものではなくＰＮＰトランジスタにも
適用できることは説明するまでもない。In addition, although the above explained the NPN transistor,
Needless to say, the invention is not limited to this, and can also be applied to PNP transistors.
以上説明したとおシ１本発明によれば従来方法に較ベマ
スク目合せの回数を増加させることなく、浅接合とパタ
ーンの微細化に十分対応可能な多結晶シリコンを用いた
バイポーラ・トランジスタを形成することが可能である
。As explained above, 1. According to the present invention, a bipolar transistor using polycrystalline silicon that can sufficiently accommodate shallow junctions and finer patterns can be formed without increasing the number of mask alignments compared to conventional methods. Is possible.
第１図（ａ）〜（２）は本発明の一実施例を説明するた
めに工程順に示した断面図、第２図伽）〜（０は従来の
半導体装置の製造方法の一例を説明するために工程順に
示した新面図である。
１０１・・・・・・Ｐ型半導体基板、１０２・・・・・
・Ｎ＋聾埋込層、１０３・・・・・・Ｎ型エピタキシャ
ル層、１ｏ４・・・・・・Ｎ＋型拡散領域、１０５・・
・・・・Ｐ型ベース領域、１０６・・・・・・Ｐ＋灘拡
散領域、１０７・・・・・・素子分離絶縁膜、１０８・
・・・・・絶縁膜層、１０９・・・・・・Ｎ＋観多結晶
シリコン膜、１１０・・・・・・フォト・レジスト、１
１１・・・・・・Ｎ＋型エミッタ領域、１１２・・・・
・・Ｎ＋型コレクタ領域、１１３・・・・・・多結晶シ
リコン膜、１１４・・・・・・電極用アルミニウム膜、
２０１・・・・・・Ｐ型半導体基板、２０２・・・・・
・Ｎ＋型埋込層、２ｏ３・・・・・・Ｎ型エピタキシャ
ル層、２０４・・・・・・Ｎ＋型拡散領域、２０５・・
・・・・Ｐ型ベース領域、２ｏ６・・・・・・Ｐ＋型拡
散領域、２０７・・・・・・素子分離絶縁膜。
２０８・・・・・・絶縁膜、２ｏ９・・・・・・多結晶
シリコン膜、２１０・・・・・・酸化膜、２１１・山・
・窒化膜、２１２・・・・・・酸化膜、２１３・・・・
・・Ｎ＋型エミッタ領域、２１４Ｎ＋型拡散領域、２１
５・・・・・・電極用金属。
気へ
＋−＋為
察１回FIGS. 1(a) to (2) are cross-sectional views shown in the order of steps to explain an embodiment of the present invention, and FIGS. 101... P-type semiconductor substrate, 102...
・N+ deaf burial layer, 103...N type epitaxial layer, 1o4...N+ type diffusion region, 105...
... P type base region, 106 ... P+ nada diffusion region, 107 ... element isolation insulating film, 108.
...Insulating film layer, 109...N+ transparent polycrystalline silicon film, 110...Photoresist, 1
11...N+ type emitter region, 112...
... N+ type collector region, 113 ... polycrystalline silicon film, 114 ... aluminum film for electrode,
201...P-type semiconductor substrate, 202...
・N+ type buried layer, 2o3...N type epitaxial layer, 204...N+ type diffusion region, 205...
... P type base region, 2o6 ... P + type diffusion region, 207 ... element isolation insulating film. 208... Insulating film, 2o9... Polycrystalline silicon film, 210... Oxide film, 211 Mountain...
・Nitride film, 212...Oxide film, 213...
...N+ type emitter region, 214N+ type diffusion region, 21
5...Metal for electrode. To Ki +- + Tamesan 1 time
Claims (1)
上に、半導体層を形成する工程と、該半導体層上に第１
酸化膜、窒化膜を順に形成しその後両者を選択的に除去
する工程と、該窒化膜をマスクに第１導電型不純物を該
半導体層に導入する工程と、前記窒化膜をマスクに前記
半導体層の一部を酸化し、第２酸化膜を形成する工程と
、マスクに使用した前記窒化膜を除去し前記第１酸化膜
を除去すると共に第２酸化膜を残す工程と、該第２酸化
膜をマスクに第２導電型不純物を導入する工程と、熱処
理を行なうことにより前記第２導電型不純物を前記半導
体層から前記半導体基板へ導入する工程と、前記第２酸
化膜を除去した後に電極用金属膜を形成する工程と、該
金属膜と前記半導体層の同一部分を選択的に除去する工
程を含むことを特徴とする半導体装置の製造方法。forming a semiconductor layer on a semiconductor substrate on which an insulating film having a plurality of openings is formed; and forming a first semiconductor layer on the semiconductor layer.
a step of sequentially forming an oxide film and a nitride film and then selectively removing both; a step of introducing a first conductivity type impurity into the semiconductor layer using the nitride film as a mask; and a step of introducing a first conductivity type impurity into the semiconductor layer using the nitride film as a mask. a step of oxidizing a part of the mask to form a second oxide film; a step of removing the nitride film used as a mask and removing the first oxide film while leaving a second oxide film; a step of introducing a second conductivity type impurity using a mask as a mask; a step of introducing the second conductivity type impurity from the semiconductor layer into the semiconductor substrate by performing heat treatment; A method for manufacturing a semiconductor device, comprising the steps of forming a metal film and selectively removing the same portion of the metal film and the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4304485A JPS61202464A (en) | 1985-03-05 | 1985-03-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4304485A JPS61202464A (en) | 1985-03-05 | 1985-03-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61202464A true JPS61202464A (en) | 1986-09-08 |
Family
ID=12652893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4304485A Pending JPS61202464A (en) | 1985-03-05 | 1985-03-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61202464A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232757A (en) * | 1988-03-14 | 1989-09-18 | Sony Corp | Semiconductor device and manufacture thereof |
-
1985
- 1985-03-05 JP JP4304485A patent/JPS61202464A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232757A (en) * | 1988-03-14 | 1989-09-18 | Sony Corp | Semiconductor device and manufacture thereof |
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