JPS6074477A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To augment current amplification degree improving accuracy by a method wherein impurities are introduced utilizing a pattern edge making off the sides of heat resistant base electrode and thermally diffused to specify the base width. CONSTITUTION:A base region 16 and an emitter region 17 are formed by means of diffusion self matching process making reference to a pattern edge of an insulating film 15 formed on the sides of a base electrode 14 or another edge of the insulating film 15 formed on the base electrode 14 and the sides of the base electrode 14. Therefore the base width may be formed narrower than convertional base width since the width of said regions 16, 17 in the lateral direction may be controlled accurately. Resultantly, any carrier implanted from the emitter region 17 may be effectively absorbed into a collector region.

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to a 2-chiral bipolar t-disc and a method for manufacturing the same, and particularly to a diffusion self-alignment (1) 1r -f
The present invention relates to a lateral bipolar transistor formed by USION-8CLF-AIJ'ig+J and a method for manufacturing the same. (b) Background of the Technology A lateral bipolar transistor is based on a substrate and has an emitter and a collector formed on its surface. Therefore, since one transistor operates in the lateral direction, it is called a lateral transistor. This structure has the advantage of 2. The purpose of this invention is to make it easier to form the necessary opposite conductivity type transistors and also to form the necessary bipolar transistors in an IC formed using a MIS (Dinzoster). (C) Prior art and problems However, the conventional Cytidyl Paiborato Shinji;
As shown in the schematic cross-sectional view shown in FIG. 1, for example, an I
+', $ type Emi Tsuta area Etll! :n''pyJ Since the structure is such that the collector regions C are arranged side by side at a predetermined interval, carriers from the emitter region E (e'-
+9 injection is

Most of the carriers other than the carriers that are injected in the direction other than the direction toward the lid region C and the direction toward the collector region C; Therefore, conventional transistors have drawbacks (such as the inability to obtain a large carrier efficiency current amplification factor), and the base region B and substrate S
There is also the disadvantage that the junction capacitance fi between the two is large and the switching speed is reduced. Therefore, 3QJ (Si l 1
By drawing the lateral transistor on the substrate (cO1I Qll llll5 old; 1tor), the parasitic capacitance of the base region is removed, and by removing the base region located [from the emitter region and the collector region] A structure was devised to improve carrier transport efficiency. However, in this structure, the base electrode must be led out from the upper surface of the base region, so when the electrode is led out through the electrode contact window as usual, the emitter region and the collector must be led out. Distance between areas: 1
The base width widens significantly and the current amplification factor decreases, making it unusable. Therefore, as shown in the schematic cross-sectional view shown in FIG. A base electrode 5 is formed on the base electrode 5 using a 7 otolithography technique, and impurity ions are implanted into the P-type base region 4 by using the base electrode 5 as a mask and implanting impurity ions that are aligned with the base electrode 5 and The structure was formed by forming an n+ type emitter region 6 and an n+ type collector region 7 reaching the bottom of the base region 4. (In the figure. 1 is an insulating substrate, 2 is an isolation insulating film) However, in this conventional structure, the base width is the width of the base when forming the base electrode 5).
The base width cannot be extremely narrowed because it is limited by the critical dimension of IJ lithography technology (approximately 2C#m). The depth of the base area 4 is usually 0.4 to 0.5
It is formed in the order of [μm], so it is shallow (thin) like this.
In addition, in the case of a base region having a wide width as described above, recombination of carriers moving in the base region 4 at the upper and lower interfaces becomes effective. From these points, the conventional lateral bipolar transistor cannot be expected to have a current amplification factor close to that of a normal vertical bipolar transistor, and the value of the current amplification factor varies greatly depending on the accuracy of the lithography technology. There were also seven problems. (dl Purpose of the Invention) Therefore, in the present invention, an electrode material that can withstand high temperatures, such as polycrystalline/licon, is used for the base electrode, and when forming the base region and emitter region, the side surface of the base electrode or the corresponding Utilizing the butter 7 edge defined by the insulating film deposited on the side surface of the base electrode, P-type impurities and n-type impurities are introduced in alignment with the pattern edge, and a base region is formed by thermal diffusion means. For example, the so-called diffusion self-alignment (Diffusion
fusion Self-41ign) type lateral
The present invention provides a bipolar transistor and a method for manufacturing the same, and its purpose is to increase the current amplification factor of a lateral bipolar transistor, improve its accuracy, and facilitate the circuit configuration of a semiconductor IC. (e) Structure of the Invention In other words, the present invention includes a first one-conductivity type semiconductor layer, an opposite conductivity type semiconductor layer, and a first one-conductivity type semiconductor layer in a region defined by an insulating film on a substrate made of an insulator. a second semiconductor layer of one conductivity type having a low impurity concentration and a third semiconductor layer of one conductivity type having a low impurity concentration, and a third semiconductor layer of one conductivity type having the opposite conductivity type; A semiconductor device characterized in that an electrode layer of an opposite conductivity type is provided on top of a semiconductor layer and a second semiconductor layer of one conductivity type, and the electrode layer is of an opposite conductivity type and is in contact with both layers. A single crystal semiconductor layer is provided, the semiconductor layer is of homogeneous -tj-conductivity type, a strip-shaped electrode is formed on the -conductivity type semiconductor layer to cross the -conductivity type semiconductor layer, and a strip electrode is formed on seven sides of the electrode. An opposite conductivity type impurity is selectively introduced and implanted into the negative conductivity type semiconductor layer to be produced in alignment with the side surface of the electrode or the end surface of an insulating film disposed on the side surface of the electrode. Diffusing the conductive Wt type impurity to form an opposite conductivity type diffusion region in the -conductivity type semiconductor layer that reaches the bottom surface of the -conductivity type semiconductor layer and whose end face facing the electrode reaches a region immediately below the electrode. , C exposed on the other side of the opposite conductivity type diffusion region and the electrode.
One conductivity type impurity is introduced into the one conductivity type semiconductor layer aligned with the end face of the insulating film disposed on each side of the electrode, and the - conductivity type impurity is diffused into the opposite conductivity type diffusion region. A diffusion region of one conductivity type that reaches the bottom surface of the diffusion region of the opposite conductivity type and whose end face facing the electrode reaches a region immediately below an insulating film disposed on the side surface of the electrode in the direction is connected to the -conductivity type semiconductor layer. - forming one conductivity type diffusion region that reaches the bottom surface of the conductivity type semiconductor layer and whose end face opposite to the electrode ζ reaches a region directly under the insulating film disposed on the side surface of the electrode in the direction; The present invention relates to a method for manufacturing a semiconductor device, which includes a step of imparting a conductivity type. (f) Embodiments of the Invention The present invention will be explained below with reference to FIG. FIG. 3 is a schematic top view (A) and a schematic cross-sectional view (B) showing the main parts of an embodiment of the 2-chiral bibolar transistor of the present invention, and FIGS. and Figure 5 (
A) Mainly) is a process sectional view of a different embodiment of the manufacturing method of the present invention. Note that the same parts in FIGS. 4 and 5 above are shown with rotating blades.
As shown in Figure 1), this is a silicon dioxide (S102) film formed on a silidino substrate (not shown).
2 Insulating base layer 11 C by inter-element isolation 5102 film 12
Defined and separated thickness of 0.4 to 0.5 μm'l
It has an n-type collector region 13 made of a type 7937 layer, and on the nlJ collector region 13, the collector region J3
in direct contact with. Further, the IS is made of, for example, P1+ type polycrystalline silicon (Sl) with a width of about 1 to 2 [μm] across the collector region 13.
A base electrode 14 is disposed, and an insulating film 15 made of chemical vapor deposition (CVD)-8Io having a thickness of about 0.6 to 1 μmal is selectively disposed on the side surface of the base electrode 14.
In the IIn type collector region 13 exposed on one side of the base electrode 14, P is aligned with the end surface (pattern edge) of the CVD-5io2 insulating film 15 formed on the side surface of the A base electrode 14 (for example, in this direction). J) type base region 16 into which a type impurity is introduced and formed by thermal diffusion so that the C vertical direction reaches the bottom surface of the collector region 13 and the horizontal direction reaches the region immediately below the base electrode 14; , the base region 16
CVD-8i02 used in forming the base region in
A 7n type impurity is introduced into the end face of the insulating film 15 in a matching manner. In addition, the n-type emitter region 17 is formed by thermal diffusion so that the vertical direction reaches the bottom surface of the base region 16 and the horizontal direction reaches the region immediately below the CVP-SIO□ insulating film 15.
CvI) on the side surface of the base electrode in the direction in the n-type collector region 13 exposed on the other side of the base electrode 14.
-8 inch, n-type impurity is introduced in alignment with the end surface of the film 13, and thermal diffusion 1 reaches the bottom surface of the collector region 13 in the vertical direction and directly under the CVD-8Io insulating film 15 in the horizontal direction. It has a 01 lance-shaped collector contact area 8 formed to reach the contact area. Note that in the above structure, the base electrode 14 may be a high melting point metal into which a P-type impurity is introduced or a silicide thereof3.
．． Since the P-type impurity is introduced, even if the base electrode 14 comes into direct contact with the Rika type collector region 13, there will be no short circuit between the base and the collector during normal operation. When forming the above structure, P forming the base region 16
The type impurity may be introduced in alignment with the side surface of the base electrode 14. Furthermore, carbon coated on the side surface of the base electrode 14
V]'J insulating film is not limited to the above-mentioned 5I02 film. Next, two types of manufacturing methods for forming the lateral bipolar transistor of the present invention will be described with reference to the drawings, with reference to one embodiment of each method. Refer to FIG. 4(A) When forming the lateral bipolar transistor of the present invention, for example, a silicon (Sl) substrate (not shown) is used.
On the insulating base 21 made of the upper 5i02 film t04-05
An SOI substrate on which a non-doped single crystal SiJ layer 22 having a thickness of about [μm] is formed is prepared, and devices are formed on the single crystal 81 layer 22 using, for example, a normal selective oxidation method (LOCO8 method). A formation region is separated and defined, and the single crystal S1
After forming the element isolation S'02 film 23 that reaches the bottom of the layer 22, the single crystal Si layer 22 is coated with, for example, phosphorus (P).
"') is implanted at a dose of -10" (ATM meme) and an acceleration energy of 80 = ](+1 Q(ev: 1). , electronic beef 4. 7 recrystallized by heating and melting with a lamp, etc., 81 oxygen ions (0'') were deeply ion-implanted into the Si substrate, and 5Io2 was formed inside the 81 substrate by subsequent heat treatment. Any method is possible, or even an SO8 substrate can be used. Although element isolation was performed on the '02 film 23 film 3, the element isolation may be an air isolation structure in which the 81 layer in the area other than the element formation area is selectively removed. (b) Then, the substrate was heated to 1,050 to 1.1 iJ OCc)
The injected phosphorus (P) is uniformly redistributed by heat treatment at a temperature of approximately 30 to 60 minutes, and the monocrystalline Si layer is formed. ] type Si layer 22n and then chemical vapor deposition (
Thickness O, #1-0.5 (/I r
A non-doped polycrystalline S1 layer 24 of approximately
(tr+r1) Si, N, film 25 of about (tr+r1) is formed. Refer to FIG. I E > Houte S' 3N
4 film 25 and polycrystalline S' h 24 are selectively etched. A polycrystalline sI base electrode 24B having an S'sNt film 25 on top is formed. Enching in IE above 1.
The gas is carbon tetrafluoride (CF4, etc.) for S/sN<, and carbon tetrachloride (CCl2, etc.) for polycrystalline S+.
．． ) etc. are used. Referring to FIG. 4), after removing the resist film 26, the resist film 26 is coated on the substrate using the 10-D method, for example, Jv, 1)+1・-1[)・
:A 5ho2 film 27 of 1N'l" degree is formed. Refer to FIG.
17.1 The above C
:VI-j-ja'02 film 27 is removed sequentially from the top surface of the element region (・, +;; On the sides of the polycrystalline Si base electrode', -11, CVJ with a thickness approximately equal to the thickness (1,6 = I (/1111 J about 0) m (XV)) -:3 +02 crotch Z
7 remains. In addition, the niche gas in the above RIE process is cb゛, trifluoride (L J+!).
・8) Night time is used. In the figure, the dotted line S indicates F, and the second one is R'J.: 4g, 1. , f) 1! previous cvD-si
o2 membrane surface. Refer to FIG. 4(v) Next, the base electrode 2411 has an n-type ('= r 1 22
After selectively covering the 11th surface with the resist film 28, the base 1
1 n-type S1 layer 2 exposed on the other side of 24B
On the 211 plane, the end face of the CVD 5102 film 27 formed on the side surface of the base electrode 24B (pattern 1 - boron, which is an impurity for forming the base in alignment with the nozzle)
J3) ion implantation is performed (B is boron ion). The implantation conditions are 1, for example, a dose of 3
/7al, the implantation energy is about 30 (Key: 1).See FIG.
A heat treatment is performed at a temperature of about 0°C for a predetermined time to diffuse the implanted boron (B) and form two P-type base regions. Note that this diffusion depth is 2 P-type region 7J”n-type S1 layer 2
The depth is selected to reach the bottom surface of the base electrode 2n and to form a junction formed in the lateral direction within the direct region of the base electrode 24B, and also to a value corresponding to a desired amplification factor. Here, for example, the side surface R of the base electrode z 4 B: the end surface of the formed CVD-S 102i27 (the pattern/
The diffusion depth is set to about 2(,+c+n) in the lateral direction from the edge). The P-type base region 29 thus formed by diffusion has a concentration distribution from the pattern/edge of the cvD-sIot conversion 27 toward the junction. Referring to FIG. 4(1), a CVD-S'Ot film 27 iC%' is then formed on each side surface 1 of the base electrode 24I3.
? S'c! -1': ``-. IJ type base region 29 surface with C exposed on one side of the base electrode 24B and n type S with 'C exposed on the other side.
' In 22 N-type impurity, such as phosphorus (P), which will become the emitter and υJ rectifier contact, should be implanted at a high concentration on the n-plane.
0 to 1.0 (lO('0:l) heat treatment is performed for a constant period of time to diffuse the implanted phosphorus (P) and form II" d into the pm base region 29. An n-type Si IM 2 with type emitter region 30 as collector region f4
2 Inner ζ n″d~ type collector/contact region 31
form each. Here, the phosphorus image/implantation conditions are 2, for example, dose 5.5 x ], Q Inl
(at IIyud]. The implantation energy is about 60 (Kcv). Also, the diffusion depth of the phosphorus is determined by the force exerted on the bottom surface of the base region 29. If the junction formed in the lateral direction is CV'D'-S I O
□The depth is selected to be within the area immediately below the membrane 27 (which must not be in contact with the base electrode), and here the cvo-si
From the pattern edge of the O2 film 27, for example, O15 [μ+n
] degree. Note that, as described above, the depth of the base region 29 is formed to be about 2 [μm] from the pattern edge, so the base width wn is 1.5 [μm]. FIG. 4 (See I) Next, the S'3N4 film 25 on the polycrystalline 81 space electrode 24B is removed by a method such as phosphoric acid (H3PO4) boiling, and then P-type impurities such as boron are added to the polycrystalline SI base electrode 24B. (B) is ion-implanted (B゛1 is boron ion).The implantation conditions are 9, for example, a dose of 8x 1014 (a
tm/m), and the implantation energy is about 30 [:KeV]. During the ion implantation, boron (B) is also implanted into the surfaces of the C emitter region 30 and collector contact region 31, but the implantation amount is sufficiently lower than that of the N-type impurity implanted into these regions. does not reverse to P type. Also, there is no risk of interference with contact. followed by 90
Heat treatment is performed at a temperature of about 0 to 950°C. The boron (13) implanted into the base electrode 24B is diffused into the polycrystalline SI, and the base electrodes 2 and 1B are made of P.
form a model. In the diffusion process of γS, the diffusion coefficient in the polycrystalline 81 is nearly one order of magnitude larger than that in the single crystal layer, so the
is not diffused, nor is the impurity in the single crystal layer redistributed. Refer to FIG. 4 (N). Next, by the usual methods, an insulating film is formed, an electrode is formed, a window is formed, an electrode wiring is formed, etc., and the lateral bi-bonotransistor of the present invention is completed. do. In the figure, 732 is an insulating film, 33 is an engineered ζ ivy electrode wiring, 3
4 indicates collector electrode wiring. Note that base electrode 2
The wiring for 4B is not shown because it is connected to songs other than the R song. Next, another method of manufacturing the lateral piston resistor of the present invention will be described with reference to FIG. 5 *L for one embodiment. Refer to FIG. 5(a). This method is different from the above-mentioned method in that after the base region is formed by aligning it with the side surface of the base electrode, a CVD insulating film is formed on the side surface of the base electrode, and the CVD insulating film is aligned with the pattern edge. The method also includes the step of forming an emitter region within the base region. That is, the same method as described above is applied on an SOI substrate in which an n'H1 single crystal Si layer 22n defined and separated by an element isolation 5i02 film 23 is formed on a SiO□ insulating substrate 21 by a method similar to that of the above embodiment. The method traverses the n-type nest crystal SiM22n region. In addition, after forming a polycrystalline Si base electrode 24B having a 5isN4 film 25 on the upper surface, in the two-layer method, the top of the II type Si layer 2 exposed on one side of the base electrode 240 is selected with a resist film 28. The base electrode 24B covers the n-type Si layer 22n exposed on the other side of the gate electrode 24B.
Align it with the sides of. For example, boron (I3) ions are implanted under the same implantation conditions as in the previous embodiment. (B+ is boron ion and ion implantation region) Refer to FIG. 5(b) Next, heat treatment is performed for a predetermined time at the same temperature as in the above embodiment, and the bottom surface of the n-type 5il (W22n) is reached and directly below the base electrode 74n. A P-type base region 29 having a junction is formed in the region. Refer to FIG.
4.CVD-5+02 film 27 with desired thickness on the side surface of
form. Referring to FIG. 5), the 11-type S1 layer 22n, which will become the P-type base region 29 and the collector region, is aligned with the base/contour of the CVO-8I O□ film 27 formed on the side surface of the base electrode 2411 as in the previous embodiment. n-type impurity (e.g. phosphorus (1))
Ions are implanted at a high concentration and subjected to predetermined heat treatment to form a 1-layer junction in the P base region 29 that reaches the bottom surface of the base region 29 and is directly under the CVD-3i02 film 27. The emitter region 30 is also used as a collector region, and an nt4 type collector/contact region 31 is formed in the rl type Si layer 22n.(P+ is a phosphorus ion) Then, although not shown in the drawings, the same steps as in the previous embodiment are carried out. (g) Effects of the Invention As shown in Example 1 above, in the lateral bipolar transistor of the present invention, the base region and the emitter region are connected to the base electrode. (1) Ifu-5ion Self-Al
ign). As a result, the lateral spread dimension of these regions can be precisely controlled with an accuracy of, for example, 100 (A:I), and the C pace width can be formed to be significantly narrower than conventional methods (sub-micro 7 width is also possible). Therefore, carriers injected from the C emitter region are efficiently absorbed into the collector region.Also, in the bichiral bipolar transistor/seven star of the present invention, the base region is formed by diffusion. , an electric field corresponding to the impurity concentration distribution is generated inside the base region, and this accelerates the injected carry \゛ toward the collector, increasing the 1i1f transfer efficiency of carry 1. (It becomes a drift type) Furthermore, the total effective A base electrode is provided in contact with the base region, and the base electrode is given a conductivity type opposite to that of the collector region. As explained above, according to the present invention, the transport efficiency of 1 to 1 μL is high, and therefore the device has a high current amplification factor. A high-speed lateral bipolar transistor with small parasitic capacitance and a low parasitic capacitance is provided. Moreover, since the lateral bipolar transistor of the present invention has a simple structure, a pAIS+transistor or It is possible to coexist with a vertical bipolar transistor. Therefore, the present invention has the effect of simplifying the circuit configuration of a semiconductor IC. It can also be formed with the opposite conductivity type.

[Brief explanation of drawings]

1 and 2 are schematic cross-sectional views of a conventional 2-chiral bipolar transistor, and FIG. 3 is a schematic top view (A) showing the main parts of an embodiment of the 2-chiral bipolar transistor of the present invention. In the schematic sectional view (B), FIGS. 4(A) to 4(N) and FIGS. 5(A) to 5) are process sectional views of different embodiments of the manufacturing method of the present invention. In the figure, 11 is slo, an insulating substrate, 12 is an element isolation 5I02 film, 13 is an n-type collector region, 14 is a P-type polycrystalline/recon base electrode, and 15 is a chemical vapor grown SIO□ insulating film 216. P-type base region, 17 is n'' type emitter region, 18 is n''z type collector contact region, 21
is sio, an insulating substrate, 22 is a single crystal silicon layer, 22n
23 is an n-type single crystal silicon layer, 23 is an element isolation 5io2 film, 24 is a non-doped polycrystalline silicon layer, 24B is a polycrystalline silicon paste electrode, 25 is a windowed silicon film, 26.
28 is a resist film, 27 is a chemical vapor deposition 5iot film, 2
9 is a P-type base region, 30 (n''pfjlpfjl emitter region, medium-sized collector contact region 2W is the width of the chemical vapor grown 5ift film + 'W'l+ is the base width. 411121 Figure 4

Claims (1)

[Scope of Claims] 1. A first one-conductivity type semiconductor layer, an opposite conductivity type semiconductor layer, and a second one-conductivity type semiconductor layer having a lower impurity concentration than the first one-conductivity type semiconductor layer, on a substrate made of an insulator. A semiconductor layer having a semiconductor layer and a third semiconductor layer of one conductivity type in order from one side, and a semiconductor layer of opposite conductivity type that is directly in contact with the single conductivity type semiconductor layer and the second semiconductor layer of one conductivity type on the top of the opposite conductivity type single conductor layer and the second semiconductor layer of one conductivity type. A semiconductor device comprising an electrode layer. 2. A defined and separated single-crystal semiconductor layer is provided on an insulating substrate, and the semiconductor layer is of a uniform conductivity type. A strip-shaped electrode crossing the -conductivity type semiconductor layer is formed on the -conductivity type semiconductor layer, and a band-shaped electrode is formed on the -conductivity type semiconductor layer that is exposed on one side of the N-pole, and is selectively attached to the side surface of the electrode or the electrode. An opposite conductivity type impurity is introduced in alignment with the end face of the insulating film disposed on the side surface, and the opposite conductivity type impurity is diffused into the -conductivity type semiconductor layer until it reaches the bottom surface of the -conductivity type semiconductor layer and the opposite conductivity type impurity is introduced. A reverse conductivity type diffusion region whose end face facing the electrode reaches a region immediately below the electrode is formed, and the opposite conductivity type diffusion region and the other side of the electrode (11
Introducing impurities of one conductivity type into the exposed semiconductor layer of one conductivity type in alignment with the end faces of the insulating films disposed on the respective sides of the electrodes, and diffusing the -conductivity type impurities,
A diffusion region of one conductivity type that reaches the bottom surface of the diffusion region of the opposite conductivity type within the diffusion region of the opposite conductivity type, and whose end face facing the electrode reaches a region immediately below the insulating film disposed on the side surface of the electrode in the direction. −
forming one conductivity type diffusion region in the conductivity type semiconductor layer, each reaching the bottom surface of the conductivity type semiconductor layer and having an end face facing the electrode reaching a region immediately below an insulating film disposed on a side surface of the electrode in the direction; 1. A method for manufacturing a semiconductor device, which further comprises the step of imparting a reverse conductivity type to the electrode.