JPH01272153A - Manufacture of guard ring - Google Patents

Manufacture of guard ring

Info

Publication number
JPH01272153A
JPH01272153A JP10154988A JP10154988A JPH01272153A JP H01272153 A JPH01272153 A JP H01272153A JP 10154988 A JP10154988 A JP 10154988A JP 10154988 A JP10154988 A JP 10154988A JP H01272153 A JPH01272153 A JP H01272153A
Authority
JP
Japan
Prior art keywords
impurity
guard ring
type
semiconductor substrate
epitaxial growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10154988A
Other languages
Japanese (ja)
Inventor
Haruhiko Yamamoto
治彦 山本
Mitsuhide Maeda
前田 光英
Yasunori Miyamoto
宮本 靖典
Takuya Komoda
卓哉 菰田
Kazuyuki Tomii
富井 和志
Yuji Suzuki
裕二 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP10154988A priority Critical patent/JPH01272153A/en
Publication of JPH01272153A publication Critical patent/JPH01272153A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a deep guard ring in a short thermal diffusion time by evaporating a second conductivity type impurity onto the surface of a semiconductor substrate, shaping a first conductivity type epitaxial growth layer, diffusing the second conductivity type impurity up to the buried region of the epitaxial growth layer from a section just above the buried region and forming the guard ring. CONSTITUTION:An oxide film 6 is shaped onto the surface of an N<-> type low- concentration impurity semiconductor substrate 3, impurity evaporating windows are bored, and a P-type impurity is evaporated onto the surface of the semiconductor substrate 3. The oxide film 6 is removed, an epitaxial growth 3 layer 8 having the same type and the same resistivity as the substrate 3 is deposited, and P<+> type buried regions 1 are formed. The surface of the epitaxial growth layer 8 is oxidized, an oxide film 9 is shaped, and impurity evaporating windows 10 are bored to sections just above the previously formed P<+> type buried regions 1. A P-type impurity is evaporated to the epitaxial growth layer 8 through the impurity evaporating windows 10, and the P-type impurity is diffused up to the buried regions 1 through a thermal diffusion process, thus forming guard rings 2.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体素子の高耐圧化のために用いられるガ
ードリングの製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a guard ring used for increasing the voltage resistance of semiconductor devices.

[従来の技術] 従来、半導体素子の高耐圧化を達成するために、第6図
に示すように、半導体基板3の表面に主接合領域5より
も拡散長の深いガードリング2を設ける構造が広く採用
されている。これは、ガードリング2の存在により空乏
領域4を広げて平面接合に近付けることにより、電界集
中の起こりやすい部分をなくすためである。
[Prior Art] Conventionally, in order to achieve a high breakdown voltage of a semiconductor element, as shown in FIG. Widely adopted. This is because the presence of the guard ring 2 widens the depletion region 4 to bring it closer to a planar junction, thereby eliminating areas where electric field concentration is likely to occur.

[発明が解決しようとする課題] しかしながら、一般的な熱拡散工程で形成したガードリ
ング構造では、P型の高濃度不純物拡散領域よりなるガ
ードリング2からN型の低濃度不純物半導体基板3へ延
びる空乏領域4に曲率の小さい部分が生じ、電圧を印加
すると、この部分に電界が集中して、接合の降伏が容易
に起こり、耐圧を低下させるという問題があった。また
、深いガードリング2を形成するためには、通常、長時
間の熱拡散工程が必要である1例えば、拡散温度が11
50℃でガードリング2の拡散深さを10〜20μ糟と
する場合に必要な拡散時閉は1〜2日である。このよう
な長時間の熱拡散工程を行うと、不純物の再分布によっ
て絶縁酸化膜等が汚染され、耐圧低下の原因になる。さ
らに、長時間の高温処理で半導体基板3が反り、マスク
アライメント精度が低下するという問題も生じる。
[Problems to be Solved by the Invention] However, in the guard ring structure formed by a general thermal diffusion process, the guard ring 2 consisting of the P-type high concentration impurity diffusion region extends to the N-type low concentration impurity semiconductor substrate 3. There is a problem in that a portion with a small curvature is generated in the depletion region 4, and when a voltage is applied, an electric field is concentrated in this portion, easily causing breakdown of the junction and lowering the withstand voltage. Furthermore, in order to form a deep guard ring 2, a long thermal diffusion process is usually required.
When the diffusion depth of the guard ring 2 is 10 to 20 μm at 50° C., the required diffusion time is 1 to 2 days. If such a long thermal diffusion process is performed, the insulating oxide film etc. will be contaminated due to the redistribution of impurities, causing a decrease in breakdown voltage. Furthermore, there is also the problem that the semiconductor substrate 3 is warped due to the long-term high-temperature treatment, resulting in a decrease in mask alignment accuracy.

本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、ガードリング領域近傍の空乏層
の曲率を大きくして高耐圧化を図り、しかも短い拡散時
間で形成することが可能なガードリングの製造方法を提
供することにある。
The present invention has been made in view of these points, and its purpose is to increase the curvature of the depletion layer near the guard ring region to increase the breakdown voltage, and to form the depletion layer in a short diffusion time. An object of the present invention is to provide a method for manufacturing a guard ring that enables the following.

[課題を解決するための手段] 本発明に係るガードリングの製造方法にあっては、上記
の課題を解決するために、第6図に示すように、第1の
導電型(N−型)の半導体基板3における表面の主接合
領域5の外周部分に第2の導電型(P中型)のガードリ
ング2を備えた高耐圧半導体素子の製造方法において、
第1図乃至第5図に示すように、半導体基板3の表面に
第2の導電型(P中型)の不純物を蒸着した後、第1の
導電型(N″″型)のエピタキシャル成長層8を形成す
ることにより第2の導電型(P中型)の埋め込み領域1
を予め形成しておき、その埋め込み領域1の真上部分か
ら第2の導電型(N−型)の不純物を埋め込み領域1に
達するまで拡散してガードリング2を形成することを特
徴とするものである。
[Means for Solving the Problems] In order to solve the above problems, in the method for manufacturing a guard ring according to the present invention, as shown in FIG. In the method of manufacturing a high voltage semiconductor device, the semiconductor substrate 3 includes a guard ring 2 of a second conductivity type (P medium type) on the outer periphery of the main bonding region 5 on the front surface of the semiconductor substrate 3,
As shown in FIGS. 1 to 5, after impurities of the second conductivity type (P medium type) are deposited on the surface of the semiconductor substrate 3, an epitaxial growth layer 8 of the first conductivity type (N'''' type) is formed. By forming the second conductivity type (P medium type) buried region 1
is formed in advance, and an impurity of the second conductivity type (N- type) is diffused from directly above the buried region 1 until it reaches the buried region 1 to form the guard ring 2. It is.

[作用] 本発明にあっては、このように、第1の導電型の半導体
基板3の表面に第2の導電型の不純物拡散工程によりガ
ードリング2を形成する前に、第2の導電型の不純物蒸
着工程と、第1の導電型のエピタキシャル成長工程とを
行うことにより、第1の導電型の半導体基板3の表面に
第2の導電型の埋め込み領域1を予め形成しであるので
、熱拡散工程による第2の不純物拡散領域が第2の導電
型の埋め込み領域1とつながって、深いガードリング2
を短い熱拡散時間で形成できるものである。
[Function] In the present invention, as described above, before the guard ring 2 is formed on the surface of the semiconductor substrate 3 of the first conductivity type by the impurity diffusion process of the second conductivity type, the second conductivity type is The buried region 1 of the second conductivity type is formed in advance on the surface of the semiconductor substrate 3 of the first conductivity type by performing the impurity vapor deposition step and the epitaxial growth step of the first conductivity type. The second impurity diffusion region formed by the diffusion process is connected to the second conductivity type buried region 1, forming a deep guard ring 2.
can be formed in a short thermal diffusion time.

[実施例] 第1図は本発明の製造方法により製造されたガードリン
グの断面図であり、第2図乃至第5図は本発明の製造方
法の各工程を説明するための断面図である。以下、各工
程について説明する。
[Example] Figure 1 is a cross-sectional view of a guard ring manufactured by the manufacturing method of the present invention, and Figures 2 to 5 are cross-sectional views for explaining each step of the manufacturing method of the present invention. . Each step will be explained below.

まず、第2図に示すように、N−型の低濃度不純物半導
体基板3の表面を酸化して、二酸化ケイ素よりなる酸化
膜6を形成し、周知のフォトリソグラフ工程とエツチン
グ工程を経て、不純物蒸着窓7を開口する。この不純物
蒸着窓7を介して、半導体基板3の表面にP型の不純物
を蒸着する。
First, as shown in FIG. 2, the surface of an N-type low-concentration impurity semiconductor substrate 3 is oxidized to form an oxide film 6 made of silicon dioxide, and then the impurity is etched through a well-known photolithography process and an etching process. The vapor deposition window 7 is opened. A P-type impurity is deposited on the surface of the semiconductor substrate 3 through the impurity deposition window 7 .

次に、酸化膜6を除去した後、半導体基板3と同型同抵
抗率のエピタキシャル成長層8を堆積し、第3図に示す
ように、P中型の埋め込み領域1を形成する。エピタキ
シャル成長層8の表面を酸化して、二酸化ケイ素よりな
る酸化膜9を形成し、周知のフォトリソグラフ工程とエ
ツチング工程を経て、第4図に示すように、不純物蒸着
窓10を先に形成したP中型の埋め込み領域1の真上に
開口する。この不純物蒸着窓10を介して、第5図に示
すように、エピタキシャル成長層8にP型の不純物を蒸
着する。そして、熱拡散工程を経て、下部の埋め込み領
域1に十分到達するようにP型の不純物を拡散させるこ
とにより、第1図に示すように、ガードリング2を形成
する。
Next, after removing the oxide film 6, an epitaxial growth layer 8 having the same type and resistivity as the semiconductor substrate 3 is deposited to form a P medium-sized buried region 1, as shown in FIG. The surface of the epitaxial growth layer 8 is oxidized to form an oxide film 9 made of silicon dioxide, and then a well-known photolithography process and an etching process are performed to form a P layer with an impurity vapor deposition window 10 previously formed, as shown in FIG. It opens directly above the medium-sized buried region 1. A P-type impurity is deposited on the epitaxial growth layer 8 through this impurity deposition window 10, as shown in FIG. Then, through a thermal diffusion process, the P-type impurity is diffused so as to sufficiently reach the lower buried region 1, thereby forming a guard ring 2 as shown in FIG.

このようにして形成されたガードリング2は最深部が半
導体基板3の表面と平行な方向に平面的に広がっている
ので、形成される空乏領域4の曲率は大きく、接合の降
伏電圧は高くなる。また、同じ拡散深さのガードリング
2を形成する場合に、従来例のように熱拡散工程のみで
形成するよりも拡散時間は思くて済む、したがって、第
6図に示す主接合領域5を形成する際のP十領域の拡散
条件と、ガードリング2の拡散条件とが同じであれば、
これらの拡散工程を同時に実施することができる。
Since the guard ring 2 formed in this way has its deepest part spread planarly in a direction parallel to the surface of the semiconductor substrate 3, the curvature of the formed depletion region 4 is large and the breakdown voltage of the junction is high. . In addition, when forming the guard ring 2 with the same diffusion depth, the diffusion time is shorter than when forming it only by a thermal diffusion process as in the conventional example. Therefore, the main bonding region 5 shown in FIG. If the diffusion conditions for the P10 region and the guard ring 2 during formation are the same,
These diffusion steps can be performed simultaneously.

[発明の効果] 本発明のガードリングの製造方法にあっては、上述のよ
うに、第1の導電型の半導体基板の表面に第2の導電型
の不純物拡散工程によりガードリングを形成する前に、
第2の導電型の不純物蒸着工程と、第1の導電型のエピ
タキシャル成長工程とを行うことにより、第1の導電型
の半導体基板の表面に第2の導電型の埋め込み領域を予
め形成しであるので、熱拡散工程による第2の不純物拡
散領域が第2の導電型の埋め込み領域とつながって、深
いガードリングを短い熱拡散時間で形成できるという利
点がある。また、このように、ガードリングの形成に必
要な熱拡散時間が短くなることにより、不純物の再分布
による汚染、半導体基板の反り等の問題も改善すること
ができる。さらに、本発明の方法により形成されたガー
ドリングは、最深部の形状が半導体基板の表面と平行な
方向に広がっているので、空乏領域の曲率が大きくなり
、接合の降伏電圧が高くなるという効果がある。
[Effects of the Invention] As described above, in the guard ring manufacturing method of the present invention, before forming the guard ring on the surface of the first conductivity type semiconductor substrate by the second conductivity type impurity diffusion step. To,
A buried region of the second conductivity type is formed in advance on the surface of the semiconductor substrate of the first conductivity type by performing an impurity deposition step of the second conductivity type and an epitaxial growth step of the first conductivity type. Therefore, there is an advantage that the second impurity diffusion region formed by the thermal diffusion process is connected to the buried region of the second conductivity type, and a deep guard ring can be formed in a short thermal diffusion time. Furthermore, by shortening the thermal diffusion time required to form the guard ring, problems such as contamination due to redistribution of impurities and warping of the semiconductor substrate can be improved. Furthermore, since the shape of the deepest part of the guard ring formed by the method of the present invention extends in a direction parallel to the surface of the semiconductor substrate, the curvature of the depletion region becomes large and the breakdown voltage of the junction increases. There is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の製造方法により製造されたガードリン
グの断面図、第2図乃至第5図は本発明の製造方法の各
工程を説明するための断面図、第6図は従来方法により
製造されたガードリングの断面図である。 1は埋め込み領域、2はガードリング、3は半導体基板
、4は空乏領域、5は主接合領域、6゜9は酸化膜、7
.10は不純物蒸着窓、8はエピタキシャル成長層であ
る。
FIG. 1 is a sectional view of a guard ring manufactured by the manufacturing method of the present invention, FIGS. 2 to 5 are sectional views for explaining each step of the manufacturing method of the present invention, and FIG. 6 is a sectional view of a guard ring manufactured by the conventional method. FIG. 3 is a cross-sectional view of the manufactured guard ring. 1 is a buried region, 2 is a guard ring, 3 is a semiconductor substrate, 4 is a depletion region, 5 is a main junction region, 6°9 is an oxide film, 7
.. 10 is an impurity vapor deposition window, and 8 is an epitaxial growth layer.

Claims (1)

【特許請求の範囲】[Claims] (1)第1の導電型の半導体基板における表面の主接合
領域の外周部分に第2の導電型のガードリングを備えた
高耐圧半導体素子の製造方法において、半導体基板の表
面に第2の導電型の不純物を蒸着した後、第1の導電型
のエピタキシャル成長層を形成することにより第2の導
電型の埋め込み領域を予め形成しておき、その埋め込み
領域の真上部分から第2の導電型の不純物を埋め込み領
域に達するまで拡散してガードリングを形成することを
特徴とするガードリングの製造方法。
(1) In a method for manufacturing a high-voltage semiconductor device including a guard ring of a second conductivity type on the outer periphery of a main bonding region on a surface of a semiconductor substrate of a first conductivity type, a guard ring of a second conductivity type is provided on the surface of the semiconductor substrate. After depositing the type impurity, a buried region of the second conductive type is formed in advance by forming an epitaxial growth layer of the first conductive type, and a buried region of the second conductive type is formed directly above the buried region. A method for manufacturing a guard ring, which comprises forming a guard ring by diffusing impurities until it reaches a buried region.
JP10154988A 1988-04-25 1988-04-25 Manufacture of guard ring Pending JPH01272153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10154988A JPH01272153A (en) 1988-04-25 1988-04-25 Manufacture of guard ring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10154988A JPH01272153A (en) 1988-04-25 1988-04-25 Manufacture of guard ring

Publications (1)

Publication Number Publication Date
JPH01272153A true JPH01272153A (en) 1989-10-31

Family

ID=14303512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10154988A Pending JPH01272153A (en) 1988-04-25 1988-04-25 Manufacture of guard ring

Country Status (1)

Country Link
JP (1) JPH01272153A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996026547A1 (en) * 1995-02-20 1996-08-29 Rohm Co., Ltd. Semiconductor device with guard ring and process for its production

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996026547A1 (en) * 1995-02-20 1996-08-29 Rohm Co., Ltd. Semiconductor device with guard ring and process for its production

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