JPS6149471A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6149471A JPS6149471A JP17209484A JP17209484A JPS6149471A JP S6149471 A JPS6149471 A JP S6149471A JP 17209484 A JP17209484 A JP 17209484A JP 17209484 A JP17209484 A JP 17209484A JP S6149471 A JPS6149471 A JP S6149471A
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- oxidation
- mask
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 7
- 230000001133 acceleration Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 16
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 239000012535 impurity Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法、特に超高周波トランジ
スタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a super high frequency transistor.
（ロ）従来の技術
超高周波用トランジスタとしてしゃ断周波数を高くする
には微小な電極と狭いベース幅を必要とするが、ベース
幅を狭くすることはベース抵抗を高くしてトランジスタ
の性能指数を悪くする。(b) Conventional technology Increasing the cutoff frequency of an ultra-high frequency transistor requires a minute electrode and a narrow base width, but narrowing the base width increases the base resistance and worsens the transistor's figure of merit. do.
従来第２図（イ）に示すようなトランジスタでは、各領
域上の酸化膜０２を窓開けしてベース電極０３）、エミ
ッタ電極Ｑ４１を形成していた。このような場合、エミ
ッタ電極αａは上記窓穴を覆うために、ベース電極０３
）はエミッタ電極（１４１と短絡しないだけの距離をと
らなければならない。そのためにベース抵抗を低減する
のが困難であった。この問題を改良するために第２図（
ロ）に示した構造のトランジスタが提案されている。（
特許出願公告、昭５９−８４このトランジスタは、半導
体基板Ｃυにベース領域ｃ２つとエミッタ領域（ハ）を
形成した後、多結晶シリコン層を堆積する。次にこれを
パターニングすることによりエミッタ電極（２）を形成
し、酸化膜（ハ）で被膜する。次にこれをマスクとして
セルファライン法によりベース領域（２２１上の酸化膜
を除去してベース領域（２ｚ内に高濃度のベースコンタ
クト領域弼を形成する。この後、蒸着アルミニウムより
成るベース電極□□□を形成する。Conventionally, in a transistor as shown in FIG. 2(a), a base electrode 03) and an emitter electrode Q41 were formed by opening the oxide film 02 on each region. In such a case, the emitter electrode αa is connected to the base electrode 03 in order to cover the window hole.
) must be far enough away from the emitter electrode (141) to avoid short-circuiting.For this reason, it has been difficult to reduce the base resistance.In order to improve this problem, Fig. 2 (
A transistor with the structure shown in (b) has been proposed. (
Patent Application Publication, 1984-1984 This transistor is manufactured by forming two base regions c and an emitter region (c) on a semiconductor substrate Cυ, and then depositing a polycrystalline silicon layer. Next, this is patterned to form an emitter electrode (2) and covered with an oxide film (c). Next, using this as a mask, the oxide film on the base region (221) is removed by the self-line method to form a highly concentrated base contact region in the base region (2z).After this, a base electrode made of vapor-deposited aluminum is formed. Form □.
斯る構造によれば、エミッタ電極＜２４）とベース電極
（５）間の距離を短絡しない最小の距離に設定でき、さ
らに高濃度のベースコンタクト領域（ホ）と相まつて最
小のベース抵抗を得ることができる。According to such a structure, the distance between the emitter electrode (<24) and the base electrode (5) can be set to the minimum distance that will not cause a short circuit, and combined with the highly concentrated base contact region (e), the minimum base resistance can be obtained. be able to.
（ハ）発明が解決しようとする問題点
しかしながら、斯上した構造のトランジスタを形成する
ためＫはベースとエミッタを形成するのに４ｍ々（ＩＩ
）−ｒスフを必要とし、さらにベースコンタクト領域（
２６）を形成する時のマスクとなるエミッタ電極（２４
１を形成するのに複数の工程を必要とする。(c) Problems to be solved by the invention However, in order to form a transistor with the above structure, K is 4 m (II) to form the base and emitter.
)-r suffix, and also requires a base contact area (
The emitter electrode (24) serves as a mask when forming the emitter electrode (26).
Multiple steps are required to form 1.
そのため全工程数が多くなり、コスト高になるという欠
点があった。Therefore, there is a drawback that the total number of steps increases and the cost increases.
に）問題点を解決するだめの手段
本発明は斯上した欠点に鑑みてなされ、耐酸化性膜をマ
スクとして用いてセルファライン法でベースコンタクト
領域とベース領域を形成し、さらＫこれを用いて選択酸
化した後の酸化膜をマスクとしてセルファライン法でエ
ミッタ領域を形成することにより従来の欠点を除去する
ことにある。B) Means for solving the problem The present invention was made in view of the above-mentioned drawbacks, and the base contact region and the base region are formed by the self-line method using an oxidation-resistant film as a mask, and The purpose of this invention is to eliminate the drawbacks of the conventional method by forming an emitter region by the self-line method using the oxide film selectively oxidized by the method as a mask.
（ホ）作用
本発明によれば耐酸化性膜を直接的あるいは間接的にマ
スクとして用いることにより、単一のマスクでセルファ
ライン法によりトランジスタの各領域を微細に且つ正確
に簡単な工程で形成できる。(E) Function According to the present invention, by directly or indirectly using an oxidation-resistant film as a mask, each region of a transistor can be formed finely and accurately in a simple process using a single mask using the self-line method. can.
（へ）実施例
第１図（イ）〜（ト）は本発明を工程順に示した断面図
である。(F) Embodiment FIGS. 1A to 1G are sectional views showing the present invention in the order of steps.
本発明の第１の工程は第１図（イ）に示す如く、半導体
基板（１）表面に薄い酸化膜（２）を形成し、トランジ
スタのエミッタとなるべき領域上の酸化膜に耐酸化性膜
（３）を付着する工程である。半導体基板としてＮ型の
基板（１）を用い、薄い酸化膜（２）はあらかじめ基板
（１）表面に形成した比較的厚い酸化膜（２）をエツチ
ングしてトランジスタの形成される領域の基板（１）表
面を露出した後に熱酸化もしくはＣＶＤ法等で約３０Ｏ
Ａの厚さに形成する。耐酸化性膜（３）としては窒化シ
リコンを用い、これをＣＶＤ法等により約３０ＯＡの厚
さに堆積した後にパターニングしてトランジスタのエミ
ッタとなるべき領域上に幅約５μでエミッタと同形状の
シリコン窒化膜（３）を形成する。この時のパターニン
グは後の工程で形成するエミッタ領域に間接的にマスク
として作用するので、このトランジスタの特性を決める
非常に重要な工程となる。The first step of the present invention is to form a thin oxide film (2) on the surface of a semiconductor substrate (1), as shown in FIG. This is the step of attaching the film (3). An N-type substrate (1) is used as the semiconductor substrate, and a thin oxide film (2) is formed by etching a relatively thick oxide film (2) previously formed on the surface of the substrate (1) to form a thin oxide film (2) in the area where the transistor is to be formed. 1) After exposing the surface, it is heated to about 30O by thermal oxidation or CVD method.
Form to thickness A. Silicon nitride is used as the oxidation-resistant film (3), which is deposited to a thickness of about 30 OA by CVD, etc., and then patterned to form a film with a width of about 5 μm and the same shape as the emitter on the region that will become the emitter of the transistor. A silicon nitride film (3) is formed. The patterning at this time indirectly acts as a mask for the emitter region that will be formed in a later step, so it is a very important step that determines the characteristics of this transistor.
本発明の第２の工程は第１図の）に示す如く、シリコン
窒化膜（３１をマスクとしてイオン注入することにより
Ｐ 型のベースコンタクト領域（４）を形成する工程で
ある。不純物イオンとしてボロンを用い、これを加速電
圧１５ＫｅＶ程度で基板（１）表面に打込むと厚い酸化
膜（２）とシリコン窒化膜（３）はマスクとし作用する
が、薄い酸化膜（２）は通過するためこの領域の基板（
１）表面にベースコンタクト領域（４）を形成すること
ができる。この後第１図（ハ）に示す如く、熱処理によ
りベースコンタクト領域（４）を深さ２μ程度までドラ
イブインする。The second step of the present invention is to form a P-type base contact region (4) by implanting ions using a silicon nitride film (31 as a mask) as shown in FIG. 1. Boron is used as an impurity ion. When this is implanted into the surface of the substrate (1) at an accelerating voltage of about 15 KeV, the thick oxide film (2) and silicon nitride film (3) act as a mask, but the thin oxide film (2) passes through. Area substrate (
1) A base contact region (4) can be formed on the surface. Thereafter, as shown in FIG. 1(c), the base contact region (4) is driven in to a depth of about 2 μm by heat treatment.
本発明の第３の工程は第１図に）に示す如く、第２の工
程より更に加速電圧を上げてイオン注入することにより
Ｐ型のベース領域（５）を形成する工程である。不純物
イオンとしてボロンを用い、これを加速電圧３５ＫｅＶ
程度で基板（１）表面に打込むと厚い酸化膜（２）はマ
スクとして作用するが、薄い酸化膜（２）とシリコン窒
化膜（３）及びシリコン窒化膜（３）の付着した領域の
薄い酸化膜（２）は通過して基板（１）表面に達する。As shown in FIG. 1, the third step of the present invention is a step of forming a P-type base region (5) by performing ion implantation at a higher acceleration voltage than in the second step. Boron is used as an impurity ion, and it is accelerated at a voltage of 35 KeV.
The thick oxide film (2) acts as a mask when implanted into the surface of the substrate (1) to a certain extent. The oxide film (2) passes through and reaches the surface of the substrate (1).
そのため第２の工程で不純物がドープされなかったシリ
コン電化膜（３）下の領域にベースコンタクト領域（４
）を接続するように浅くベース領域（５）を形成するこ
とができる。Therefore, the base contact region (4) is applied to the region under the silicon electrified film (3) that was not doped with impurities in the second step.
) can be formed shallowly to connect the base region (5).
本発明の第４の工程（よ第１図（ホ）（（示す如く、／
リコン窒化膜（３）をマスクとして選択酸化することに
よりシリコン窒化膜（３）が付着した領域以外の酸化膜
を厚（成長する工程である。シリコン窒化膜（３）が付
着した領域以外の酸化膜の厚さは少なくとも第５の工程
でイオン注入する際にマスクとじて作用する様に形成す
る。なおこの時に第３の工程で形成したペース領域（５
）のアニールと深さ０．３μ程度までドライブインする
工程とをかねる。The fourth step of the present invention (as shown in FIG.
This is a process in which the silicon nitride film (3) is used as a mask to selectively oxidize the oxide film in areas other than the silicon nitride film (3). The thickness of the film is determined at least so that it acts as a mask during ion implantation in the fifth step.At this time, the paste region (5
) and the drive-in process to a depth of about 0.3μ.
本発明の第５の工程は第１図（へ）に示す如く、シリコ
ン窒化膜（３）を除去してイオン注入することに＋
よりＮ 型のエミッタ領域（６）を形成する工程である
。シリコン窒化膜（３）は例えば熱リン酸等により除去
する。不純物イオンとしてヒ素もしくはアンチモン等の
Ｎ型不純物を用い、これを加速電圧２０ＫｅＶ程度で基
板（１）表面に打込むとシリコン窒化膜（３）を除去し
た跡の酸化膜は通過するがその他の領域では厚い酸化膜
がマスクとして働く。そのためペース領域（５）内に深
さ約０．１μのエミッタ領域（６）を形成できる。The fifth step of the present invention, as shown in FIG. 1(f), is a step of removing the silicon nitride film (3) and implanting ions to form an N type emitter region (6) using +. The silicon nitride film (3) is removed using, for example, hot phosphoric acid. When an N-type impurity such as arsenic or antimony is used as an impurity ion and is implanted into the surface of the substrate (1) at an accelerating voltage of about 20 KeV, it passes through the oxide film left after removing the silicon nitride film (3), but does not pass through other areas. In this case, a thick oxide film acts as a mask. Therefore, an emitter region (6) with a depth of approximately 0.1 μm can be formed within the pace region (5).
本発明の第６の工程は第１図（ト）に示す如く、ベース
コンタクト領域（４）とエミッタ領域（６）上の酸化膜
（２）を窓開けし、周知の蒸着技術等を用いて蒸着アル
ミニウムよりなる金属電極（７）を形成する工程である
。The sixth step of the present invention is to open the oxide film (2) on the base contact region (4) and the emitter region (6) as shown in FIG. This is a step of forming a metal electrode (7) made of vapor-deposited aluminum.
本発明によれば、シリコン窒化膜（３）をマスクを用い
てパターニングすればトランジスタの各領域はこれを直
接的もしくは間接的にマスクとしたセルファライン方式
により形成できる。このことはペース領域（５）とエミ
ッタ領域（６）を微細に且つ正確 ゛にしか
も簡単に形成することが可能になる。微細に且つ正確に
形成できることはエミッタ接合容量を小さくすることが
でき、またペース端子取出しは高濃度のベースコンタク
ト領域（４）を介して取り出すので金属電極（７）との
良好なオーミック接触と相まって最小のベース抵抗を得
ることができる。According to the present invention, by patterning the silicon nitride film (3) using a mask, each region of the transistor can be formed by a self-line method using the silicon nitride film (3) directly or indirectly as a mask. This makes it possible to form the pace region (5) and the emitter region (6) finely, precisely, and easily. The fact that it can be formed finely and accurately makes it possible to reduce the emitter junction capacitance, and since the paste terminal is taken out through the highly concentrated base contact region (4), it is combined with good ohmic contact with the metal electrode (7). Minimum base resistance can be obtained.
これらの事により、エミッタ接合容量が小さくベース抵
抗の低いトランジスタが簡単な工程で容易に得ることが
できる。Due to these factors, a transistor with a small emitter junction capacitance and a low base resistance can be easily obtained through a simple process.
（ト）発明の効果
本発明によればエミッタ接合容量が小さく、且つベース
抵抗の低いトランジスタを簡単な工程で得ることができ
る。このことは、高電流増幅率でしかも高周波特性の優
れたＳ／Ｎ比の良い超高周波用トランジスタが得られる
ことになり、さらにセルファライン方式を用いてマスク
回数を減らしたことからコストの低減を図ることができ
る。従って安価で特性優良な超高周波用トランジスタを
提供することができる。(G) Effects of the Invention According to the present invention, a transistor with a small emitter junction capacitance and a low base resistance can be obtained through a simple process. This means that an ultra-high frequency transistor with a high current amplification factor, excellent high frequency characteristics, and a good S/N ratio can be obtained, and the cost can also be reduced by using the self-line method to reduce the number of masks. can be achieved. Therefore, it is possible to provide an ultra-high frequency transistor that is inexpensive and has excellent characteristics.
第１図（イ）〜（ト）は本発明の各工程を工程順に示し
た断面図、第２図（イ）は従来例を示した断面図で、第
２図（ロ）は電極を改良した従来例を示した断面図であ
る。
主な図番の説明
（１）は半導体基板、 （２）は薄い酸化膜、 （３）
はシリコン窒化膜である。Figures 1 (A) to (G) are cross-sectional views showing each step of the present invention in order of process, Figure 2 (A) is a cross-sectional view showing a conventional example, and Figure 2 (B) is an improved electrode. FIG. 2 is a sectional view showing a conventional example. Explanation of main figure numbers (1) is semiconductor substrate, (2) is thin oxide film, (3)
is a silicon nitride film.
Claims (1)
トランジスタのエミッタとなるべき領域上の前記酸化膜
上に耐酸化性膜を付着する工程と、前記耐酸化性膜をマ
スクとしてイオン注入することにより前記半導体基板表
面に前記耐酸化性膜下の領域を除いて逆導電型のベース
コンタクト領域を形成する工程と、該ベースコンタクト
領域を形成する時より加速電圧を上げてイオン注入する
ことにより前記耐酸化性膜下の前記半導体基板表面に前
記ベースコンタクト領域と隣接して逆導電型のベース領
域を浅く形成する工程と、前記耐酸化性膜をマスクとし
て選択酸化することにより他の領域の酸化膜を厚くする
工程と、前記耐酸化性膜を除去してイオン注入する事に
より前記ベース領域内に一導電型のエミッタ領域を形成
する工程とを有することを特徴とする半導体装置の製造
方法。(1) Forming a thin oxide film on the surface of one conductivity type semiconductor substrate,
A step of depositing an oxidation-resistant film on the oxide film on the region that is to become the emitter of a transistor, and implanting ions using the oxidation-resistant film as a mask to form a region under the oxidation-resistant film on the surface of the semiconductor substrate. forming a base contact region of the opposite conductivity type, and implanting ions at a higher acceleration voltage than when forming the base contact region, thereby forming the base contact on the surface of the semiconductor substrate under the oxidation-resistant film. a step of shallowly forming a base region of the opposite conductivity type adjacent to the region, a step of selectively oxidizing the oxidation-resistant film using the oxidation-resistant film as a mask to thicken the oxide film in other regions, and removing the oxidation-resistant film. forming an emitter region of one conductivity type in the base region by performing ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17209484A JPS6149471A (en) | 1984-08-17 | 1984-08-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17209484A JPS6149471A (en) | 1984-08-17 | 1984-08-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6149471A true JPS6149471A (en) | 1986-03-11 |
Family
ID=15935427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17209484A Pending JPS6149471A (en) | 1984-08-17 | 1984-08-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6149471A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5678869A (en) * | 1995-06-01 | 1997-10-21 | Mitsui Kinzoku Kogyo Kabushiki Kaisha | Switch for detecting full-latch condition in vehicle door latch device |
| US6264253B1 (en) | 1997-08-27 | 2001-07-24 | Ohi Seisakusho Co., Ltd. | Door lock apparatus provided with a sensing switch |
| US6428059B2 (en) | 2000-02-29 | 2002-08-06 | Ohi Seisakusho Co., Ltd. | Latch detector for automotive door locks |
| DE102005014137B4 (en) * | 2004-03-30 | 2016-02-11 | Mitsui Kinzoku Act Corp. | Door locking system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010579A (en) * | 1973-05-25 | 1975-02-03 | ||
| JPS5420675A (en) * | 1977-07-18 | 1979-02-16 | Toshiba Corp | Production of semiconductor device |
| JPS58105571A (en) * | 1981-12-17 | 1983-06-23 | Oki Electric Ind Co Ltd | Preparation of semiconductor device |
-
1984
- 1984-08-17 JP JP17209484A patent/JPS6149471A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010579A (en) * | 1973-05-25 | 1975-02-03 | ||
| JPS5420675A (en) * | 1977-07-18 | 1979-02-16 | Toshiba Corp | Production of semiconductor device |
| JPS58105571A (en) * | 1981-12-17 | 1983-06-23 | Oki Electric Ind Co Ltd | Preparation of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5678869A (en) * | 1995-06-01 | 1997-10-21 | Mitsui Kinzoku Kogyo Kabushiki Kaisha | Switch for detecting full-latch condition in vehicle door latch device |
| US6264253B1 (en) | 1997-08-27 | 2001-07-24 | Ohi Seisakusho Co., Ltd. | Door lock apparatus provided with a sensing switch |
| US6428059B2 (en) | 2000-02-29 | 2002-08-06 | Ohi Seisakusho Co., Ltd. | Latch detector for automotive door locks |
| DE102005014137B4 (en) * | 2004-03-30 | 2016-02-11 | Mitsui Kinzoku Act Corp. | Door locking system |
| DE102005063378B4 (en) * | 2004-03-30 | 2018-11-15 | Mitsui Kinzoku Act Corp. | Door locking system |
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