JPS58105571A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To easily and accurately obtain semiconductor element with a miniature structure while a severe masking is unnecessary by forming the diffusion or ion implantation window of the emitter region which also works as a contact hole of electrode and the base region with a sheet of mask. CONSTITUTION:A polycrystalline Si film 22 is deposited on an n type Si substrate 21, an SiO2 film 23 and an Si3N4 film 24 are stacked thereon and the entire surface is covered with a resist film 25 of the specified pattern. Then, the surface is etched with a layer 25 used as the mask, an exposed film 24 and then the film 23 are eliminated, the B ion is implanted through the film 22 while the layer 25 is left and an p type ion implanted region 26 is formed on the surface of substrate 21. Thereafter, the layer 25 is removed, ion implantation is carried out again, the region 26 is deepened by heat treatment in the O2 ambient, and a p- type first operating region 27 is formed in contact with the region 26 between them. At this time, the films 24a, 23a sandwiched by the SiO2 film 28 generated at the exposed area of film 22 are removed and a p<+> type second operating region 29 is formed at the lower side of region 27 including it by the diffusion method.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device suitable for high frequency band power transistors and the like.

FIG. 1 is a manufacturing process diagram for explaining a conventional manufacturing method of this type of semiconductor device, and shows the case of an npn transistor.

First, in the step shown in FIG. 1A, an n-type silicon substrate 1 is prepared, a silicon oxide film 2 is formed thereon, and then windows are selectively opened. Next, in the step shown in FIG. 1CB), a p+ type side space region 3 is formed in the n type silicon substrate 1 by diffusion or ion implantation from this window opening. Next, in the step shown in FIG. 1C, a p-type main space region 4 is similarly formed by diffusion or the like. Next, in the step shown in FIG. 1(9), a meter-shaped emitter region 5 is formed above the main pace region 4 by diffusion or the like. Next, in the step shown in FIG. 1(6), a window is opened in the silicon oxide film 2 at the electrode forming portion, and a space electrode 6 and an emitter electrode 7 are formed by lift-off or etching to complete the device.

However, in this external manufacturing method, mask alignment is required when forming the side space region 3, main space region 4, emitter region 5, and electrodes, and mask alignment with strict precision is required to manufacture fine semiconductor elements. This is a major cause of yield reduction, and a slight mask shift increases the parasitic capacitance and resistance of the device, resulting in deterioration of characteristics and reliability.

The present invention relates to a method for manufacturing a semiconductor device that eliminates the need for mask alignment with strict precision in order to eliminate such drawbacks, and will be described in detail below.

FIG. 2 is a diagram showing the manufacturing process of an npn type transistor in order to explain the manufacturing method of a semiconductor device which is an embodiment of the present invention. A polysilicon film 22 is formed on the polysilicon film 22, and a silicon oxide film 23 and a silicon nitride film 24 are sequentially formed thereon by the CVD method, and after the entire surface is covered with a resist 25, a /4' turning is performed by the photolithography method as shown in the figure. do. This silicon oxide film 23 acts as a buffer for distortion caused by the difference in coefficient of expansion between the silicon nitride film 24 and the polysilicon film 22 due to heat in later steps. Next, in the step shown in FIG. 2(B), zolon ions are implanted while leaving the resist 25 to form a p-type first conductive region 26. Next, in the step shown in FIG. 2C, after removing the resist 25, boron ions are implanted and annealing is performed in an oxygen atmosphere to form a p'' type first operating region 27. At the same time, the polysilicon film 22 is selectively oxidized to form a silicon oxide film 28. Next, in the step () in FIG. 2, a silicon nitride film 24a is formed.

After removing the silicon oxide film 23a by photolithography, a p-type second conductive region 29 is formed by diffusing or ion-implanting highly concentrated boron. Next, in the process shown in FIG. 2 (■), after coating the resist 30, the silicon nitride film 24b and silicon oxide FIX 23b in the emitter electrode formation area are removed by photolithography, and arsenic ions are implanted while leaving the resist 30. Annealing is performed to form an n+ type second operating region 3.

In the process shown in FIG. 2, a space electrode 32. is formed on the polysilicon film 22a. An emitter electrode 33 is formed on the polysilicon film 2' 2b to complete the device.

As described above, according to the manufacturing method of the present invention, the emitter region, which also serves as the contact hole of the electrode, and the diffusion or ion implantation window for the space region are formed with a single mask, which eliminates the need for strict mask alignment and allows fine structures to be formed. semiconductor devices can be easily manufactured with high precision, parasitic capacitance and parasitic resistance are reduced, resulting in less variation in characteristics, and electrode metal can completely cover contact holes, improving reliability.

Furthermore, pace resistance can be easily reduced and high frequency characteristics can be improved.

[Brief explanation of the drawing]

FIG. 1 is a manufacturing process diagram of a conventional semiconductor device, and FIG. 2 is a manufacturing process diagram of a semiconductor device of the present invention. 21... Silicon substrate, 22... Polysilicon film,
24... Silicon nitride film, 25... Resist, 26
...first conductive region, 22...first operating region, 28.
...Silicon oxide film, 29...Second conductive region, 30.
. . . resist, 31 . . . second operating region. Patent applicant: Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] A step of sequentially forming a polysilicon film and a nitride film on the semiconductor substrate and selectively removing the nitride film after covering the first renost; and using the resist and the nitride film as a mask, impurities of one conductivity type are applied to the semiconductor substrate. a step of introducing impurities into the semiconductor substrate and selectively forming a first conductive region of one conductivity type; a step of introducing a polysilicon film into a silicon oxide film to form a first operating region and converting a portion of the polysilicon film not masked by the nitride film into a silicon oxide film;
removing the nitride film in the space region forming portion and introducing impurities of the same conductivity type as the first conductive region into the semiconductor substrate from that portion to form a second conductive region; and applying a second resist over the entire surface. removing the nitride film in the emitter region forming portion and introducing impurities of a conductivity type different from that of the first conductive region using the second renost as a mask to form a second operating region. Features: A method for manufacturing semiconductor devices.