JPH0669244A - Manufacture of junction field-effect - Google Patents

Abstract

PURPOSE:To produce a junction field-effect transistor with little variation in gate breakdown voltage, by reducing a variation in length between a gate and a drain. CONSTITUTION:Contact holes 11 are formed in places for forming a source, a drain, and a gate. The place for forming the gate is coated with a resist film 6. By using a mask of the resist film 6 and an layer insulating film 9, an ion-implantation step with a second conductivity-type impurity 7 is carried out to form second conductivity-type high-density regions 3 and 4. Then, the places for forming the source and the drain are coated with a resist film 6. By using a mask of the resist film 6 and the layer insulating film 9, and ion implantation step with a first conductivity-type impurity 8 is carried out to form a first conductivity-type high-density region 5. After the resist film 6 is removed, an annealing step is carried out to form the second high-density conductivity-type regions 3 and 4 as a source as a source and a drain, and the first conductivity-type high-density region 5 is formed as a gate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a junction field effect transistor (JFET).

[0002]

2. Description of the Related Art FIG. 2 shows a junction type field effect transistor (J
It is a figure which shows the structure of FET. Referring to FIG. 2, this JFET has a back-gate region 1 of a first conductivity type, a channel region 2 of a second conductivity type, a high-concentration region 3 of a second conductivity type serving as a source, and a second region serving as a drain. It has a high-concentration region 4 of the conductivity type and a high-concentration region 5 of the first conductivity type serving as a gate, and the high-concentration regions 3 and 4 of the second conductivity type and the high-concentration region 5 of the first conductivity type are The metal electrodes 10 are connected to each other through contact holes formed in the interlayer insulating film 9.

3A and 3B and FIGS. 4A to 4E are views showing a conventional manufacturing process of the JFET shown in FIG. Conventionally, in order to previously form the second conductivity type channel region 2 in the first conductivity type back gate region 1, as shown in FIG. 3A, the resist film 6 is used as a mask.
Impurities 7 of the second conductivity type are formed in the back gate region 1 of the first conductivity type.
Ion implantation is performed. Then, as shown in FIG. 3B, after removing the resist film 6, annealing is performed,
A second conductivity type channel region 2 is formed in the first conductivity type back gate region 1.

Then, in order to form the source 3 and the drain 4, as shown in FIG. 4A, ion implantation of the second conductivity type impurity 7 is performed using the resist film 6 as a mask. Further, in order to form the gate 5, as shown in FIG. 4B, the first conductivity type impurity 8 is ion-implanted using the resist film 6 as a mask. Then, as shown in FIG. 4C, after removing the resist film 6, annealing is performed to form a source 3, a drain 4 and a gate 5 in the second conductivity type channel region 2, and then, the interlayer The insulating film 9 is deposited.
Next, as shown in FIG. 4D, the interlayer insulating film 9 is etched using the resist film 6 as a mask to form a contact hole. Thereafter, as shown in FIG. 4E, a metal film is deposited, and this is patterned to form the metal electrode 10, so that the JFET as shown in FIG. 2 can be manufactured.

[0005]

By the way, the gate breakdown voltage of a JFET is generally the same as that of the gate 5 and the channel region 2.
The reverse breakdown voltage is determined, but with the miniaturization of the element, the gate breakdown voltage is often determined by the distance between the gate 5 and the drain 4 and the impurity concentration. In this case, in the manufacturing method as described above, the source 3 and the drain 4 are
The photolithography process for deciding the position of and the photolithography process for deciding the position of the gate 5 are performed in separate steps as shown in FIGS. 4 (a) and 4 (b). The distance between the gate 5 and the drain 4 varies,
As a result, there is a problem that the gate breakdown voltage of the JFET varies.

The present invention provides a method for manufacturing a junction field effect transistor capable of manufacturing a junction field effect transistor in which variation in distance between a gate and a drain is reduced and variation in gate breakdown voltage is small. Has an aim.

[0007]

1 (a) to 1 (f) show a junction field effect transistor (JFET) according to the present invention.
It is a figure which shows the example of a manufacturing process. The manufacturing steps of FIGS. 1A to 1F are for manufacturing the JFET shown in FIG. 2. As a pre-process of the steps of FIGS. The steps shown in a) and (b) are performed.

That is, also in the fabrication of the JFET according to the present invention, as shown in FIGS. 3A and 3B, first, the second conductivity type channel region 2 is formed in the first conductivity type back gate region 1. Form. Then, as shown in FIG. 1A, the interlayer insulating film 9 is deposited. Next, as shown in FIG. 1B, the interlayer insulating film 9 is etched using the resist film 6 as a mask to form contact holes 11 in the portions to be the source, drain and gate. Then, FIG. 1 (c)
As shown in FIG. 3, a portion to be a gate is covered with a resist film 6, and the resist film 6 and the interlayer insulating film 9 are used as a mask to form a second conductivity type impurity 7 in a portion to be a source and a drain.
Ion implantation of the second conductivity type high concentration regions 3 and 4
To form. After that, as shown in FIG. 1D, the portions to be the source and the drain are covered with a resist film 6, and the resist film 6 and the interlayer insulating film 9 are used as a mask to make the portion to be the gate the first conductivity type. Ions of impurities 8 are implanted to form the high-concentration region 5 of the first conductivity type. Then, as shown in FIG. 1E, the resist film 6 is removed,
Annealing is performed to form the high-concentration regions 3 and 4 of the second conductivity type as the source and the drain, respectively, and the high-concentration region 5 of the first conductivity type is formed as the gate. Then, Figure 1
As shown in (f), a metal film is deposited and patterned to form a metal electrode 10, and the JFET shown in FIG. 2 is formed.
Can be formed.

As described above, in this manufacturing process, the contact holes 11 are simultaneously formed in one step in the portions to be the source, drain, and gate, and the high-concentration region 3 of the second conductivity type to be the source and drain is formed. , 4 are formed by self-alignment with respect to the contact holes 11 using the resist film 6 covering the portions to be gates and the interlayer insulating film 9 in which contact holes are formed in advance as masks, and
Using the first-conductivity-type high-concentration region 5 to be a gate as a mask, the resist film 6 covering the portions to be a source and a drain and the interlayer insulating film 9 in which a contact hole is formed in advance are used as masks for self-alignment. The contact hole 11 is previously formed in the interlayer insulating film 9, and the source 3, the drain 4, and the gate 5 are formed by self-alignment with respect to the contact hole, so that the distance between the gate 5 and the drain 4 is increased. Can be made extremely small in variation, and even if the distance between the gate 5 and the drain 4 becomes extremely small due to miniaturization,
It is possible to realize a JFET with less variation in gate breakdown voltage.

In the above example, the ion implantation into the portions to become the source 3 and the drain 4 is performed before the ion implantation into the portion to become the gate 5, but the order may be reversed. good. That is, the process of FIG. 1C and the process of FIG. 1D may be reversed. Further, in the above example, the annealing is performed after the ion implantation into all the portions to become the source 3, the drain 4 and the gate 5, but the ion implantation into the portions to become the source 3 and the drain 4 is performed. Annealed later, gate 5
Annealing may be performed after each ion implantation such that annealing is performed after ion implantation is performed on a portion to be formed.

[0011]

EXAMPLES Examples of the present invention will be described below. In this example, first, a predetermined resist pattern was formed on a P-type silicon substrate having a resistivity of 6 Ωcm, phosphorus ions were accelerated by an ion implantation method at an acceleration energy of 150 keV, and a dose amount of 2.0E12 / cm ² was used. Then, the resist is removed, and annealing is performed for 10 hours in an electric furnace in a nitrogen atmosphere at 1100 ° C. to activate the implanted ions to form an N-type well to be the first conductivity type back gate region 1. It was made.

Next, the back gate region 1 was separated by the normal LOCOS method in order to separate the elements of the adjacent JFETs. Next, in order to form the channel region 2, a predetermined resist pattern is formed, the acceleration energy is 70 keV and the dose amount is 3.0E1 by the ion implantation method.
After implanting boron ions at 3 / cm ² , the resist was removed, and thereafter, the implanted ions were activated by annealing in a nitrogen atmosphere at 950 ° C. for 10 hours to form a channel region 2.

Next, 80% of SiO ₂ is deposited by the CVD method.
Then, an interlayer insulating film 9 was formed. Then, using the resist film 6 as a mask, the interlayer insulating film 9 was dry-etched using a CHF ₃ -based gas to form contact holes 11 in the source, drain, gate portions, and back gate electrode extraction portions. . Then, a portion to be a gate and a portion for taking out the back gate electrode are covered with a resist pattern 6, and the resist pattern 6 and the interlayer insulating film 9 are used as a mask to form a source,
BF ₂ ions were implanted into the portion to be the drain by an ion implantation method at an acceleration energy of 50 keV and a dose amount of 5.0E15 / cm ² , and then the resist was removed. Next, a resist pattern 6 is formed, and by using the resist pattern 6 and the interlayer insulating film 9 as a mask, an acceleration energy of 50 keV is applied to a portion to be a gate and a back gate electrode extraction portion by an ion implantation method.
Arsenic ions are implanted at a dose of 5.0E15 / cm ² ,
After that, the resist was removed. After removing the resist, 9
The implanted ions were activated by annealing in an electric furnace in a nitrogen atmosphere at 00 ° C. for 1 hour to form a source 3, a drain 4, a gate 5 and a back gate electrode extraction portion. Then, it is dipped in a dilute hydrofluoric acid-based solution to remove the oxide film, and then an aluminum alloy is deposited by a sputtering method, and the aluminum alloy is patterned to form a metal electrode 10 to complete a P-channel JFET. Let

P-channel JF produced in this way
In ET, the reverse breakdown voltage of the gate 5 and the channel region 2 is 7.5 V, and the distance between the gate 5 and the drain 4 is 3 μm.
After that, the gate breakdown voltage started to fall. Further, when the distance between the gate 5 and the drain 4 was set to 2 μm, the gate breakdown voltage of the JFET by the conventional method had a variation of 5 V ± 1 V. According to the present invention, this variation is 5 V ± 1 V.
It could be improved to 0.2V.

[0015]

As described above, according to the present invention, after the contact holes are formed in the portions to be the source, drain and gate, the portions to be the gate should be covered to become the source and drain. Ions of the second conductivity type impurity are implanted into the portion, and the portions of the source and drain to be covered are covered with the ions of the first conductivity type impurity into the portion to be the gate. It is possible to form the JFET with a substantially uniform distance from the gate electrode with high accuracy, and it is possible to realize a JFET in which the variation in gate breakdown voltage is extremely small as compared with the related art.

[Brief description of drawings]

1A to 1F are views showing an example of a manufacturing process of a junction field effect transistor according to the present invention.

FIG. 2 is a diagram showing a structure of a junction field effect transistor.

3 (a) and 3 (b) are views showing a pre-process of the manufacturing process of FIGS. 1 (a) to 1 (f).

4A to 4E are views showing an example of a manufacturing process of a conventional junction field effect transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st conductivity type back gate region 2 Channel region 3 Source (2nd conductivity type high concentration region) 4 Drain (2nd conductivity type high concentration region) 5 Gate (1st conductivity type high concentration region) 6 Resist Film 7 Second conductivity type impurity 8 First conductivity type impurity 9 Interlayer insulating film 10 Metal electrode

Claims (3)

[Claims] 1. A step of forming a contact hole in each portion to be a source, a drain and a gate, and a portion to be a source and a drain after covering a portion to be a gate after forming a contact hole in each of the portions. And a step of implanting ions of the second conductivity type impurity into the substrate, and a step of implanting ions of the first conductivity type impurity into the part to be the source and drain and to the gate. And a method for manufacturing a junction field effect transistor. 2. The method for manufacturing a junction field effect transistor according to claim 1, wherein the ion implantation of the second conductivity type impurity into the portions to be the source and the drain is performed by self-alignment with respect to the contact hole. Further, the method for manufacturing a junction field effect transistor, wherein the ion implantation of the first conductivity type impurity into the portion to be the gate is performed by self-alignment with respect to the contact hole. 3. The method of manufacturing a junction field effect transistor according to claim 1, wherein a second conductivity type impurity is ion-implanted into the portions to be the source and drain, and the first conductivity type is into the portion to be the gate. A method for manufacturing a junction field effect transistor, characterized in that after implanting impurities, each implanted ion is activated by annealing to form a source, a drain and a gate.