JPS60167470A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture MISFET's of high drain withstand voltage with good reproducibility and high yield by a method wherein the distance of alienation of a channel dope region from a drain region is controlled by the side etch amount of an Si film on a poly Si film. CONSTITUTION:After removal of a photo resist 16, the channel dope region (P type diffused layer) 17' is formed by heat treatment. Finally, As ions are implanted at an acceleration energy of 40KeV to the Si substrate surface by using a poly Si film 13 as a mask, and an N<+> type source 18 and an N<+> drain 19 are formed by heat treatment, resulting in the completion of an N-channel MOSFET of the structure of alienation of the channel dope region 17' from the source region 18 and the drain region 19. Since the above-mentioned distance of alienation is determined by the post-etching dimension (Lsio2) of an Si oxide film 14, it is necessary to control the film thickness, etching speed, and etching time of the Si oxide film with good accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MISFET with excellent drain suppression.

Configuration of conventional example and its problems Conventional N-channel type M I S F E T l, -
j5, as shown in the cross-sectional shape in FIG.
The structure includes a source (n+ layer) 2, a drain (n layer) 3, a channel doped region (p type diffusion layer) 4, and a gate insulating film 6.

The conventional method for manufacturing the MISFKT is as follows: First, a silicon substrate 1 is thermally oxidized to form a gate insulating film 5, and boron ions are implanted into the silicon substrate 1 to form a channel doped region 4. Next, after forming a gate electrode 6 using polysilicon doped with phosphorus, 1. Arsenic ions are implanted into the silicon substrate 1 to form the source 2.
Then, a drain 3 is formed to complete the MISFET.

The impurity concentration of the channel doped region 4 is set to 1, the impurity concentration in the silicon substrate, the thickness of the gate insulating film 5, the gate voltage, and the threshold voltage of the MISFKT, which varies depending on the length L of the pole 6, is set in the circuit design. (e.g. ○, sV
In order to control the impurity concentration to approximately 10 to 10 cm
It is necessary to form a channel doped region 4 of approximately 100 mL. As shown in FIG. 1, this channel doped region 4 is in contact with the n-type drain 3 to form a pn junction, and the drain breakdown voltage of the MISFET is Depends on impurity concentration. In other words, the higher the impurity concentration in the channel doped region, the lower the drain breakdown voltage.

With the miniaturization of MISFETs, the impurity concentration in the channel doped region tends to increase.
In ISFETs, it has been impossible to avoid a decrease in drain breakdown voltage.

Purpose of the Invention The present invention was made in order to eliminate the drawbacks of the conventional MISFET described above.
An object of the present invention is to provide a method for manufacturing ET.

Structure of the Invention A method for manufacturing a semiconductor device according to the present invention includes: - forming a first insulating film on a conductive type semiconductor substrate; forming a conductive film and a second insulating film on the first insulating film; A step of forming a layered film, a step of isotropically and anisotropically etching the second insulating film and the conductive film using the same photomask to form a pattern, and a step of forming a pattern on the entire surface. forming a viscous film; etching the high viscosity film until the second insulating film is exposed; using the high viscosity film as a mask, removing the second insulating film and etching the conductive film underneath. The process of exposing
This method includes a step of selectively implanting impurity ions into the semiconductor substrate through the exposed conductive film portion. According to this method, the channel doped region and the drain diffusion layer are formed apart from each other, so the MISFET drain It is possible to significantly improve the withstand voltage.

DESCRIPTION OF EMBODIMENTS Below, a case in which the present invention is applied to the manufacture of an N-channel MO3FET will be explained in detail with reference to step-by-step sectional views of FIGS. 2a to 2e.

First, as shown in FIG. 2a, a p-type silicon substrate 11 is thermally oxidized to form a gate oxide film 12 with a thickness of about 300 Å, and then a polysilicon film 13 with a thickness of about 200 Å is formed thereon by a normal CVD method. After doping with phosphorus (by thermal diffusion) to form
A silicon oxide film 1 with a thickness of about 600 OA was made using the same CVD method.
form 4.

Next, the photoresist 15 is buttered as shown in FIG. 2, and then the silicon oxide film 14 is coated with buffered hydrofluoric acid.
isotropically etched. and photoresist 16
Using as a mask, polysilicon 13 is anisotropically etched by reactive ion etching. As a result, the silicon oxide film 14 is overetched to a dimension Lsio2. The dimension after etching (Lsio2) of the silicon oxide film 14 shown in FIG. 2 is controlled by the etching time using the buffered hydrofluoric acid.

Next, after removing the photoresist 15 used as a mask, a relatively high viscosity 7 photoresist 16 is applied to the entire surface, and approximately 2
The photoresist surface is planarized by baking at 00'C. Then, the photoresist 16 is etched back from layer to line B using oxygen plasma to expose the surface of the silicon oxide film 14, as shown in FIG. 2C.

After removing the exposed silicon oxide film 14 with oxidized hydrofluoric acid, using the remaining photoresist 16 as a mask, boron ions are implanted at an acceleration energy of 150 keV, as shown in FIG. 2d. , p-type impurity layer 1
form 7. At this time, the impurity is implanted into the region indicated by the arrow, and the ion acceleration energy, the film thickness of the polysilicon 13, the film thickness of the photoresist 16 (in this case, the film thickness of the silicon oxide film 14) are It is important to set the relevant parameters to optimal values.

Next, the photoresist 16 is removed and heat treated to form a channel doped region (p-type diffusion layer) 17'.

Finally, using the polysilicon film 13 as a mask, arsenic ions are implanted into the silicon substrate surface at an acceleration energy of 40 keys, followed by heat treatment to form a 1n+ type source 18 and drain 19. A channel doped region 17 and a source region 18 . An N-channel MO3FET having a structure in which the drain region 19 is separated is completed.

Further, since the above-mentioned separation distance is determined by the dimension (Ls102) of the silicon monoxide film 14 after etching, it is necessary to accurately control the thickness of the silicon oxide film, the etching rate, and the etching time.

In this embodiment, photoresist was used for the high viscosity film and 1-, but in other examples, polyimide resin may also be used.

Effects of the Invention According to the method of manufacturing a semiconductor device of the present invention, a structure in which a channel tope region and a drain region are separated +7) MISF
Since the ET can be formed on a self-aligned line and can be controlled by the above-mentioned separation distance or the amount of oxide of the silicon oxide film of the polysilicon film, a MISFET with high train breakdown voltage can be manufactured with good reproducibility and high yield.

[Brief explanation of the drawing]

Figure 1-: A sectional view of the main parts showing the structure of a conventional MISFET, Figures 2 a-e are MISFETs manufactured by the manufacturing method of the present invention.
FIG. 3 is a process cross-sectional view for explaining the state of forming an FKT. 11...Silicon substrate (p-), 12...
・Gate oxide film, 13...Polysilicon film (gate N&) 14...Silicon oxide 1L15.
... photo resist, 16... photoresist layer (ion implantation layer), 17'... channel doped region (1)), 18... Source (n″-
), 19... Doshi-in (n+). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] A step of forming a first insulating film on a semiconductor substrate of one conductivity type, a step of forming a conductive film and a second insulating film in a stacked manner, and a step of forming a conductive film and a second insulating film in a layered manner using the same photomask. A step of forming a pattern by isotropically and anisotropically etching the second insulating film and the conductive film, respectively A step of forming a high viscosity film on the entire surface, a step of forming the high viscosity film on the second insulating film a step of etching until the film is exposed; a step of removing the second insulating film using the high viscosity film as a mask and exposing the conductive film thereunder; A method for manufacturing semiconductor devices that includes a process of selectively ion-implanting impurities.