JPH03153081A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To suppress the increase of the sheet resistance in source and drain regions and the generation of hot carriers so that it can cope with the micronization of an element by providing a recess, which is thinner the other parts of source and drain regions, as a channel region, which includes one part each of the source and drain regions, in a semiconductor film, and constituting a gate electrode as long as the width of this recess or longer than it. CONSTITUTION:It is doped with n-type impurities so as to form an n<+> layer 3 where impurity concentration is high. At this time, the acceleration voltage and heat treatment time are controlled so that the thickness of a p<->-layer 4 remaining on a substrate insulating film 1b may be about 0.2mum. And it is coated with a resist 6, which has a specified pattern where a channel formation planned position is opened, and then an n<+>-layer 3 is etched selectively and as a channel region 5 a p<->-layer 7 being thinned below 0.2mum is made. Thereafter, a gate 10 is made at the channel region, that is, thin part 5. At this time, the gate length W is made the one equal to or more than the width of the thin part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor having a thin film structure and a method for manufacturing the same.

[Conventional technology] Conventionally, so-called Sol technology in which a semiconductor thin film is formed on an insulating substrate
Insulated gate field effect transistor (hereinafter referred to as M
(O3FET), the Sol film thickness is several thousand Å.
Thin film MOS whose channel region is completely depleted in
FETs are known to have excellent performance that cannot be obtained with bulk structures or thick-film Sol structures, such as suppressing short channel effects, increasing mobility, and reducing overshoot phenomena.

FIG. 2 shows the structure of a general thin film MO3FET. This MOSFET has an insulating substrate, for example, a Sing layer 2 on the surface.
After forming a Si film 22 that will become a source/drain region 20 and a channel forming region 21 on the substrate on which 5 is formed, a Sing gate insulating film 23 and a gate electrode 24 are formed on this Si film 22. can.

However, in the above-mentioned thin film MO3FET, since the film thickness is thin in the portions that simply function as resistors, such as the source/drain region 20, the sheet resistance becomes extremely large, resulting in a decrease in current drive capability. be. In addition, with the miniaturization of devices, the gate electrode 24 and the source
Since the impurity concentration change in the overlap part 20a of the drain region 20 is steep, a high electric field is applied, and hot carriers (carriers that have obtained energy from the electric field and are in a high-energy state) are generated near the top of the drain. There is a problem that device characteristics deteriorate due to injection of hot carriers into the gate oxide film 23.

To solve these problems at the same time, for example, Japanese Patent Application Laid-Open No. 62-281473 proposes that the vicinity of the gate electrode in the source/drain region be A step is formed to be lower than the surface of the source/drain region,
By ion-implanting impurities using the gate electrode region as a mask, as shown in FIG. 3, the impurity concentration in the source/drain region 31a near the gate electrode 30 is made lower than that in the other source/drain regions 31, thereby reducing hot carriers. The so-called LDD (Lightly
A doped drain structure has been proposed.

However, since this device performs ion implantation using the gate electrode region as a mask as described above, the gate length must necessarily be made finer than the region width lowered by the step of the Si film. Therefore, as device miniaturization progresses, gate electrodes will be required to become even more miniaturized, making it difficult to configure gate electrodes with precision. The problem is that they will not be able to respond to changes.

[Problem to be solved by the invention]

The present invention has been made in view of the various problems described above, and provides a thin-film field-effect transistor and The purpose is to provide a manufacturing method thereof.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides the following: In the invention according to claim 1, a source region, a drain region, a semiconductor film on an insulating substrate,
In a field effect transistor having a gate insulating film and a gate electrode and using the semiconductor film as an active semiconductor layer, the semiconductor film has a channel region including a part of the source and drain regions. The gate electrode is provided with a recessed portion that is thinner than other parts of the region, and has a length substantially equal to or longer than the width of the recessed portion provided in the semiconductor film. A field effect transistor is provided, and in the invention according to claim 2, a first semiconductor layer of a first conductivity type and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer are provided on an insulating substrate.
a first semiconductor film forming a semiconductor film having a second semiconductor layer of a conductive type;
removing the second semiconductor layer in this one region in order to make one region of the semiconductor layer thinner than other regions;
a second step of forming a thin film portion made of the first semiconductor layer of the first conductivity type in this one region; a second step of forming a gate oxide film by thermally oxidizing the thin film portion of the semiconductor film; By heat treatment, impurities of the second conductivity type from the second semiconductor layer in other regions of the semiconductor film are diffused horizontally into the thin film portion, thereby forming a boundary between the first conductivity type and the second conductivity type in the yi film portion. a third step of forming a diffusion region of the thin film portion into a second conductivity type having an impurity concentration lower than that of the second semiconductor layer; Provided is a method for manufacturing a field effect transistor, characterized in that the method includes a fourth step of disposing a gate electrode on the thin film portion.

〔Example〕

Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIGS. 1(a) to 1(g) show cross-sectional views at each step of a manufacturing method according to an embodiment of the present invention. This example will be described below according to the manufacturing process.

First, as shown in FIG. 1(a), a SiO□ film 1b and a Si film 1a are sequentially formed on the surface of a Si substrate 10 to form a Sol substrate 1. Note that in the Sol substrate 1, SiNl
A is p-type 5iW4, which constitutes the 301st part, and has a film thickness of about 0.3 to 1 μm and an impurity concentration of I x 10 17 cm -' or less.

Next, as shown in FIG. 1(b), the SO2 substrate 1 is etched to form a silicon island to isolate the elements. Also, this element isolation is LO
The CO3 method may be used and an oxide film layer may be used.

Next, as shown in FIG. 1C, an n-type impurity such as phosphorus is doped by ion implantation to create a highly doped layer 3 with an impurity concentration of 10 cm or more. At this time, the ion implantation acceleration voltage and heat treatment time are controlled so that the thickness of the p-714 remaining on the substrate insulating film lb is about 0.2 μm.

Note that 2 is an oxide film formed on the surface of the silicon island. Further, other methods such as a vapor phase method may be used for doping with impurities at this time.

Then, as shown in FIG. 1(d), a resist 6 having a predetermined pattern in which a channel region is to be formed is opened.
N''N3 is selectively etched using, for example, a 1:3:8 mixture of hydrofluoric acid, nitric acid, and acetic acid.Thereby, a thin film is formed as the channel region 5 to a thickness of 0.2 μm or less. By using selective etching of the n-layer 3, the thickness of the p-layer 7 can be controlled with high precision.This etching can be performed using a dry etching method using optically excited C1□ gas, etc. Other etching methods may also be used.Also, selective etching is not particularly necessary as long as the thickness of the p-layer 7 can be controlled with high precision.Subsequently, as shown in FIG. After peeling off the n0 layer 3, a gate oxide film 8 is formed in the channel region 5 by thermal oxidation.
The impurity of n''N3 further diffuses and reaches the substrate insulating film ib.Due to this diffusion of n0 layer 3, the channel region 5 where the junction surface 9 of the n'' layer 3p- layer 7 is made into a thin film.
However, this horizontal diffusion occurs when the concentration of n''N3 is 1, as shown by curve P in Figure 5.
Because it occurs from a relatively low level below 0"CI-",
As shown by curve A in FIG.
The impurity concentration changes slowly in the layer 3 diffusion region. Note that curve B in FIG. 4(a) is a characteristic line showing the change in impurity concentration of the conventional thin film MOSFET shown in FIG.

Thereafter, a gate 10 is formed in the channel region, that is, the thin film portion 5, as shown in FIG. 1(f). At this time, the gate length W is set to be equal to or longer than the width of the thin film portion 5, but since the source/drain region and the channel region are formed in a self-aligned manner by the recessed portion of the thin film portion 5, the device Even if miniaturization progresses, element processing accuracy will not deteriorate due to gate alignment accuracy, etc.

Furthermore, as shown in FIG. 1(g), an interlayer insulating film 11,
The electrode 12 is formed, and the desired Sol structure MO3FET is manufactured. Furthermore, in order to reduce the sheet resistance of the thick-film source/drain regions, n-type impurities such as As may be further doped in self-alignment with the gate regions after the gate IO is formed. As a result, the concentration distribution of the impurity As in the vertical direction directly under the source/drain electrode 12 is the curve A in FIG.
As shown in s, the concentration from the substrate insulating film 1b to a portion having the same thickness as the thin film region 5 can be set to a high concentration of 10"cl" or more.

MO shown in FIG. 1(g) manufactured according to the above manufacturing process
In the SFET, a channel region 14 including a portion 13a of the source/drain region is made thinner than the other source/drain regions 13. Therefore, since the channel region 14 is a thin film, the entire channel region is depleted and the second
Like the conventional thin film MO3FET shown in the figure, the source/drain breakdown voltage has been improved.

It is possible to obtain excellent characteristics such as suppressing threshold shift, suppressing short channel effects such as suppressing deterioration of subthreshold characteristics, increasing channel mobility, and reducing overshoot phenomenon. Further, in the source/drain region, the thin film region is the minimum necessary and the other parts are made thick, so that the sheet resistance of the source/drain region can be made small, and the series resistance component of this part can be reduced.

Further, in the MO3FE-T according to the above embodiment and the thin film MO3FET shown in FIG. 2, FIG. 1(6) respectively.

Figure 4(a) shows the impurity concentration distribution along the line XX' in Figure 2, and the gate voltage Vcs
Figure 4(b) shows the simulation results of the electric field strength distribution at ``IV, source-drain voltage ■., = 2■.
4, curve A shows the characteristic of the above embodiment, and curve B shows the characteristic of the conventional one shown in FIG. 2. However, as shown in FIG. The change in impurity concentration in the overlap portion 13a of the gate region and the source/drain region of the yl film portion is more gradual than the change in impurity concentration in the circuit portion 20a of the conventional device, as shown in FIG. 4(b). As shown, the maximum electric field generated on the drain side can be suppressed, and the generation of hot carriers in the vicinity of the drain region can be suppressed.

According to the above embodiment, the gate electrode can have a gate length W equal to or longer than the width of the thin film portion, and
The source/drain region and the channel region are formed in a self-aligned manner by the thin film portion, so even as the device becomes smaller, the device processing accuracy will not deteriorate due to gate alignment accuracy, etc., and the device can be manufactured with high precision. can be manufactured.

Note that in the above embodiment, an n-channel type MOSF
Although it is an ET, a P-channel type may also be used.

[Effects of the Invention] As described above, according to the field effect transistor with a thin film structure of the present invention, it is possible to suppress an increase in sheet resistance in the source/drain region and the generation of hot carriers, and also to reduce the size of the device. It has the excellent effect of being able to respond to

[Brief explanation of the drawing]

FIGS. 1(a) to (2) are cross-sectional views of an element in the order of manufacturing steps according to an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views of a thin film MO3FET manufactured by a conventional manufacturing method, and FIG. (a)
are characteristic diagrams showing impurity concentration distributions of a MOS FET according to an embodiment of the present invention and a thin film MO3FET according to the conventional technology,
FIG. 4(b) is a characteristic diagram showing the electric field strength distribution for the impurity concentration distribution shown in FIG. 4(a), and FIG. 5 is the impurity concentration distribution in the depth direction from the surface in one embodiment of the present invention. FIG. 1...Sol substrate, la...Si film edge film, 3...
n-layer, 4...p-layer...thin p-layer, 8...
Gate oxide film. Junction surface of p- layer, 10...Gate train'tllL 13a...Oharrasop portion 2 with source/gate region Janel region. 1b...Substrate isolation 5...Thin film part, 79...n layer and 13...Source/drain region 14...Thin film chip

Claims (3)

[Claims] (1) In a field effect transistor in which a semiconductor film on an insulating substrate has a source region, a drain region, a gate insulating film, and a gate electrode, and the semiconductor film serves as an active semiconductor layer, the semiconductor film includes: A recess is provided in which a channel region including a part of the source and drain regions is made thinner than other parts of the source and drain regions, and the length is substantially the same as the width of the recess provided in the semiconductor film, or A field effect transistor characterized in that the gate electrode is longer than that. (2) Forming on an insulating substrate a semiconductor film having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type having an impurity concentration higher than that of the first semiconductor layer above the first semiconductor layer. a first step, in order to make one region of the semiconductor film thinner than another region, the second semiconductor layer in this one region is removed, and the second semiconductor layer of the first conductivity type is applied to this one region; a second step of forming a thin film portion made of a semiconductor layer; thermally oxidizing the thin film portion of the semiconductor film to form a gate oxide film; Diffusing impurities of a second conductivity type from the second semiconductor layer into the thin film portion in a horizontal direction to form an interface between the first conductivity type and the second conductivity type in the thin film portion, and forming a diffusion region into the thin film portion. a third step of forming a second conductivity type having a lower impurity concentration than the second semiconductor layer; and a fourth step of disposing a gate electrode on the thin film portion of the semiconductor film via the gate oxide film. A method for manufacturing a field effect transistor, comprising: (3) After the fourth step, the method further comprises a step of doping another region of the semiconductor film with a second conductivity type impurity in a self-aligned manner with the gate electrode or the gate oxide film. Item 2. A method for manufacturing a field effect transistor according to item 2.