KR100197656B1 - Fabricating method of s.o.i. semiconductor device - Google Patents

Fabricating method of s.o.i. semiconductor device Download PDF

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KR100197656B1
KR100197656B1 KR1019950066069A KR19950066069A KR100197656B1 KR 100197656 B1 KR100197656 B1 KR 100197656B1 KR 1019950066069 A KR1019950066069 A KR 1019950066069A KR 19950066069 A KR19950066069 A KR 19950066069A KR 100197656 B1 KR100197656 B1 KR 100197656B1
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silicon
oxide film
layer
field oxide
gate
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KR970054268A (en
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고요환
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김영환
현대전자산업주식회사
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Priority to TW085109796A priority patent/TW323388B/zh
Priority to US08/696,163 priority patent/US5899712A/en
Priority to JP8358680A priority patent/JP2936536B2/en
Priority to GB9626975A priority patent/GB2308739B/en
Priority to DE19654711A priority patent/DE19654711C2/en
Publication of KR970054268A publication Critical patent/KR970054268A/en
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Publication of KR100197656B1 publication Critical patent/KR100197656B1/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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Abstract

본 발명은 반도체 에스.오.아이. 소자의 제조방법에 관한 것으로, 필드산화막 하부의 제2실리콘층인 채널스토퍼를 통하여 상기 필드산화막의 내측에 형성된 트랜지스터를 외측의 제2실리콘층에 연결하고 이를 이용하여 반도체기판의 콘택을 실현함으로써 킹크 효과를 방지하고 문턱전압의 변화를 방지하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention is a semiconductor S. O. I. A method of fabricating a device, comprising: connecting a transistor formed inside the field oxide film to a second silicon layer on the outside through a channel stopper, which is a second silicon layer below the field oxide film, and using the same to realize contact of the semiconductor substrate. It is a technology that prevents the effect and prevents the change of the threshold voltage, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.

Description

반도체 에스 오 아이 소자의 제조방법Manufacturing Method of Semiconductor SOH Element

제1도는 종래의 일 실시예에 따른 SOI MOSFET의 단면도.1 is a cross-sectional view of an SOI MOSFET according to a conventional embodiment.

제2도는 종래의 이 실시예에 따른 SOI MOSFET의 단면도.2 is a cross-sectional view of a SOI MOSFET according to this conventional embodiment.

제3A도 내지 제3B도는 본 발명의 실시예에 따른 SOI MOSFET의 제조 공정도.3A to 3B are manufacturing process diagrams of the SOI MOSFET according to the embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 제1 실리콘 2 : 제1 실리콘산화막1: first silicon 2: first silicon oxide film

3 : 제2 실리콘 4 : 패드 산화막3: second silicon 4: pad oxide film

5 : 질화막 6 : 필드산화막5: nitride film 6: field oxide film

7 : 게이트산화막 8 : 게이트7: gate oxide film 8: gate

9 : 저농도 이온주입영역 10 : 제2 산화막9: low concentration ion implantation region 10: second oxide film

11 : 고농도 이온주입영역 12 : 절연막11 high concentration ion implantation region 12 insulating film

13 : 금속패턴13: metal pattern

14 : 채널스톱임플란트 도핑영역, 채널스토퍼 (CHANNEL STOPPER)14: Channel stop implant doping area, channel stopper

20 : 제1콘택 30 : 제2콘택홀20: 1st contact 30: 2nd contact hole

본 발명은 에스.오.아이.(silicon on insulator, 이하에서 SOI 라 함) 구조를 갖는 반도체소자의 제조방법에 것으로, 소자분리막인 필드산화막의 하부에 채널 스토퍼를 형성할 수 있도록 제2실리콘기판을 확보하여 후속공정으로 과다 전류를 소화할 수 있도록하는 기술에 관한 것이다.The present invention relates to a method for fabricating a semiconductor device having a S.O.I. structure, a second silicon substrate for forming a channel stopper under a field oxide film as a device isolation film. The present invention relates to a technique for securing an excess current by securing a subsequent process.

SOI 소자는 실리콘 기판위에 절연 역할을 하는 실리콘 산화막을 형성하고, 그 위에 실제 사용되는 실리콘기판 예를 들어 단결정 실리콘층을 형성하고, 상기 단결정 실리콘층의 상부에 반도체소자를 제조하는 방법으로 소자의 분리 기술이 용이하고, 소자의 전기적인 특성이 우수하며 널리 연구 되고 있다.The SOI device forms a silicon oxide film that insulates a silicon substrate, a silicon substrate, for example, a single crystal silicon layer is used on the silicon substrate, and a semiconductor device is formed on the single crystal silicon layer. The technology is easy, and the electrical characteristics of the device are excellent and widely studied.

일반적으로, 벌크(bulk) 모스전계효과 트랜지스터(metal oxide semconduct field effect transistor, 이하 MOSFET라 한다.)는 게이트, 소오스, 드레인, 실리콘기판의 4 - 터미널(terminal) 구조인데 비하여, SOI 구조의 MOSFET는 실리콘기판에 대한 콘택 및 관련배선에 대한 연결이 필요없기 때문에 칩(chip)의 크기를 소형화할 수 있다.In general, a bulk MOS field effect transistor (hereinafter referred to as a MOSFET) is a four-terminal structure of a gate, a source, a drain, and a silicon substrate. The size of the chip can be miniaturized by eliminating the need for contact to the silicon substrate and connection to the associated wiring.

또한, COMS를 구현하는 데 있어 웰을 형성하지 않으며, 각각의 MOSFET의 활성영역이 서로 절연되어 있기 때문에 래치-업을 방지할 수 있다.In addition, the wells are not formed in implementing the COMS, and the latch-up can be prevented because the active regions of the respective MOSFETs are insulated from each other.

얇은 실리콘박막에 제작되는 SOI 소자는 소오스/드레인 접합이 필름 두께 전체에 형성되므로, 소오스/드레인의 면접합용량(area junction capacitance)이 거의 없고, 패리미터(perimeter)에 의한 접합용량만이 존재한다. 따라서, SOI 소자는 벌크 MOSFET에 비해 고속, 저전력 특성을 갖는다.In SOI devices fabricated in thin silicon thin films, source / drain junctions are formed over the entire film thickness, so there is almost no area junction capacitance of the source / drain, and only a junction capacitance due to a perimeter exists. . Thus, SOI devices have high speed and low power characteristics compared to bulk MOSFETs.

제1도는 종래 기술로 제조된 SOI 소자를 도시한 단면도이다.1 is a cross-sectional view showing a SOI device manufactured by the prior art.

제1도를 참조하면, 제 1 실리콘(1)기판 상부에 제1 실리콘산화막(2)을 형성하고, 상기 제1 실리콘산화막(2)의 상부에 사다리꼴 모양의 제2 실리콘(3)층을 형성한다.Referring to FIG. 1, a first silicon oxide film 2 is formed on the first silicon substrate 1, and a trapezoidal second silicon 3 layer is formed on the first silicon oxide film 2. do.

그 다음, 상기 제2 실리콘(3)층의 상부에 패드산화막(도시않음)을 형성하고, 상기 패드산화막의 상부에 질화막(도시않음)을 형성한다.Next, a pad oxide film (not shown) is formed on the second silicon 3 layer, and a nitride film (not shown) is formed on the pad oxide film.

그 다음, 소자분리영역을 노출하는 식각마스크를 사용하여 상기 질화막 과, 패드산화막을 식각하여 질화막패턴과, 패드산화막패턴을 형성한다.Next, the nitride layer and the pad oxide layer are etched using an etching mask exposing the device isolation region to form a nitride layer pattern and a pad oxide layer pattern.

그 다음, 노출된 제2 실리콘(3)층을 산화하여 상기 제2 실리콘(3)층의 상부에 필드산화막(6)을 형성한다.Next, the exposed second silicon 3 layer is oxidized to form a field oxide film 6 on the second silicon 3 layer.

그 다음, 상기 질화막패턴과, 패드산화막패턴을 차례로 식각하여 제거한다.Next, the nitride film pattern and the pad oxide film pattern are sequentially removed by etching.

그 다음, 상기 제2 실리콘(3)층의 상부에 게이트산화막(7)과, 폴리실리콘 층을 차례로 형성한 후, 상기 폴리실리콘층을 패터닝하여 게이트(8)를 형성한다. 그 다음, 상기 게이트를(8)를 마스크로 상기 제2 실리콘(3)층에 고농도의 이온을 주입하여 고농도 이온주입영역(11)을 형성한다.Next, the gate oxide layer 7 and the polysilicon layer are sequentially formed on the second silicon 3 layer, and then the polysilicon layer is patterned to form the gate 8. Next, a high concentration ion implantation region 11 is formed by implanting high concentration ions into the second silicon layer 3 using the gate 8 as a mask.

그 다음, 상기 구조의 전 표면에 제2 산화막(10)을 형성한 후, 전면 식각하여 상기 게이트(8)의 측벽에 제2 산화막(10)스페이서를 형성한다.Next, after forming the second oxide film 10 on the entire surface of the structure, the entire surface is etched to form the second oxide film 10 spacer on the sidewall of the gate 8.

그 다음, 상기 구조의 전 표면에 절연막(12)을 형성하고, 콘택홀을 형성하기 위한 식각마스크를 사용하여 상기 절연막(12)을 게이트(8)와, 제2 실리콘(3)층이 노출될 때까지 식각하여 콘택홀을 형성한다.Next, an insulating film 12 is formed on the entire surface of the structure, and the gate 8 and the second silicon 3 layer are exposed through the insulating film 12 using an etching mask for forming a contact hole. Etch until a contact hole is formed.

그 다음, 상기 콘택홀을 매립하는 금속패턴(13)을 형성한다.Next, a metal pattern 13 filling the contact hole is formed.

그러나, 상기와 같은 SOI 구조의 MOSFET는 얇은 실리콘 박막의 두께와, 반도체기판에 콘택이 없는 것으로 인하여 이래와 같은 여러 가지 문제점이 발생한다.However, the MOSFET having the SOI structure as described above has various problems due to the thickness of the thin silicon thin film and the absence of contact on the semiconductor substrate.

우선, 얇은 실리콘박막의 두께는 MOSFET 의 문턱전압(threshold voltage)의 변화요인이 된다.First, the thickness of the thin silicon thin film becomes a factor of change in the threshold voltage of the MOSFET.

MOSFETS의 문턱전압은 다음과 같이 나타낼 수 있다.The threshold voltage of MOSFETS can be expressed as follows.

VT= VFB+ QB/Cox .... 식1V T = V FB + Q B / Cox .... Equation 1

여기서, VT는 문턱전압, VFB는 플래트 밴드 전압, QB는 벌크 차지, Cox는 산화막의 충전 용량이다.Where V T is the threshold voltage, V FB is the flat band voltage, Q B is the bulk charge, and Cox is the charge capacity of the oxide film.

채널의 차지(charge)는 실리콘박막의 두께에 따라 변하게 되는데, 실리콘 박막의 두께가 얇아짐에 따라 SOI 구조의 MOSFET의 문턱전압도 낮아지게 된다. 따라서, 실리콘박막의 두께 변화는 SOI 구조의 MOSFET의 문턱전압에 직접적인 영향을 주게 된다.The charge of the channel changes according to the thickness of the silicon thin film. As the thickness of the silicon thin film becomes thinner, the threshold voltage of the MOSFET of the SOI structure also decreases. Therefore, the thickness change of the silicon thin film directly affects the threshold voltage of the MOSFET of the SOI structure.

현재의 기술로 조절할 수 있는 실리콘박막의 두께는 약 100Å정도이다. 이값은 SOI 구조의 MOSFET를 제작했을 때, 약 0.1 Volt 정도의 문턱전압의 변화를 가져올 수 있다.The thickness of the silicon thin film that can be adjusted by current technology is about 100 mm 3. This value can cause a change in the threshold voltage of about 0.1 Volt when the MOSFET of the SOI structure is manufactured.

두 번째, 반도체기판의 콘택이 없기 때문에 포화시 채널의 유동전하가 실리콘입자의 분자와 충돌하여 생기는 소수캐리어를 흡수해주는 경로가 없다.Second, because there is no contact of the semiconductor substrate, there is no path that absorbs the minority carriers generated by the channel's flow charge when it saturates the molecules of the silicon particles.

따라서, 상기 캐리어들은 필드에 의해 소오스/드레인으로 빠지게 되고, 이는, SOI 구조의 MOSFET의 드레인전류를 증가시키게 되는데 이를, 킹크 효과(KINK EFFECT)라 한다.Thus, the carriers are pulled into the source / drain by the field, which increases the drain current of the MOSFET of the SOI structure, which is referred to as a kink effect.

상기 킹크효과는 SOI 구조의 MOSFET을 이용한 회로설계에 제한을 가져오며 또, 채널영역에 발생하는 소수케리어들이 빨리 재결합되지 않는 경우 반도체기판에 축적되고, 이는 반도체기판의 바이어스를 증가시켜 SOI 구조의 MOSFET의 문턱전압을 낮추게 된다.The kink effect has a limitation in circuit design using a MOSFET having an SOI structure, and when a small number of carriers occurring in a channel region are not quickly recombined, the kink effect accumulates in a semiconductor substrate, which increases the bias of the semiconductor substrate and increases the MOSFET of the SOI structure. Will lower the threshold voltage.

위에서 언급한 상기 두가지 요인은 차세대 반도체소자로서 SOI 소자를 사용하는데 가장 큰 문제로 대두되고 있다.The two factors mentioned above are the biggest problems in using SOI devices as next-generation semiconductor devices.

제 2 도는 종래의 MESA 에치 방법에 의하여 제작된 SOI MOSFET의 단면도이다.2 is a cross-sectional view of a SOI MOSFET fabricated by a conventional MESA etch method.

제 2 도를 참조하면, 제1 실리콘(1)기판 상부에 제1 실리콘산화막(2)을 형성하고, 상기 제1 실리콘산화막(2)의 상부에 사다리꼴 모양의 제2 실리콘(3)층을 형성한다.Referring to FIG. 2, a first silicon oxide film 2 is formed on the first silicon substrate 1, and a trapezoidal second silicon 3 layer is formed on the first silicon oxide film 2. do.

그 다음, 상기 제2 실리콘기판(3)의 상부에 패드산화막을 형성하고, 소자 분리영역을 노출하는 식각마스크를 사용하여 상기 패드산화막을 식각하여 패드 산화막패턴을 형성한다.Next, a pad oxide layer is formed on the second silicon substrate 3, and the pad oxide layer is etched using an etching mask exposing the device isolation region to form a pad oxide layer pattern.

그 다음, 상기 패드산화막패턴을 식각장벽으로 하여 상기 제2 실리콘(3)층을 식각한다.Next, the second silicon 3 layer is etched using the pad oxide layer pattern as an etch barrier.

그 다음, 상기 제2 실리콘(3)층의 상부에 게이트산화막(7)과, 폴리실리콘층을 차례로 형성한 후, 상기 폴리실리콘층과 게이트산화막을 차례로 패터닝하여 게이트(8)와, 게이트산화막(7)패턴을 형성한다.Next, a gate oxide film 7 and a polysilicon layer are sequentially formed on the second silicon 3 layer, and then the polysilicon layer and the gate oxide film are patterned in sequence to form a gate 8 and a gate oxide film ( 7) Form a pattern.

그 다음, 상기 게이트(8)와, 게이트산화막(7)패턴을 마스크로 상기 제2 실리콘기판(3)에 고농도의 이온을 주입하여 고농도 이온주입영역(11)을 형성한다.A high concentration ion implantation region 11 is then formed by implanting high concentration ions into the second silicon substrate 3 using the gate 8 and the gate oxide film 7 pattern as a mask.

그 다음, 상기 구조의 전 표면에 제2 산화막(10)을 형성한 후, 전면식각하여 상기 게이트(8)의 측벽에 제2 산화막(10)스페이서를 형성한다.Next, after forming the second oxide film 10 on the entire surface of the structure, the entire surface is etched to form the second oxide film 10 spacer on the sidewall of the gate 8.

그 다음, 상기 구조의 전 표면에 절연막(12)을 형성하고, 콘택홀을 형성하기 위한 식각 마스크를 사용하여 상기 절연막(12)을 게이트(8) 와, 제2 실리콘(3)층이 노출될 때까지 식각하여 콘택홀을 형성한다.Then, the insulating film 12 is formed on the entire surface of the structure, and the gate 8 and the second silicon 3 layer are exposed through the insulating film 12 using an etching mask for forming contact holes. Etch until a contact hole is formed.

그 다음, 상기 콘택홀을 매립하는 금속패턴(13)을 형성한다.Next, a metal pattern 13 filling the contact hole is formed.

그러나, 상기 제 1 도의 SOI 소자의 문제점을 그대로 가지는 동시에, MESA 식각된 실리콘면이 (111) 방향을 가져 SOI MOSFET의 문턱전압은 표면상태로 인해 다르므로 MOSFET의 준 문턱전압(subthreshold) 영역에서 두 개의 문턱전압을 갖게 되어 킹크 현상이 나타나는 문제점이 있다.However, while the problem of the SOI device of FIG. 1 remains as it is, the MESA-etched silicon surface has a (111) direction, so that the threshold voltage of the SOI MOSFET is different due to the surface state, so that the two threshold voltages of the SOI device are different in the MOSFET subthreshold region. There is a problem in that there is a kink phenomenon due to the two threshold voltages.

따라서, 본 발명의 목적은 상기 문제점을 해결하기 위하여, 필드산화막 하부에 일정두께의 제2실리콘을 확보하고 불순물을 주입하여 채널 스토퍼를 형성함으로써 필드산화막의 내측(트랜지스터를 기준으로 할 때) 에 형성된 트랜지스터가 상기 필드산화막의 하부로 연결된 제2실리콘을 상기 필드산화막의 외측에 형성하여 반도체기판의 콘택을 형성할 수 있도록 하고 그에 따른 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체 SOI 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a channel stopper by securing a second silicon having a predetermined thickness under the field oxide film and injecting impurities to form a channel stopper in order to solve the above problems. A method of manufacturing a semiconductor SOI device in which a transistor forms a second silicon connected to a lower portion of the field oxide film outside the field oxide film to form a contact of a semiconductor substrate, thereby improving characteristics and reliability of the semiconductor device. The purpose is to provide.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체 SOI 소자의 제조 방법은, 반도체 에스.오.아이. 소자의 제조방법에 있어서, 기판인 제1 실리콘 상부에 매립층과 박막인 제2실리콘을 순차적으로 적층하는 공정과, 상기 제2실리콘의 비활성영역에 필드산화막을 형성하되, 상기 제2실리콘의 일정두께를 열산화시켜 형성함으로써 상기 필드산화막의 하부에 제2실리콘을 확보하는 공정과, 상기 제2실리콘 하부의 비활성영역에 채널스토퍼를 형성하는 공정과, 상기 필드산화막의 내측에 LDD 구조의 트랜지스터를 형성하여 상기 트랜지스터가 상기 제2실리콘을 통해 필드산화막의 외측과 연결되는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, the manufacturing method of the semiconductor SOI element which concerns on this invention is a semiconductor S.O.I. A method of manufacturing a device, comprising: sequentially depositing a buried layer and a thin film of second silicon on a first silicon, which is a substrate, and forming a field oxide film in an inactive region of the second silicon, wherein a predetermined thickness of the second silicon is formed Thermally oxidizing to form a second silicon under the field oxide film, forming a channel stopper in an inactive region under the second silicon, and forming an LDD structure transistor inside the field oxide film. And the transistor is connected to the outside of the field oxide film through the second silicon.

이상의 목적을 달성하기 위한 본 발명의 원리는, 매립층 상부에 형성되는 필드산화막 하부에 채널스토퍼가 형성된 제2실리콘을 확보하여 필드산화막 내측에 트랜지스터가 형성되고 하측에 매립층이 형성된 형태로 플로팅 (floating) 되어 있는 트랜지스터의 문제점을 해결하기 위하여, 제2실리콘의 필드산화공정시 필드산화막이 상기 제2실리콘과 접촉되지 않도록 상기 제2실리콘층의 50 - 90% 두께로 필드산화공정을 실시함으로써 필드산화막 하측을 통하여 상기 필드산화막 내측에 제2실리콘이 외측의 제2실리콘과 연결되도록 형성하고 상기 제2실리콘에 반도체기판의 콘택을 형성할 수 있도록 하는 것이다.The principle of the present invention for achieving the above object is to ensure the second silicon formed with a channel stopper on the bottom of the field oxide film formed on the buried layer to form a transistor formed inside the field oxide film and the buried layer formed in the bottom (floating) In order to solve the problem of the transistor, the field oxide film is formed by performing a field oxidation process with a thickness of 50 to 90% of the second silicon layer so that the field oxide film does not come into contact with the second silicon during the field oxidation process of the second silicon. The second silicon is formed in the field oxide layer so as to be connected to the second silicon outside, and a contact of the semiconductor substrate may be formed in the second silicon.

이하, 첨부된 도면을 참조하여 본 발명의 실시예에 대한 상세한 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제 3A 도 및 제 3B 도는 본 발명의 실시예에 따른 SOI 구조의 MOSFET 제조 공정도이다.3A and 3B are MOSFET manufacturing process diagrams of the SOI structure according to the embodiment of the present invention.

제 3A 도를 참조하면, 제1 실리콘(1)기판 상부에 매립절연막인 제1 실리콘산화막(2)을 형성하고, 상기 제1 실리콘산화막(2) 상부에 제2 실리콘(3)층을 형성한다.Referring to FIG. 3A, a first silicon oxide film 2, which is a buried insulating film, is formed on the first silicon substrate 1, and a second silicon 3 layer is formed on the first silicon oxide film 2. .

그 다음, 상기 제2 실리콘(3)층의 상부에 패드산화막(4)과 질화막(5)을 각각 일정두께 형성한다.Next, a pad oxide film 4 and a nitride film 5 are formed on the second silicon 3 layer at a predetermined thickness.

그리고, 소자분리마스크를 이용한 식각공정으로 상기 질화막(5)과, 패드 산화막(4)을 식각하여 질화막(5)패턴과, 패드산화막(4)패턴을 형성한다.The nitride film 5 and the pad oxide film 4 are etched by an etching process using an element isolation mask to form the nitride film 5 pattern and the pad oxide film 4 pattern.

그 다음, 상기 질화막(5)패턴과 패드산화막(4)패턴을 장벽으로 하여 상기 제2 실리콘(3)층을 열산화시켜 성장시키되, 상기 제2 실리콘(3)층 증착두께의 50내지 90% 정도의 두께로 성장시켜 필드산화막(6)을 형성한다.Next, the second silicon (3) layer is thermally oxidized to grow using the nitride film (5) pattern and the pad oxide film (4) pattern as a barrier, and the thickness of the second silicon (3) layer is 50 to 90%. The field oxide film 6 is formed by growing to a thickness of a degree.

제 3B 도를 참조하면, 상기 질화막(5)패턴과 패드산화막(4)패턴을 차례로 식각하여 제거한다.Referring to FIG. 3B, the nitride film 5 pattern and the pad oxide film 4 pattern are sequentially removed by etching.

그 다음, 상기 필드산화막(6)의 하부에 채널 스톱 임플랜트 (channel stop implant) 공정을 실시하여 상기 필드산화막(6)의 하부에 도핑영역인 채널 스토퍼(14)를 형성한다.Next, a channel stop implant process is performed under the field oxide film 6 to form a channel stopper 14 as a doped region under the field oxide film 6.

그 다음, 상기 전체표면상부에 게이트산화막(7)과 폴리실리콘층을 차례로 형성하고, 게이트전극마스크를 이용한 식각공정으로 상기 폴리실리콘층과 게이트산화막(7)을 식각하여 게이트(8)를 형성한다.Next, a gate oxide film 7 and a polysilicon layer are sequentially formed on the entire surface, and the polysilicon layer and the gate oxide film 7 are etched by an etching process using a gate electrode mask to form a gate 8. .

그리고, 상기 게이트(8)를 마스크로 상기 제2 실리콘(3)층에 저농도의 불순물이온을 주입하여 저농도 이온주입영역(9)을 형성한다.A low concentration of ion implantation region 9 is formed by implanting low concentration of impurity ions into the second silicon 3 layer using the gate 8 as a mask.

그 다음, 상기 구조의 전 표면에 제2 산화막(10)을 일정두께 형성한 후, 전면 이방성식각하여 상기 게이트(8)의 측벽에 제2 산화막(10) 스페이서를 형성한다.Next, after the second oxide film 10 is formed to a predetermined thickness on the entire surface of the structure, the entire surface is anisotropically etched to form a second oxide film 10 spacer on the sidewall of the gate 8.

그리고, 상기 게이트(8)와 제2 산화막(10) 스페이서를 마스크로 상기 제2 실리콘(3)층에 고농도의 불순물이온을 주입하여 고농도 이온주입영역(11)을 형성한다.A high concentration ion implantation region 11 is formed by implanting a high concentration of impurity ions into the second silicon layer 3 using the gate 8 and the second oxide film 10 spacers as a mask.

그 다음, 상기 구조의 전 표면에 절연막(12)을 형성하고 평탄화시킨다. 그리고, 콘택마스크를 이용한 식각공정으로 상기 절연막(12)을 식각하여 상기 제2실리콘(3)층과 게이트(8)를 각각 노출시키는 제1콘택홀(20)과 제2콘택홀(30)을 형성한다.Then, an insulating film 12 is formed and planarized on the entire surface of the structure. The first contact hole 20 and the second contact hole 30 exposing the second silicon 3 layer and the gate 8 are etched by etching the insulating layer 12 by an etching process using a contact mask. Form.

그리고, 상기 콘택홀(20, 30)을 통하여 상기 제2실리콘(3)층과 게이트(8)에 접속되는 금속패턴(13)을 형성한다.The metal pattern 13 is formed to be connected to the second silicon 3 layer and the gate 8 through the contact holes 20 and 30.

이상에서 설명한 바와같이 본 발명에 따른 반도체 SOI 소자의 제조방법은, 필드산화막 하부에 채널스토퍼가 있는 제2실리콘층을 확보하여 트랜지스터가 형성된 제2실리콘층이 플로팅되지 않도록 하고 후속공정으로 반도체기판의 콘택이 이루어지도록 함으로써 킹크 효과를 방지하고 문턱전압의 변화를 방지 할 수 있어 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, in the method for manufacturing a semiconductor SOI device according to the present invention, a second silicon layer having a channel stopper is secured under the field oxide layer so that the second silicon layer on which the transistor is formed is not floated, and the semiconductor substrate is subsequently processed. By making the contact, it is possible to prevent the kink effect and to prevent the change of the threshold voltage, thereby improving the characteristics and reliability of the semiconductor device.

Claims (2)

반도체 에스.오.아이 소자의 제조 방법에 있어서, 기판인 제1실리콘 상부에 매립층과 박막인 제2실리콘을 순차적으로 적층하는 공정과, 상기 제2 실리콘의 비활성영역에 필드산화막을 형성하되, 상기 제2실리콘의 일정두께를 열산화시켜 형성함으로써 상기 필드산화막의 하부에 제2실리콘을 확보하는 공정과, 상기 제2실리콘 하부의 비활성영역에 채널스토퍼를 형성하는 공정과, 상기 필드산화막의 내측에 LDD 구조의 트랜지스터를 형성하여 상기 트랜지스터가 상기 제2실리콘을 통해 필드산화막의 외측과 연결되는 공정을 포함하는 반도체 에스.오.아이. 소자의 제조방법.A method of manufacturing a semiconductor S.I.I device, comprising: sequentially depositing a buried layer and a second silicon, which is a thin film, on a first silicon, which is a substrate, and forming a field oxide film in an inactive region of the second silicon, wherein Forming a second silicon under the field oxide film by thermally oxidizing a predetermined thickness of the second silicon, forming a channel stopper in an inactive region under the second silicon, and forming the inside of the field oxide film. Forming a transistor having an LDD structure such that the transistor is connected to the outside of the field oxide film through the second silicon. Method of manufacturing the device. 제 1항에 있어서, 상기 열산화공정은 상기 제2실리콘의 50 - 90% 두께로 실시하는 것을 특징으로 하는 반도체 에스.오.아이. 소자의 제조 방법.The semiconductor S.I.I. method according to claim 1, wherein the thermal oxidation process is performed at a thickness of 50-90% of the second silicon. Method of manufacturing the device.
KR1019950066069A 1995-08-21 1995-12-29 Fabricating method of s.o.i. semiconductor device KR100197656B1 (en)

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US08/696,163 US5899712A (en) 1995-08-21 1996-08-13 Method for fabricating silicon-on-insulator device
JP8358680A JP2936536B2 (en) 1995-12-29 1996-12-27 Semiconductor device and method of manufacturing the same
GB9626975A GB2308739B (en) 1995-12-29 1996-12-27 Semiconductor device and a manufacturing method for the same
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