JPH0888233A - Manufacture of vertical mos semiconductor device - Google Patents

Abstract

PURPOSE: To form a second conductivity area through a self-aligning process by filling up removed parts with a masking material layer and removing a conductive material layer in the area between paired gate electrodes after leaving the conductive material layer in the area between the gate electrodes at the time of patterning the gate electrodes. CONSTITUTION: At the time of forming a gate oxide film 2 and gate electrodes 3 on the surface of a silicon substrate 1, etching is performed so as to leave a polycrystalline Si layer 30 at the part against which second boron ion implantation is performed. When first boron ion implantation and high-temperature heat treatment are performed after ashing a resist 4, a p-n junction is formed between a p-well 5 and the n-type substrate 1. After forming the p-n junction, the widow part used as a window for ion implantation is filled up with an appropriate material. Then, a window is opened through the gate oxide film 2 by patterning and dry-etching the resist 4 after applying the resist 4 again. After ashing the resist 4, a p<+> -area 51 is formed by removing the thermal oxide film 81 and by using the boron 61 implanted at the second time as a diffusing source. The following processes are the same as those of the conventional method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a vertical MOS semiconductor device in which a main current mainly flows in a direction perpendicular to a main surface of a semiconductor substrate.

[0002]

2. Description of the Related Art At present, a vertical MOS-FET is used as a main semiconductor element such as a switching power supply and a large current drive circuit. This is because the voltage-driven element is suitable for computer control, and because the main current can be switched at high speed, various waveforms can be formed, so that its range of use has expanded. Further, composite elements such as IGBT and MOS-thyristor have been developed and commercialized by taking advantage of such characteristics. The basic manufacturing method of these semiconductor elements is a vertical MOS-FET.
Is the same as.

2A to 2E show a conventional vertical MOS.
-A part of the manufacturing process of the FET is shown. n-type silicon substrate 1
Then, a gate oxide film 2 is formed by thermal oxidation, and then a reduced pressure C
Polycrystalline Si layer 30 serving as a gate electrode using a VD device or the like
Are laminated. Next, in order to process the polycrystalline Si layer 30 into the gate electrode 3, the resist 4 is applied and patterned [FIG. 2 (a)]. The exposed polycrystalline Si layer 30 is removed by a dry etching method or the like. Remaining resist 4
Is ashed and removed. In this state, boron is implanted using an ion implanter. At this time, boron is implanted through the gate oxide film 2 on the surface of the silicon substrate 1 where the polycrystalline Si layer 30 is removed, but at the other portions, the gate electrode 3 is formed.
Blocked by. After that, by performing a high temperature heat treatment at about 1150 ° C., the implanted boron is diffused inside the silicon substrate 1 to form a p-type region p well 5 as shown in FIG. 2 (b). Next, apply the resist 4 again,
A photomask is aligned with the arrangement of the lower polycrystalline Si layer 3, and the resist 4 is patterned to open a window for ion implantation. By design, the remaining portion of the resist 4 between the edge of the gate electrode 3 and the opened window must be bilaterally symmetrical.
Due to the problem of alignment accuracy of the photomask and the like, they are not always symmetrical, and are slightly deviated as shown in FIG. 2 (c). In this state, the ion implantation device is used to perform the second implantation of boron 61. When the high temperature heat treatment is performed again after the resist 4 is ashed, the p ⁺ region 51 having a higher boron concentration is formed inside the p well 5 due to the diffusion using the boron 61 implanted the second time as a diffusion source [FIG. 2 (d)]. The dose of the second boron implantation is about two orders of magnitude higher than that of the first time, and the high temperature heat treatment is usually performed at 1150 ° C. or lower. It is also possible to omit the initial high temperature heat treatment and simultaneously perform diffusion at this time. The important point is that the boron concentration on the outermost surface of the silicon substrate 1 is divided into a region 5 determined by the first boron implantation and a region 51 determined by the first and second additions. Then, resist coating and patterning are performed again, and a part of the portion having the window for the second boron implantation is covered with the resist 4. [Fig. 2 (e)].
Then, arsenic 62 is implanted using an ion implanter in order to form the n ⁺ region 7 serving as the source region. The dose amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² , and the gate electrode 3
And on the surface of the silicon substrate 1 between the gate electrode and the resist. The first boron implantation and the arsenic implantation at the time of forming the p-well 5 are both ion-implanted into the silicon substrate 1 with the edge portion of the gate electrode 3 as a boundary, and therefore are so-called self-alignment processes with less fluctuation in manufacturing. .
After the state shown in FIG. 2E, there is a series of steps such as removing the resist 4 and performing a heat treatment for activating arsenic, and then laminating an interlayer insulating film, forming a contact hole, vapor deposition of an electrode metal, and patterning. However, it is omitted here. The cross-sectional structure shown in FIG. 2 exists as a stripe-shaped, circular, or rectangular cell-shaped simple substance in a two-dimensional plane. A plurality of simple substances are arranged on the plane of the silicon substrate 1, and the gate electrode 3 is a gate electrode. The n ⁺ region 7 is electrically connected to the terminal at one location or a plurality of locations respectively at the source electrode. A pressure resistant structure that surrounds all of these,
A drain electrode on the back surface of the silicon substrate 1 is formed to form one vertical MOS-FET.

[0004]

A vertical M according to the prior art.
In the method of manufacturing the OS-FET, the second boron implantation shown in FIG. 2C does not become a self-alignment step, so that the p well 5 and the p ⁺ region 51 are inevitably deviated from each other and asymmetrical cannot be prevented. Until now, this asymmetry has been accepted as a design margin because it is not a factor that largely determines the electrical characteristics of a MOS-FET that is a unipolar element. However, in recent years, miniaturization of a stripe-shaped or cell-shaped single body, active utilization of a pn diode existing between the n-substrate 1 and the p-region 5 on an electric circuit as a freewheeling diode, and further, the IGBT described above. With the advent of MOS devices including bipolar operations such as MOS and thyristors, the above asymmetry cannot be ignored.

The reason for this will be briefly described with reference to FIG.
It Free-wheeling die for n-channel MOS-FET
When used as an ode, it is connected to the source electrode 8.
Connect the source terminal S to the positive electrode of the power supply and the drain electrode 9.
Connected drain terminal D to the negative pole. Also, the gate power
The channel will not open to the gate terminal G connected to pole 3.
A bias potential should be applied as described above. p-well 5 and silicon
Since the pn junction composed of the substrate 1 is in the forward bias state, p
A current flows from the well 5 toward the silicon substrate 1. Electric current
Flow through a path with low electrical resistance or high electric field strength.
Therefore, in order to obtain excellent diode characteristics, p⁺
It is desired to diffuse the region 51 deeply to make the resistance as low as possible. Shi
However, due to the asymmetry, the electrical resistance also has asymmetry.
As shown in FIG. 3, the p-well 5 and the n-type
In the part where the curvature of the pn junction between the plates 1 is large, p⁺Area 51
It becomes easier for the current 10 to concentrate on the side closer to the
It deteriorates the ion characteristics. Also the effect of deep diffusion
Also appears in the boron concentration of the MOS channel on the left and right of the surface,
The threshold balance is lost. For example, in Figure 2 (c)
Between the edge of the gate electrode 3 and the window of the resist 4
Even if the width is designed to be 1 μm, an error of ± 0.2 μm actually occurs.
I will mess up. If the maximum case is assumed, leave the resist
The width is 0.8 μm on one side and 1.2 μm on the other side. Deep
Assume that the ratio of the diffusion distance in the horizontal direction to the horizontal direction is 1: 0.5
And in this case p which does not affect the MOS characteristics ⁺Area 51
The diffusion depth is 1.6 μm. 2.0 as designed
μm is allowed, and this difference is enough for the forward characteristic of the diode.
Influence, and the depth of the p-well 5 is shallow due to miniaturization.
The more it becomes, the more remarkable it becomes. In this way, with unipolar characteristics
To maximize the bipolar operation, the variation
Since it is necessary to suppress it as much as possible, the bubble of the photomask
A highly accurate device must be installed. But,
Manufacturing stability is increased, but the problem of higher costs and more
The same problem came up again when we needed to make the layers finer.
Therefore, it does not solve the problem.

An object of the present invention is to solve the above-mentioned problems and form a region for forming a pn junction for bipolar operation and a high impurity concentration region formed in the surface layer of the region by a self-aligning process. And a vertical MOS for forming a channel region for unipolar operation in a self-aligning process
It is to provide a method for manufacturing a semiconductor device.

[0007]

In order to achieve the above object, the present invention provides a first second conductivity type region selectively formed in a first conductivity type layer of a semiconductor substrate and a first second conductivity type region thereof. A second second conductivity type region having a higher impurity concentration than the first region selectively formed in the central portion of the surface layer of the second conductivity type region,
A region of the second conductivity type sandwiched between the source region of the first conductivity type selectively formed on the surface layer of the first and second second conductivity type regions and the exposed portion of the first conductivity type layer. In a method of manufacturing a vertical MOS semiconductor device in which a gate electrode is provided as a channel region via a gate insulating film, a conductive material layer is formed on the surface of a first conductivity type layer of a semiconductor substrate via the insulating film. A step of patterning the conductive material layer to form a pair of gate electrodes, and leaving the conductive material layer in the center of the portion sandwiched between the gate electrodes;
A step of filling a portion sandwiched between the gate electrode and the residual conductive material layer with a mask material, a step of selectively etching and removing the residual conductive material layer to leave a mask made of the mask material, and using the gate electrode as a mask. A step of introducing impurities for forming the first second conductivity type region, a step of introducing impurities for forming the second second conductivity type region using a mask made of a mask material, and a channel for the gate electrode And a step of introducing an impurity for forming a source region as a mask covering the region. A silicon element body is used as a semiconductor substrate, polycrystalline silicon is used as a conductive material, a silicon oxide layer formed by oxidizing the surface of the silicon element body is used as a mask material, and a polycrystalline silicon layer is used by utilizing a difference in etching rate. Is selectively removed to leave the silicon oxide layer. In that case, when the surface of the silicon element body is oxidized to form a silicon oxide layer as a mask material, the silicon oxide layer formed on the polycrystalline silicon layer is replaced by the silicon oxide layer formed by the oxidation of the silicon element body. It may be removed selectively by utilizing the difference in etching rate between the two. Then, it is preferable to use reactive ion etching when patterning the polycrystalline silicon layer to form the gate electrode, and leaving the polycrystalline silicon layer having a smaller thickness than the gate electrode in the center of the portion sandwiched between the gate electrodes. .

[0008]

When the gate electrode is patterned from the conductive material layer, the conductive material layer is left in the center of the pair of gate electrodes, and the portion where the conductive material layer is removed is filled with the mask material layer.
By removing the central conductive material layer by a method such as utilizing the difference in etching rate, the removed portion becomes a window for impurity introduction for forming the second second conductivity type region. Thereby, the second second conductivity type region can be formed by a substantially self-aligning process with the first second conductivity type region formed by using the gate electrode as a mask. Further, by using the gate electrode as a mask for controlling the channel region side when forming the source region, the source region can also be formed with the second conductivity type region by a self-alignment process. When polycrystalline silicon is used as the conductive material of the gate electrode in performing such a process, a difference in etching rate occurs between the polycrystalline silicon and the oxide film on the surface of the silicon element body using polycrystalline silicon as a mask material. It is possible to easily remove the crystalline silicon and leave the silicon oxide film as a mask. Further, the oxide film formed on the surface of the polycrystalline silicon layer when the surface of the silicon body is oxidized has a difference in etching rate from the oxide film formed on the surface of the silicon body, so that the oxide film of the mask material remains. By removing the oxide film on the surface of the polycrystalline silicon layer, the polycrystalline silicon layer of the gate electrode can be exposed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings including the same parts in FIG. Embodiment 1 In the embodiment shown in FIGS. 1 (a) to 1 (e), it is the same as the conventional method until the gate oxide film 2 is formed on the surface of the n-type silicon substrate 1 and a polycrystalline silicon layer is laminated. When the polycrystalline silicon layer is patterned to form the gate electrode 3, dry etching is performed so that the polycrystalline Si layer 30 is left on the surface of the portion of the silicon substrate 1 where the second boron ion implantation is performed. The sectional structure is as shown in FIG. After the resist 4 is ashed, the first boron ion implantation is performed, and then the high temperature heat treatment is performed.
The heat treatment was performed at 1150 ° C. for about 3 hours, depending on the impurity concentration of the substrate, depending on the impurity concentration of the substrate, 3 μm in the depth direction from the surface of the gate electrode 3.
A pn junction between the p-well 5 and the n-substrate 1 is formed at a position 2 μm laterally from below the edge of the substrate. Polycrystalline Si left
If the width of the layer 30 is about 1 μm, the pn junction is continuously formed thereunder. Next, the portion used as the ion implantation window is filled with an appropriate material. As this material, it is necessary to select a material having a high etching selection ratio with respect to polycrystalline Si. In this embodiment, thermal oxide films of single crystal Si and polycrystalline Si are used. As a heat treatment condition for oxidation, it is preferable to use a combustion method of hydrogen gas H ₂ and oxygen gas O ₂ at a relatively low temperature of 750 to 850 ° C. The thickness of the oxide film needs to be at least 3000Å,
This thickness control can be performed by heat treatment time. This oxidation process
Continuous processing is possible using the same electric furnace as the preceding high temperature heat treatment. At this stage, the cross-sectional structure shown in FIG. 1 (b) is obtained.

The oxide film 82 formed of polycrystalline Si and the oxide film 81 formed of polycrystalline Si have almost the same film thickness.
000Å, but in the former case where the refractive index is 1.44 to 1.45
In the latter case, it is 1.46. This difference can be used as a difference in properties for wet etching.
For example, by volume ratio nitric acid (70%): hydrofluoric acid (49%):
When an etching solution of H ₂ O = 2: 3: 60 is used, the etching rate of the oxide film 82 made of polycrystalline Si is 3 to 10 times faster, so that it can be selectively etched. Although the difference in etching rate differs depending on the crystallinity of polycrystalline Si, the oxidizing conditions, the composition ratio of the etching solution, and the temperature, wet etching with high selectivity is possible by controlling these. As a result, the polycrystalline Si layers 3 and 30 can be exposed, and the thermal oxide film 81 on the silicon substrate 1 can be left therebetween. Next, the resist 4 is applied and patterned again. This resist 4 is made of polycrystalline Si when the etching for removing the polycrystalline Si layer 30 is performed in the next step.
Although the gate electrode 3 is covered so as not to be etched, the alignment accuracy with the gate electrode 3 is not important. However, the edge of the resist 4 must be located on the thermal oxide film 81, and the edge of the resist 4 and the thermal oxide film 8 must be located.
The width between the edge and the edge of 1 is preferably at least 2 μm. After patterning the resist 4, only the exposed polycrystalline Si layer 30 is dry-etched. For example, when SF ₆ is used as the etching gas, the etching rate of the polycrystalline Si layer 30 with respect to the oxide film 81 is about 10 times, so that the selective etching can be easily performed, and the thick thermal oxide film 81 as shown in FIG. A thin gate oxide film 2 window surrounded by is formed. The position of the peripheral edge of this window is almost determined by the photomask at the time of etching the first polycrystalline Si layer 30 shown in FIG. 1A and does not depend on the subsequent mask alignment accuracy. Therefore, the first and second ion implantations are performed. Is a pseudo self-alignment process. The acceleration voltage during the second boron 61 ion implantation is determined in consideration of the thickness of the thermal oxide film 81. Considering a slight decrease of 3000 Å, it was set to 40 KeV here. Conventionally, it was a relatively high value of about 150 KeV, but there is no effect because deep thermal diffusion is performed in the subsequent process.

After the resist ashing, the thermal oxide film 81 is removed with an aqueous solution of hydrofluoric acid, and the high temperature heat treatment is performed again to use the boron 61 injected the second time as a diffusion source to form the p ⁺ region 51 as shown in FIG. 1 (d). It As described above, since the boron concentration on the outermost surface is required to be divided into a region determined by the first boron implantation and a region determined by the first and second additions, it is already 2 μm or more on the mask. In the case of this embodiment having a difference of 1), the cross-sectional shape as shown in FIG.
It is advantageous to perform the heat treatments at the same time from the viewpoint of reducing the number of steps and making the p ⁺ region 51 as wide as possible. The steps after FIG. 1E are exactly the same as the conventional method. Note that the mask of the resist 4 that regulates the inner edge of the source region 7 does not affect the width of the channel region and the impurity concentration even if the alignment accuracy thereof is slightly different.

In order to confirm the effect of the present invention on the device characteristics, the forward voltage drop of the freewheeling diode incorporated in the MOS-FET and the heat treatment after the second boron implantation for forming the p ⁺ region 51 are performed. I investigated the relationship of time. The circles and the crosses in the graph of FIG. 4 are measured values according to the present invention and those according to the conventional method, respectively, and the area of the active region of the element is the same, and the effect of the heat treatment is remarkable for the current.
The magnitude of sufficient conductivity modulation was selected and made constant. Since the p-well 5 has already been formed in both devices, it is considered that the shape of the pn junction hardly changes.
In the heat treatment step, the furnace is placed at 700 ° C., the temperature is raised to 1100 ° C. at a constant temperature rising speed, and the temperature is maintained for a fixed time. After that, it is cooled to 700 ° C. at a constant temperature decrease speed and taken out of the furnace. The heat treatment time shown in the graph is 1100 ° C.
It is a time kept for a long time, and even if it is 0 minute, the annealing treatment for activating the impurities is sufficiently received.

From 0 to 20 minutes, no significant difference is observed in the conventional method of the present invention. There is a difference in the voltage drop between 30 minutes and 90 minutes, and after that, both elements have a constant voltage drop. In the region where the heat treatment time is short, the diode characteristics are p-well 5 and n-type silicon substrate 1.
No difference is seen because it is determined by the pn junction consisting of. The decrease in the voltage drop is observed earlier in the device manufactured by the conventional method. A closer look at the current / voltage characteristic waveform shows that the current rising portion is almost unchanged, but the slope of the current / voltage characteristic at the observed current value is steeper in the element by the conventional method. This means that in the device by the conventional method having a structure in which current concentration easily occurs,
This is because sufficient conductivity modulation must occur early, and once conductivity modulation occurs, the dependence on the device structure becomes less susceptible, and the voltage drop quickly settles to a fixed value. On the other hand, in the device according to the present invention, a current can flow uniformly inside the device, and since the same current is passed, the degree of conductivity modulation may be small,
It can be inferred that the result shown in FIG. 4 was obtained. In order to support the above result, a large pulse current was repeatedly applied and the state of heat generation of the element was observed with an infrared camera. From these results, it was found that the element according to the conventional method has a variation in the temperature distribution, but the element according to the present invention has improved the temperature distribution, and the thermal breakdown due to the current concentration of the bipolar element is less likely to occur.

Example 2 In Example 1, in order to expose the window portion for the second boron ion implantation, when the window for the first ion implantation is opened as shown in FIG. 1C, the resist 4 is used. Since this mask was used, it cannot be applied to fine cells due to its restrictions. Therefore, a method of another embodiment improving this point is shown in FIGS. 5 (a) to 5 (f).

Similar to the conventional method, resist coating and patterning are performed for poly-Si etching. Then, etching is performed, and anisotropic reactive ion etching (RIE) is generally used. In the process of investigating various RIE conditions and the progress of etching, the inventors of the present invention conducted the polycrystalline Si layer 3 in the vicinity of the resist mask before the polycrystalline Si etching as shown in FIG. It has been found that there are conditions for etching. Under the etching conditions in which such a process appears remarkably, the etching is once stopped when the underlying gate oxide film 2 is exposed. After exhausting the reaction gas sufficiently, etching is performed under isotropic RIE conditions to expand the exposed area of the gate oxide film 2 and the thickness of the remaining polycrystalline Si layer 30 to 1
000 to 1500Å. By combining the two types of etching in this way, Fig. 5 (b)
As described above, a polycrystalline Si layer 30 having a taper is formed. In order to improve the reproducibility of the exposed area of the gate oxide film 2 and the thickness of the polycrystalline Si layer 30, it is necessary to select isotropic RIE conditions in which the etching rate is as slow as possible. The anisotropic and isotropic RIE conditions are extremely device-dependent and cannot be generally stated, but Table 1 shows an example.

[0016]

[Table 1] After ashing the resist, the first boron ion implantation is performed. The boron 61 penetrates through the gate oxide film 2 to form the silicon substrate 1
It is driven into the surface [Fig. 5 (c)]. Thick polycrystalline Si
Although the implantation of boron 61 is blocked in the portion where the gate electrode 3 remains, it does not matter if boron is implanted into the surface of the underlying silicon substrate 1 through the thin polycrystalline Si layer 30 and the gate oxide film 2. Absent. This is because, in the subsequent process, it is possible to ignore it because the same portion is implanted by about double digits as compared with the first boron ion implantation. After the ion implantation of boron 61, the exposed gate oxide film 2 is removed with a dilute aqueous solution of acid, and then high temperature heat treatment is performed at 1150 ° C. for about 3 hours and combustion of hydrogen gas H ₂ and oxygen gas O ₂ is performed as in Example 1. Low temperature oxidation is performed by the method. By this oxidation, all of the thin polycrystalline Si layer 30 is no longer consumed as the material of the oxide film 82, so that the sectional structure shown in FIG. 5D is obtained.

Similar to the first embodiment, when the oxide film 82 made of polycrystalline Si is selectively wet-etched, the dense thermal oxide film 81 made of the silicon substrate 1 and the gate oxide film 2 are left, and FIG. As shown in (e), the second ion implantation of boron 61 is directly performed using the thermal oxide film 81 as a mask. Also here, if the conditions are determined while paying attention to the same acceleration voltage as in Example 1, boron ion implantation can be performed on the target surface of the silicon substrate 1. The subsequent steps are the same as in Example 1.

The present embodiment shows that the present invention can be applied to a fine structure, and the number of photomasks can be reduced by one from the first embodiment. By arranging a large number of fine-structured single bodies, the current to be carried by the single cells can be small. Therefore, as in the first embodiment, the MOS-FET is the same.
We investigated the forward voltage drop and the effect of miniaturization of the free-wheel diode built in the. As a result, in the device according to the conventional method, a decrease in the forward voltage drop due to the miniaturization was hardly observed, but in the device according to Example 2, the decrease tendency in the voltage drop due to the miniaturization was observed. In the element according to the present embodiment, the current flows uniformly, so that the effect of the breakdown withstanding capability during the switching operation can be expected, and the IGBT and the MOS can be expected.
-Suitable for improving the characteristics of thyristors.

[0019]

According to the present invention, when the gate electrode is patterned from the conductive material layer, the conductive material layer is left in the center of the pair of gate electrodes, and both sides thereof are filled with the mask material, whereby the center of the gate electrode is filled. Moreover, a mask for introducing impurities for forming the second second conductivity type region can be formed. As a result, a region for performing a MOS operation and a region for performing a bipolar operation are formed by a pseudo self-alignment process to form a vertical MOS.
It has become possible to manufacture semiconductor devices.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a manufacturing process of a vertical MOS-FET according to an embodiment of the present invention in the order of (a) to (e).

FIG. 2 shows an essential part of a conventional vertical MOS-FET manufacturing process.
Sectional views shown in the order of (a) to (e)

FIG. 3 is a sectional view showing a defect of a vertical MOS-FET manufactured by a conventional manufacturing method.

FIG. 4 is a diagram showing the relationship between the forward voltage drop and the heat treatment time for forming the p ⁺ region of the vertical MOSFET according to the manufacturing method of the embodiment of the present invention and the conventional manufacturing method.

FIG. 5 is a cross-sectional view showing the main parts of a manufacturing process of a vertical MOS-FET of another embodiment of the present invention in the order of (a) to (f).

[Explanation of symbols]

1 n-type silicon substrate 2 gate oxide film 3 gate electrode 30 polycrystalline Si layer 4 resist 5 p well 51 p ⁺ region 61 boron 62 arsenic 7 source region 81, 82 thermal oxide film

Claims (4)

[Claims] 1. A first second conductivity type region selectively formed in a first conductivity type layer of a semiconductor substrate and a central portion of a surface layer of the first second conductivity type region. A source region of the first conductivity type having a second second conductivity type region having an impurity concentration higher than that of the first region and selectively formed on a surface layer of the first and second second conductivity type regions. In the method of manufacturing a vertical MOS semiconductor device, the second conductivity type region sandwiched between the first conductivity type layer and the exposed portion of the first conductivity type layer is used as a channel region, and a gate electrode is provided thereon via a gate insulating film. A step of forming a conductive material layer on the surface of the first conductivity type layer of the substrate through an insulating film, and patterning the conductive material layer to form a pair of gate electrodes, and a portion sandwiched between the gate electrodes. To leave the conductive material layer in the center of the A step of filling the portion held postal layer with a mask material, a step of leaving a mask made of a mask material is removed by selectively etching the remaining conductive material layer,
A step of introducing impurities for forming the first second conductivity type region using the gate electrode as a mask, and a step of introducing impurities for forming the second second conductivity type region using a mask made of a mask material, And a step of introducing an impurity for forming a source region by using the gate electrode as a mask for covering the channel region, the method for manufacturing a vertical MOS semiconductor device. 2. A silicon base body is used as a semiconductor substrate, polycrystalline silicon is used as a conductive material, and a silicon oxide layer formed by oxidizing the surface of the silicon base body is used as a mask material. 2. The method for manufacturing a vertical MOS semiconductor device according to claim 1, wherein the polycrystalline silicon layer is selectively removed and the silicon oxide layer is left. 3. A silicon oxide layer formed on a polycrystalline silicon layer when a surface of a silicon element body is oxidized to form a silicon oxide layer as a mask material. 3. The method for manufacturing a vertical MOS semiconductor device according to claim 2, wherein the vertical MOS semiconductor device is selectively removed by utilizing the difference in etching rate from the silicon layer. 4. Reactive ion etching is used in forming a gate electrode by patterning a polycrystalline silicon layer,
4. The method for manufacturing a vertical MOS semiconductor device according to claim 2, wherein a polycrystalline silicon layer having a thickness smaller than that of the gate electrode is left in the center of the portion sandwiched by the gate electrodes.