JPH07273323A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the impurity concentration of the surface of a wafer from lowering and to control the thickness of an oxide film to a specified value accurately by forming a thin first oxide film, and growing the first oxide film up to the specified thickness by a second thermal oxidation process. CONSTITUTION:A large number of unit cells 15 are arranged regularly on a plane with a pitch breadth (a) vertically and horizontally. The unit cells 15 are formed on the main surface of a wafer 21, and a LOCOS oxide film is formed to form U grooves 50 on this main surface. Using this oxide film as a mask, a p-type base layer 16 and an n<+>-type source layer 4 are formed by self-aligning double diffusion, and by them channels 5 are set in the lateral wall parts 51 of the U grooves 50. This diffusion mask and a LOCOS oxide film used for forming the U grooves 50 are removed after the double diffusion, and gate oxide films 8 about 60nm thick are formed on the internal walls of the U grooves 50. Besides, on them gate electrodes 9 made out of polysilicon and interlayer insulating films 18 made up of BPSG are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used as a power semiconductor element, that is, a vertical MOSFET (M
(etal Oxide Semiconductor Field Effect Transistor)
And IGBT (Insulated Gate Bipolar Transistor)
It is suitable to adopt the manufacturing method (1) as a single unit or a MOSIC or the like incorporating a power semiconductor element.

[0002]

2. Description of the Related Art Vertical power MOSFETs have been used in many industrial fields in recent years because they have many characteristics such as excellent frequency characteristics, fast switching speed, and low power consumption. For example, the May 19, 1986 issue of Nikkei Electronics Inc. "Nikkei Electronics", pp.165-188, states that the focus of development of power MOSFETs has shifted to low-voltage and high-voltage products. There is. Further, this document describes that the on-resistance of a power MOSFET chip having a withstand voltage of 100 V or less is reduced to the level of 10 mΩ, which is because microfabrication of LSI is used for manufacturing the power MOSFET. It is stated that the channel width per unit area can be increased by devising the shape of the cell. Further, in this document, a vertical type power MOSFET using a DMOS type (double diffusion type) cell which is the mainstream is mainly mentioned. The reason is that the DMOS type is manufactured by a planar process which is characterized in that the flat main surface of a silicon wafer is used as it is for the channel portion, and therefore has a manufacturing advantage that the yield is high and the cost is low. .

On the other hand, with the spread of vertical power MOSFETs, there is a demand for further reduction in loss and cost.
Reducing the on-resistance by microfabrication and devising the cell shape has reached its limit. For example, according to Japanese Patent Laid-Open No. 63-266882, the DMOS type has a minimum point at which the on-resistance does not decrease further even if the size of the unit cell is reduced by microfabrication, and the main cause is the on-resistance component. It has been found to be an increase in JFET resistance. Further, in the DMOS type, as shown in Japanese Patent Application Laid-Open No. 2-86136, under the current microfabrication technology, the size of the unit cell where the on-resistance has a minimum point is around 15 μm.

Various structures have been proposed to overcome this limitation. A feature common to them is a structure in which a groove is formed on the device surface and a channel portion is formed on the side surface of the groove. This structure can greatly reduce the JFET resistance. Further, in the structure in which the channel portion is formed on the side surface of the groove, the increase in JFET resistance can be ignored even if the unit cell size is reduced, and therefore, as described in JP-A-63-266882. There is no limit that the on-resistance takes a minimum point with respect to the reduction of the unit cell size, and it can be reduced to 15 μm or less to the limit of fine processing.

As a conventional manufacturing method of the structure in which the channel portion is formed on the side surface of the groove as described above, for example, International Publication WO93 / 0.
There are manufacturing methods disclosed in JP-A-3502 and JP-A-62-12167. In addition, as a study of its characteristics, ISPSD'93 pp.13
Some are shown in 5-140. FIG. 27 is a sectional view of the MOSFET disclosed in WO93 / 03502, and FIGS.
8 is a sectional view showing a manufacturing process of the MOSFET in the publication.

The manufacturing process will be briefly described below. First, as shown in FIG. 27, a wafer 21 having an n ⁻ type epitaxial layer 2 grown on the main surface of a semiconductor substrate 1 made of n ⁺ type silicon is prepared. The semiconductor substrate 1 has an impurity concentration of about 10 ²⁰ cm ^-3 . The epitaxial layer 2 has a thickness of about 7 μm and an impurity concentration of about 10 ¹⁶ cm ⁻³ . The main surface of the wafer 21 is thermally oxidized to form a field oxide film 60 having a thickness of about 60 nm, a resist film 61 is then deposited, and a pattern is formed in a known photolithography process to open in the center of a cell formation planned position. The resist film 61 is patterned. Then, boron (B ⁺ ) is ion-implanted using the resist film 61 as a mask.

After stripping the resist, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 finally becomes a part of the p-type base layer 16 described later, and when a high voltage is applied between the drain and the source, the p-type diffusion layer 62 stably breaks down at the bottom. Raising it fulfills the purpose of improving surge resistance.

Next, as shown in FIG. 28, a silicon nitride film 63 is deposited on the main surface of the wafer 21 to a thickness of about 200 nm, and the silicon nitride film 63 is patterned to have a pitch width (dimension of the unit cell 15) a. A grid-like opening pattern for opening is formed. The opening pattern is masked so that the p-type diffusion layer 62 described above is located at the center of the pitch interval.

Next, as shown in FIG. 29, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and the n ^-- type epitaxial layer 2 is continuously etched to a depth of 1.
The groove 64 is formed by etching about 5 μm. Next, as shown in FIG. 30, the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask. This is LOCOS (Local O
xidation of Silicon), which is a well-known oxidation method. A selective oxide film, that is, a LOCOS oxide film 65 is formed by this oxidation, and at the same time, a U groove is formed on the surface of the n ⁻ type epitaxial layer 2 which is eaten by the LOCOS oxide film 65. 5
0 is formed and the shape of the groove 50 is determined.

Then, as shown in FIG. 31, boron ions for forming the p-type base layer 16 are ion-implanted through the thin field oxide film 60 using the LOCOS oxide film 65 as a mask. At this time, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position,
The region to be ion-implanted is precisely defined. Next, FIG.
As shown in FIG. 2, heat is diffused to a junction depth of about 3 μm.
By this thermal diffusion, the p-type diffusion layer 62 formed in advance in the step shown in FIG. 28 and the boron diffusion layer implanted in the step shown in FIG. 31 are integrated to form one p-type base layer 16. Further, both end faces of the region of the p-type base layer 16 are defined by the positions of the side walls of the U groove 50 in a self-aligned manner.

Next, as shown in FIG. 33, patterning is performed with a pattern left in the central portion of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a grid pattern. Using both the resist film 66 and the LOCOS oxide film 65 as a mask, phosphorus is ion-implanted through the thin field oxide film 60 to form the n ⁺ -type source layer 4. Also in this case, as in the case where boron is ion-implanted in the step shown in FIG. 31, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 is in a self-aligned position, and the ion-implanted region is accurately defined.

Next, as shown in FIG.
Heat diffusion is performed for 5 to 1 μm to form the n ⁺ type source layer 4, and at the same time, the channel 5 is set. In this thermal diffusion, the end surface in contact with the U groove 50 in the region of the n ⁺ type source layer 4 has a U groove 50.
Is defined in a self-aligned manner at the position of the side wall. Above, FIG.
~ The junction depth of the p-type base layer 16 and its shape are determined by the process of FIG.

Then, as shown in FIG. 35, the LOCOS oxide film 65 is removed by wet etching to remove the U groove 50.
The inner wall 51 of the is exposed, and then thermal oxidation is performed to a thickness of 60 n.
A gate oxide film 8 of about m is formed. Next, as shown in FIG. 36, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of wafer 21.

Then, as shown in FIG. 37, boron is ion-implanted through the oxide film 67 using the patterned resist film 68 as a mask to form the p ⁺ -type base contact layer 17. Next, as shown in FIG. 38, a junction depth of about 0.5 μm is thermally diffused to form ap ⁺ type base contact layer 17.

Then, as shown in FIG.
BPSG (BoronPhosphate Silicate) on the main surface of Ha 21
Interlayer insulating film 18 made of glass) is formed on a part of it
Make contact holes p⁺Mold base contact layer 17
And n⁺The mold source layer 4 is exposed. In addition,
The source electrode 19 made of a film is formed, and the contact
P through the hole⁺Type base contact layer 17 and n + type saw
And ohmic contact with the layer 4. In addition,
Silicon nitride for plasma film protection by plasma CVD
Forming a passivation film (not shown) of
In addition, a Ti / Ni / Au three-layer film is formed on the back surface of the wafer 21.
A drain electrode 20 composed of ⁺Type semiconductor substrate
Make ohmic contact with 1.

As described above, the planar type DMOSFE
The gate oxidation process used when manufacturing T is
In order to easily control the film thickness, as shown in FIG. 39, the wafer 21 is placed in an oxidation furnace 601 in a nitrogen atmosphere, and
As shown in 0, the temperature of the wafer surface was stabilized at a predetermined temperature, and then the atmosphere was changed to an oxygen atmosphere to perform thermal oxidation.

[0017]

The vertical MOSFET manufactured by the manufacturing method described in the above-mentioned prior art is expected to have a low on-voltage in principle as shown in the literature of ISPSD'93 pp.135-140. Was done. However, the above-mentioned International Publication WO
In the manufacturing method of the structure described in 93/03502,
When the oxidation process in the planar type DMOSFET is used, after the p-type base layer and the n ⁺ -type source layer are ion-implanted, the oxide film on the surface is removed and the gate is exposed with the Si surface exposed. In order to perform oxidation, the wafer is placed in an oxidation furnace in a nitrogen atmosphere, and impurities introduced in advance are released from the wafer surface during the time when the temperature of the wafer surface is stabilized at a predetermined temperature. There was a problem that the impurity concentration of was decreased. As a result, the resistance between the n ⁺ -type source layer and the source electrode and the diffusion resistance of the n ⁺ -type source layer increase, the on-voltage increases, and the threshold voltage also exceeds the desired value. It has fallen.

The present invention has been made in view of the above problems, and an object thereof is a method of manufacturing a semiconductor device having a thermal oxidation step, in which impurities introduced in advance are not released from the wafer surface during thermal oxidation. A method of manufacturing a semiconductor device is obtained.

[0019]

In order to achieve the above object, the invention according to claim 1 removes the oxide film of the semiconductor substrate having an oxide film formed on the surface and doped with impurities. In a method of manufacturing a semiconductor device that later includes a thermal oxidation step of thermally oxidizing the semiconductor surface, the thermal oxidation step includes a first thermal oxidation step and a second thermal oxidation step, and the first thermal oxidation step is performed. The oxidizing step includes a step of forming a thin first oxide film on the surface of the semiconductor substrate at a first temperature in an oxidizing atmosphere, and the second thermal oxidizing step at a second temperature in an oxidizing atmosphere. The method is characterized by including a step of forming a second oxide film formed by growing the first oxide film to a predetermined thickness.

According to the invention of claim 2 which is configured to achieve the above object, a semiconductor layer of the first conductivity type having a lower impurity concentration than that of the semiconductor substrate is provided on one main surface side of the semiconductor substrate. A selective oxide film having a predetermined depth from the main surface is formed in the semiconductor layer in the predetermined region by selectively oxidizing the predetermined region with the surface of the low-concentration semiconductor layer as the main surface. Oxidation step and diffusing impurities of the second conductivity type and the first conductivity type from the main surface to form a channel on the surface of the semiconductor layer in contact with the side surface of the selective oxide film, and by this diffusion, the length of the channel is increased. At the same time that a second conductive type base layer and a first conductive type source layer are formed, and the semiconductor layer is used as a first conductive type drain layer; Groove with a certain depth A step of removing a selective oxide film, a first thermal oxidation step of forming a thin first oxide film on an inner wall of the groove including a portion to be the channel at a first temperature in an oxidizing atmosphere, No. 1 oxide film is grown in an oxidizing atmosphere at a second temperature to a predetermined thickness to form a second oxide film.
A second thermal oxidation step of forming the oxide film of 1), a gate electrode forming step of forming a gate electrode on the second oxide film,
A source / drain electrode forming step of forming a source electrode electrically contacting both the source layer and the base layer and a drain electrode electrically contacting the other main surface side of the semiconductor substrate. I am trying.

Further, in the invention according to claim 1 or claim 2, the first temperature in the first thermal oxidation step is
It is preferable that the temperature is lower than the second temperature in the second thermal oxidation step. Further, in the invention according to claim 1 or 2, the first thermal oxidation step includes a step of forming a thin first oxide film on a surface of the semiconductor substrate at a first temperature in the oxidizing atmosphere. Then, the second thermal oxidation step includes a step of replacing the oxidizing atmosphere with an inert atmosphere at the first temperature and a step of changing the first temperature to the second temperature.
A temperature raising step of raising the temperature of the first oxide film to the above temperature, a step of replacing the inert atmosphere with an oxidizing atmosphere at the second temperature, and a predetermined temperature on the first oxide film at the second temperature in the oxidizing atmosphere. And a step of forming a second oxide film having a thickness.

According to a fifth aspect of the present invention, which is configured to achieve the above object, an oxide film is formed on the surface, and after removing the oxide film of the semiconductor substrate on which impurities are doped,
In the method of manufacturing a semiconductor device having a thermal oxidation step of thermally oxidizing the semiconductor surface, the thermal oxidation step forms the thermal oxide film on the semiconductor substrate by gradually inserting the substrate into a high temperature oxidizing atmosphere. It is characterized in that it is a process of performing.

According to a sixth aspect of the present invention, which is configured to achieve the above object, a semiconductor layer of a first conductivity type having a lower impurity concentration than that of the semiconductor substrate is formed on one main surface side of the semiconductor substrate. A selective oxidation step of forming a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region by selectively oxidizing the predetermined region with the surface of the low-concentration semiconductor layer as the main surface And a second conductivity type impurity and a first conductivity type impurity are diffused from the main surface to form a channel on the surface of the semiconductor layer in contact with the side surface of the selective oxide film, and the length of the channel is defined by this diffusion. At the same time, a step of forming a second conductive type base layer and a first conductive type source layer and introducing the semiconductor layer into the first conductive type drain layer, and removing the selective oxide film to reach the predetermined depth. A groove with a groove A step of removing a selective oxide film, a step of forming a gate oxide film by oxidizing an inner wall of the groove including a portion to be the channel, and a gate forming a gate electrode on the gate oxide film. An electrode forming step, a source and drain electrode forming step of forming a source electrode electrically contacting both the source layer and the base layer, and a drain electrode electrically contacting the other main surface side of the semiconductor substrate. In the method of manufacturing a semiconductor device including the above, the thermal oxidation step is a step of gradually inserting the substrate into a high temperature oxidizing atmosphere to form the thermal oxide film on the semiconductor substrate.

In order to achieve the above-mentioned object, the invention according to claim 7 is characterized in that an oxide film is formed on the surface, and after removing the oxide film of the semiconductor substrate on which impurities are doped,
In the method of manufacturing a semiconductor device having a thermal oxidation step of thermally oxidizing the semiconductor surface, the thermal oxidation step is a step of raising the temperature after putting the substrate in an oxidizing furnace in an oxidizing atmosphere. I am trying.

According to the invention of claim 8 which is configured to achieve the above object, a semiconductor layer of the first conductivity type having a lower impurity concentration than that of the semiconductor substrate is provided on one main surface side of the semiconductor substrate. A selective oxide film having a predetermined depth from the main surface is formed in the semiconductor layer in the predetermined region by selectively oxidizing the predetermined region with the surface of the low-concentration semiconductor layer as the main surface. Oxidation step and diffusing impurities of the second conductivity type and the first conductivity type from the main surface to form a channel on the surface of the semiconductor layer in contact with the side surface of the selective oxide film, and by this diffusion, the length of the channel is increased. At the same time that a second conductive type base layer and a first conductive type source layer are formed, and the semiconductor layer is used as a first conductive type drain layer; Groove with a certain depth A gate oxide film forming step, - a selective oxide film removing step of forming a concrete, gate to form the inner wall gate oxide film by oxidizing said groove including a portion to be the channel
A gate electrode forming step of forming a gate electrode on the gate oxide film, a source electrode electrically contacting both the source layer and the base layer, and a drain electrically contacting the other main surface side of the semiconductor substrate. In the method of manufacturing a semiconductor device, the method includes a step of forming source and drain electrodes to form electrodes, and the gate oxide film in the step of forming a gate oxide film is formed in an oxidizing furnace in an oxidizing atmosphere. It is characterized by being formed by putting the semiconductor substrate therein and then raising the temperature of the oxidation furnace.

Here, in the invention according to any one of claims 2 to 4, claim 6, and claim 8, the impurity step includes a channel on a surface of the semiconductor layer in contact with a side surface of the selective oxide film. In order to form the selective oxide film, the impurities of the second conductivity type and the first conductivity type are sequentially double-diffused from the main surface in a self-aligning manner with the selective oxide film, and the length of the channel is defined by the double diffusion. A second conductive type base layer and a first
It is preferable to have a step of forming a conductive type source layer, and to use the semiconductor layer as a first conductive type drain layer.

[0027]

According to the first aspect of the present invention configured as described above, the thermal oxidation step is constituted by the first and second thermal oxidation steps. A thin first oxide film is formed by the oxide film formed in the first thermal oxidation step, and an oxide film is formed to a predetermined thickness by the second thermal oxidation step. In this case, the first oxide film suppresses the impurities from scattering from the wafer surface to the outside, so that the concentration of impurities on the wafer surface can be prevented from lowering. Further, since the oxide film formed in the first thermal oxidation step is sufficiently thinner than the oxide film formed in the second thermal oxidation step, a predetermined oxide film can be formed by controlling only the second thermal oxidation step. The thickness of can be controlled accurately.

According to the second aspect of the present invention configured as described above, the steps of forming the gate oxide film include the first and second steps.
The two thermal oxidation steps of The oxide film formed by the first thermal oxidation step prevents impurities from scattering from the wafer surface to the outside. Further, the oxide films formed by the first and second thermal oxidation steps are combined to form a gate oxide film. By doing so, it is possible to prevent the concentration of impurities on the wafer surface from lowering due to the presence of the first oxide film. As a result, a low on-voltage can be realized and a decrease in threshold voltage can be prevented.

According to the third aspect of the present invention configured as described above, the gate oxidation step is composed of the first and second thermal oxidation steps, and the first thermal oxidation step is the second thermal oxidation step. The temperature is lower than that of the thermal oxidation step. Since the scattering of impurities to the outside of the wafer is suppressed at lower temperatures, it is possible to prevent a decrease in the concentration of impurities on the wafer surface in the first thermal oxidation step. Second
In the thermal oxidation step, although the temperature is high, the oxide film formed in the first thermal oxidation step suppresses scattering of impurities to the outside of the wafer, so that the concentration of impurities on the wafer surface does not decrease. As a result, a low on-voltage can be realized, and the threshold voltage can be prevented from lowering. Further, in the second thermal oxidation step, since the oxide film is formed at a high temperature, the oxidation speed is high and the predetermined film thickness can be formed in a short time.

According to the fourth aspect of the invention configured as described above, the gate oxidation step is constituted by the first and second thermal oxidation steps. Then, in the first thermal oxidation step, the temperature of the oxidizing furnace is set to a low temperature, and in the second thermal oxidation step, the temperature is raised to a predetermined temperature and then the oxidation is performed. Since the scattering of impurities to the outside of the wafer is suppressed at lower temperatures, it is possible to prevent the concentration of impurities on the wafer surface from lowering in the first thermal oxidation step. In the second thermal oxidation step, although the temperature is high, the oxide film formed in the first thermal oxidation step suppresses scattering of impurities to the outside of the wafer, so that the concentration of impurities on the wafer surface does not decrease. As a result, a low on-voltage can be realized, and the threshold voltage can be prevented from lowering. Further, since the oxide film is formed at a high temperature in the second thermal oxidation step, the oxidation speed is high and the predetermined film thickness can be formed in a short time. The second thermal oxidation starts after the temperature is raised to a predetermined temperature and the atmosphere is changed to an oxidizing atmosphere.
The oxide film thickness formed by the second thermal oxidation step can be accurately controlled by the oxidation time.

According to the fifth aspect of the present invention configured as described above, in the gate oxidation step, the wafer is gradually inserted into an oxidation furnace kept in an oxidizing atmosphere and kept at a high temperature. By. During or immediately after the loading, an oxide film is formed to prevent the scattering of impurities while the wafer is at a low temperature.
Also, as the wafer temperature rises, the oxidation rate increases,
The oxide film is grown to a desired thickness. This way,
The concentration of impurities on the wafer surface does not decrease.

According to the sixth aspect of the present invention configured as described above, in the gate oxidation step, the wafer is gradually inserted into an oxidation furnace kept in an oxidizing atmosphere and kept at a high temperature. By. During or immediately after the loading, an oxide film is formed to prevent the scattering of impurities while the wafer is at a low temperature.
Also, as the wafer temperature rises, the oxidation rate increases,
The oxide film is grown to a desired thickness. This way,
The concentration of impurities on the wafer surface does not decrease. As a result, a low on-voltage is realized, and further reduction of the threshold voltage is prevented. Furthermore, it is not necessary to raise or lower the oxidation temperature, and the time required for the process can be shortened. Further, the oxide film thickness can be easily controlled by controlling the oxidation time.

According to the invention of claim 7 configured as described above, in the gate oxidation step, the wafer is inserted into an oxidation furnace kept in an oxidizing atmosphere and kept at a low temperature, and the temperature is raised. To rise. Since the scattering of impurities to the outside of the wafer is suppressed at lower temperatures, the concentration of impurities on the wafer surface does not decrease in the oxidation process at low temperatures. When the temperature rises, the oxide film formed at a low temperature suppresses the scattering of impurities to the outside of the wafer and prevents the concentration of impurities on the wafer surface from decreasing.

According to the eighth aspect of the present invention configured as described above, in the gate oxidation step, the wafer is inserted into an oxidation furnace kept in an oxidizing atmosphere and kept at a low temperature, and the temperature is adjusted. To rise. Since the scattering of impurities to the outside of the wafer is suppressed at lower temperatures, the concentration of impurities on the wafer surface does not decrease in the oxidation process at low temperatures. When the temperature rises, the oxide film formed at a low temperature suppresses the scattering of impurities to the outside of the wafer and prevents the concentration of impurities on the wafer surface from decreasing. As a result, a low on-voltage can be realized, and the threshold voltage can be prevented from lowering. Further, when the temperature is high, the formation rate of the oxide film is high, and a predetermined film thickness can be formed in a short time.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a plan view of a vertical power MOSFET including a square unit cell according to the first embodiment of the present invention, and FIG. 1B is a sectional view taken along line AA in FIG. 3 to 5, FIG. 7 to FIG. 13, FIG. 15, FIG.
18, FIG. 19, FIG. 21, and FIG. 22 are also vertical power M
It is sectional drawing of the wafer which is a workpiece | work in each step in manufacture of OSFET, and is equivalent to FIG.1 (b). 4 is a cross-sectional view of a wafer in which boron ions are implanted to form the central portion of the p-type base layer, and FIG. 5 is a cross-section of a wafer in which a silicon nitride film is patterned at unit cell size a intervals for LOCOS oxidation. FIG. 7, FIG. 7 is a cross-sectional view of a wafer in which a window of a silicon nitride film is etched, FIG. 8 is a cross-sectional view of a wafer in which a LOCOS oxide film is formed, and FIG. 9 is for forming a p-type base layer using the LOCOS oxide film as a mask. FIG. 10 is a sectional view of a wafer on which a p-type base layer is formed by thermal diffusion, and FIG. 11 is a LO sectional view.
A cross-sectional view of a wafer into which phosphorus ions are implanted to form an n ⁺ -type source layer using the COS oxide film as a mask, FIG. 12 is a cross-sectional view of a wafer on which an n ⁺ -type source layer is formed by thermal diffusion, and FIG. 18 is a LOCOS oxide film. A cross-sectional view of a wafer having a gate oxide film formed by thermal oxidation after removal, FIG. 19 is a cross-sectional view of a wafer having a gate electrode formed on the gate oxide film,
FIG. 21 is a cross-sectional view of a wafer in which boron ions are implanted to form a p ⁺ -type base contact layer, FIG. 22 is a cross-sectional view of a wafer in which a p ⁺ -type base contact layer is formed by thermal diffusion, and FIG. 1 (b). FIG. 3 is a completed sectional view of a wafer on which an interlayer insulating film, a source electrode and a drain electrode are formed.

The vertical power MOSFET of this embodiment is
A main part thereof, that is, a unit cell portion has a structure as shown in FIG. 1, and a large number of unit cells 15 are regularly arranged in a vertical and horizontal plane in a pitch width (unit cell size) a. Next, the manufacturing method of this embodiment will be described. In FIG. 1, the wafer 21 has an impurity concentration of 10 ²⁰ c.
An n ⁻ type epitaxial layer 2 having a thickness of about 7 μm and an impurity density of about 10 ¹⁶ cm ⁻³ is formed on a semiconductor substrate 1 made of n ⁺ type silicon having a thickness of about m ⁻³ and a thickness of 100 to 300 μm. The unit cell 15 is formed on the main surface of the wafer 21. In order to form the U groove 50 on the main surface of the wafer 21 with a unit cell size a of about 12 μm,
A LOCOS oxide film having a thickness of about 3 μm is formed, and the p-type base layer 16 having a junction depth of about 3 μm and a junction depth of 1 μm are formed by self-aligned double diffusion using the oxide film as a mask.
The n ⁺ type source layer 4 is formed to some extent, and thereby the channel 5 is set on the side wall portion 51 of the U groove 50. The junction depth of the p-type base layer 16 is set to a depth that does not cause breakdown due to breakdown at the edge portion 12 at the bottom of the U groove 50. Further, boron is diffused in the central portion of the p-type base layer 16 in advance so that the junction depth of the central portion of the p-type base layer 16 is deeper than the surroundings, and a high voltage is applied between the drain and the source. It is set so that breakdown occurs at the central portion of the bottom surface of the p-type base layer 16 when it is opened. Further, after the double diffusion, the diffusion mask and the LOCOS oxide film used for forming the U groove 50 are removed, and the gate oxide film 8 having a thickness of about 60 nm is formed on the inner wall of the U groove 50. 40 on top
A gate electrode 9 made of polysilicon having a thickness of about 0 nm and an interlayer insulating film 18 made of BPSG having a thickness of about 1 μm are formed. Further, a p ⁺ -type base contact layer 17 having a junction depth of about 0.5 μm is formed on the surface of the central portion of the p-type base layer 16, and a source electrode 19 and an n ⁺ -type source formed on the interlayer insulating film 18 are formed. The layer 4 and the p ⁺ type base contact layer 17 are in ohmic contact through the contact hole. Further, the drain electrode 20 is formed so as to make ohmic contact with the back surface of the semiconductor substrate 1.

First, as shown in FIGS. 2 and 3, n ⁺
A wafer 21 is prepared in which an n ⁻ type epitaxial layer 2 is grown on the main surface of a semiconductor substrate 1 made of type silicon and having a plane orientation of (100). The semiconductor substrate 1 has an impurity concentration of about 10 ²⁰ cm ^-3 . The epitaxial layer 2 has a thickness of about 7 μm and an impurity concentration of about 10 ¹⁶ cm ⁻³ . Next, as shown in FIG. 4, the main surface of the wafer 21 is thermally oxidized to a thickness of 6
A field oxide film 60 having a thickness of about 0 nm is formed, a resist film 61 is then deposited, and the resist film 61 is patterned by a known photolithography process into a pattern having an opening at the center of a cell formation planned position. Then, this resist film 61
Boron (B ⁺ ) is ion-implanted using the as a mask.

After the resist is peeled off, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 finally becomes a part of the p-type base layer 16 described later, and when a high voltage is applied between the drain and the source, the p-type diffusion layer 62 stably breaks down at the bottom. Raising it fulfills the purpose of improving surge resistance.

Next, as shown in FIG. 5, a silicon nitride film 63 is deposited to a thickness of about 200 nm on the main surface of the wafer 21, and the silicon nitride film 63 is vertically and parallel to the <011> direction as shown in FIG. The patterning is performed so as to form a lattice-shaped opening pattern having openings with a pitch width (size of the unit cell 15) a. The opening pattern is masked so that the p-type diffusion layer 62 described above is located at the center of the pitch interval.

Next, as shown in FIG. 7, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and the n ⁻ type epitaxial layer 2 is continuously subjected to isotropic chemical dry etching in CF ₄ and oxygen gas. Then groove 6
4 is formed. Next, as shown in FIG. 8, the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask. This is a well-known oxidation method as a LOCOS (Local Oxidation of Silicon) method.
The oxide film 65 is formed, and at the same time, the U groove 50 is formed on the surface of the n ⁻ type epitaxial layer 2 which is eaten by the LOCOS oxide film 65, and the shape of the groove 50 is determined.

At this time, the condition of chemical dry etching and L so that the side surface of the groove is a surface close to the plane orientation (111).
Select the conditions for OCOS oxidation. In this way LOCOS
The inner wall surface of the U groove 50 formed by oxidation is flat and has few defects, and the surface has a surface state as good as the initial main surface of the wafer 21 shown in FIG.

Then, as shown in FIG. 9, boron is ion-implanted to form the p-type base layer 16 through the thin field oxide film 60 using the LOCOS oxide film 65 as a mask. At this time, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 is in a self-aligned position, and the ion-implanted region is accurately defined. Next, FIG.
As shown in (3), heat is diffused to a junction depth of about 3 μm. By this thermal diffusion, the p-type diffusion layer 62 formed in advance in the step shown in FIG. 5 and the boron diffusion layer implanted in the step shown in FIG. 9 are integrated to form one p-type base layer 16. Further, both end faces of the region of the p-type base layer 16 are defined by the positions of the side walls of the U groove 50 in a self-aligned manner.

Next, as shown in FIG. 11, patterning is performed with a pattern left in the center of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a grid pattern. Using the resist film 66 and the LOCOS oxide film 65 as masks, phosphorus is ion-implanted through the thin field oxide film 60 to form the n ⁺ -type source layer 4. Also in this case, as in the case of implanting boron ions in the step shown in FIG.
The boundary portion between the OCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position, and the region where ions are implanted is accurately defined.

Next, as shown in FIG.
Heat diffusion is performed for 5 to 1 μm to form the n ⁺ type source layer 4, and at the same time, the channel 5 is set. In this thermal diffusion, the end surface in contact with the U groove 50 in the region of the n ⁺ type source layer 4 has a U groove 50.
Is defined in a self-aligned manner at the position of the side wall. Above, FIG. 9-
The junction depth of the p-type base layer 16 and its shape are determined by the process of FIG. What is important in the shape of the p-type base layer 16 is that the position of the side surface of the p-type base layer 16 is the U groove 5.
Since it is defined by the side surface of 0, is self-aligned and thermally diffuses, the shape of the p-type base layer 16 is completely symmetrical with respect to the U groove 50.

Next, as shown in FIG. 13, the LOCOS oxide film 65 is terminated with hydrogen in the aqueous solution 700 containing hydrofluoric acid while the pH is adjusted to about 5 by ammonium fluoride. While removing it, the inner wall 51 of the U groove 50 is exposed. This removing step is performed under the condition that the surface on which the selective oxide film is formed is not exposed to light. Next, FIG.
As shown in FIG. 5, an oxide film is formed until the (111) plane is formed on the side surface 5 of the U groove of the p-type base layer 16 where the channel is to be formed. By this thermal oxidation step, the flatness on the atomic order of the surface on which the channel is to be formed is increased. In this thermal oxidation step, as shown in FIG. 14, the oxidation furnace 60 is kept in an oxygen atmosphere and is kept at about 1000 ° C.
The wafer 21 is gradually inserted into 1. This way,
Since the initial stage of oxidation is performed at a relatively low temperature, impurities in the p-type base region 16 and the n ⁺ -type source region 4 can be suppressed from scattering outside the wafer during the thermal oxidation process. next,
As shown in FIG. 16, this oxide film is removed. Similar to the removal of the selective oxide film, the removal of this oxide film is also performed in an aqueous solution containing hydrofluoric acid while terminating the surface of silicon with hydrogen in a state where the pH is adjusted to about 5 by ammonium fluoride. Inner wall 51 of U groove 50 formed by such a method
Is a good silicon surface with high flatness and few defects.

Subsequently, as shown in FIG. 18, a gate oxide film 8 having a thickness of about 60 nm is formed on the side surface and the bottom surface of the U groove 50 by thermal oxidation. This thermal oxidation process is performed in the same manner as described above by keeping the oxygen atmosphere as shown in FIG.
The wafer 21 is gradually inserted into the oxidation furnace 601 maintained at 00 ° C. By doing so, since the initial stage of oxidation is performed at a relatively low temperature, it is possible to prevent impurities in the p-type base region 16 and the n ⁺ -type source region 4 from scattering outside the wafer during the thermal oxidation process. FIG. 23 shows the impurity concentration distribution of the n ⁺ type source layer in the depth direction from the portion where the Al electrode and the n ⁺ source layer contact in the vertical MOSFET of FIG. 1 thus formed. It is the result of the investigation. When the process of the present invention is used, no decrease in the impurity concentration on the surface portion is observed. As a result, a low on-voltage was realized.
Since the inner wall 51 of the U groove 50 formed by such a method is a good silicon surface having high flatness and few defects, the film quality and thickness of the gate oxide film 8 formed by thermal oxidation of this surface and Uniformity, interface state density at the interface of the channel 5, and carrier mobility are as good as those of the conventional DMOS.

Next, as shown in FIG. 19, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of the wafer 21, and the distance is 2β from the distance b between the upper ends of two adjacent U-grooves 50.
The gate electrode 9 is formed by patterning so as to be separated by a short distance c. Next, the end portion of the gate electrode 9 is oxidized so that the gate oxide film 8 becomes thick. Figure 2 at this time
Taking into account the mask alignment accuracy and the portion x where the gate oxide film is thick as shown in 0, β is set so that β> x.

As described above, the steps shown in FIGS. 9 to 19 are the most important manufacturing steps in this embodiment.
Using the oxide film 65 as a self-aligned double diffusion mask to form the p-type base layer 16, the n ⁺ -type source layer 4 and the channel 5, and then removing the LOCOS oxide film 65,
A gate oxide film 8 and a gate electrode 9 are formed. Next, FIG.
As shown in FIG. 1, boron is ion-implanted through the oxide film 67 using the patterned resist film 68 as a mask to form the p ⁺ -type base contact layer 17.

Next, as shown in FIG.
The p ⁺ -type base contact layer 17 is formed by thermal diffusion of about 5 μm. Then, as shown in FIG.
An interlayer insulating film 18 made of BPSG is formed on the main surface of No. 1, and a contact hole is formed in a part of it to expose the p ⁺ type base contact layer 17 and the n ⁺ type source layer 4. Further, a source electrode 19 made of an aluminum film is formed,
P ⁺ type base contact layer 1 through the contact hole
7 and ohmic contact with the n ⁺ type source layer 4. Further, a passivation film (not shown) made of silicon nitride or the like is formed by a plasma CVD method or the like for protecting the aluminum film, and Ti / Ni is formed on the back surface of the wafer 21.
Forming a drain electrode 20 composed of a three-layer film of / Au,
^An ohmic contact is made with the ⁺ type semiconductor substrate 1.

The effects of the first embodiment of the present invention will be described below. The gate oxidation process was kept in an oxygen atmosphere for about 1000
This is done by gradually inserting the wafer into an oxidation furnace maintained at ℃. An oxide film (first oxide film) is formed during or immediately after the loading while the wafer is at a low temperature. The oxide film functions to prevent the scattering of impurities. As the wafer temperature increases, the oxidation rate increases. By doing so, the oxide film can be formed without lowering the concentration of impurities on the wafer surface. As a result, a low on-voltage is realized, and the threshold voltage is not lowered. Furthermore, it is not necessary to raise or lower the temperature of the oxidation furnace, and the time required for the oxidation process can be shortened. The oxide film thickness is
It can be easily controlled by controlling the oxidation time.

In the first embodiment, the gate oxidation step uses an oxidizing furnace in an oxygen atmosphere, but the same effect can be obtained by replacing the oxygen atmosphere with an oxidizing atmosphere. . (Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 24 is a diagram for explaining the second embodiment. The same parts as those in the first embodiment are omitted, and only the parts different from the first embodiment will be described. As shown in FIG.
A gate oxide film 8 having a thickness of about 60 nm is formed on the side surface and the bottom surface of the U groove 50 by thermal oxidation. In this thermal oxidation step, as shown in FIG. 24, the temperature of the oxidation furnace is set to a low temperature, and the first thermal oxidation step of performing thermal oxidation in an oxygen atmosphere in the oxidation furnace is switched to a nitrogen atmosphere, and the temperature is raised to a predetermined temperature. After that, it is composed of a second thermal oxidation step of performing thermal oxidation in an oxidizing furnace with an oxygen atmosphere.

The effects of the second embodiment of the present invention will be described below. The gate oxidation step is performed by changing the temperature of the oxidation furnace to a low temperature and the first thermal oxidation step of performing thermal oxidation in an oxygen atmosphere in the oxidation furnace, and by switching to a nitrogen atmosphere and raising the temperature to a predetermined temperature. This is performed separately from the second thermal oxidation step in which thermal oxidation is performed in an oxygen atmosphere. Since the scattering of impurities introduced into the wafer in advance to the outside of the wafer is suppressed as the temperature becomes lower,
In the first thermal oxidation step, the concentration of impurities on the wafer surface does not decrease. The second thermal oxidation step is hot but the first
Since the oxide film formed in the thermal oxidation step suppresses the scattering of impurities to the outside of the wafer, the concentration of impurities on the wafer surface does not decrease. Therefore, the concentration of impurities on the wafer surface does not decrease. As a result, a low on-voltage is realized, and the threshold voltage is not lowered. Further, since the oxide film is formed at a high temperature in the second thermal oxidation step, the oxidation speed is fast and the predetermined film thickness can be formed in a short time. Further, since the second thermal oxidation is started after raising the temperature to a predetermined temperature and setting it in an oxygen atmosphere, the oxide film thickness formed by the second thermal oxidation step can be accurately controlled by the oxidation time.

In the second embodiment, the gate oxidation step uses an oxidizing furnace in an oxygen atmosphere, but the same effect can be obtained by replacing the oxygen atmosphere with an oxidizing atmosphere. Further, although the nitrogen atmosphere is used as the inert gas in the present embodiment, the present invention is not limited to this, and an argon atmosphere or the like may be used, for example.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. The same parts as those in the first embodiment are omitted, and only the parts different from the first embodiment will be described. FIG. 25 is a diagram for explaining the third embodiment. FIG.
As shown in, the gate oxide film 8 having a thickness of about 60 nm is formed on the side surface and the bottom surface of the U groove 50 by thermal oxidation. This thermal oxidation step is performed by inserting the wafer into an oxidation furnace maintained in an oxygen atmosphere and maintained at about 900 ° C. as shown in FIG. 25, and raising the temperature to about 1000 ° C.

The effects of the third embodiment of the present invention will be described below. Since the scattering of impurities to the outside of the wafer is suppressed at lower temperatures, the concentration of impurities on the wafer surface does not decrease in the thermal oxidation process at about 900 ° C. When the temperature is increased to about 1000 ° C., the oxide film formed at about 900 ° C. suppresses the scattering of impurities to the outside of the wafer, so that the impurities in the p-type base region 16 and the n + type source region 4 are removed during the thermal oxidation process. Suppress scattering to the outside. As a result, a low on-voltage is realized, and the threshold voltage is not lowered. When the temperature is further set to about 1000 ° C., the oxide film is formed at a high temperature, so that the oxidation speed is high and the predetermined film thickness can be formed in a short time.

The low temperature in the claims is about 900.
It means a temperature of ℃ or less, high temperature means a temperature of about 1000 ℃ or more. In the third embodiment, the gate oxidation step uses an oxidizing furnace in an oxygen atmosphere, but the same effect can be obtained by replacing the oxygen atmosphere with an oxidizing atmosphere.

The first, second, and third embodiments described above are vertical MOSs in which the present invention is described in International Publication WO93 / 03502.
Only the case where it is applied to the FET has been described.
Using the S oxide film as a mask, a p-type base layer and an n ⁺ -type source layer are formed.
Vertical M that is self-aligned and ion-implanted into a double layer
The present invention is not limited to the OSFET, and can be applied to a vertical MOSFET in which a p-type base layer and an n ⁺ -type source layer are ion-implanted and diffused using a resist as a mask.

Further, according to the present invention, when the oxide film for preventing the scattering of impurities by the first thermal oxidation step is formed before the ion implantation and the second thermal oxidation step is performed by ion implantation through the oxide film. Can also be applied to. Thus, it is possible to prevent impurities from scattering outside the wafer, and to prevent a decrease in the surface impurity concentration. Further, in the above-mentioned embodiment, the explanation has been made by using the grid pattern, but the present invention is not limited to the grid pattern, and can be applied to the stripe pattern and the same effect can be obtained. Can be obtained.

In the above embodiments, the present invention is applied to the vertical type power.
Only the case where it is applied to the MOSFET has been described,
It is not limited to this, but such vertical power
The present invention may be applied to a power MOSIC incorporating a MOSFET, and may also be applied to a gate structure of an insulating gate type bipolar transistor (IGBT). Further, in the embodiment, only the n-channel type has been described,
It goes without saying that the same effect can be obtained with the p-channel type in which the n-type and p-type semiconductor types are exchanged.

[Brief description of drawings]

FIG. 1A is a plan view showing a part of a vertical power MOSFET according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA of FIG.

FIG. 2 is a vertical power MOSFE according to the first embodiment of the present invention.
It is a figure with which a manufacturing process of T is explained.

FIG. 3 is a vertical power MOSFE according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining the manufacturing process of T.

FIG. 4 is a vertical power MOSFE according to the first embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view which is provided for describing a manufacturing process of T.

FIG. 5 is a vertical power MOSFE according to the first embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view which is provided for describing a manufacturing process of T.

FIG. 6 is a vertical power MOSFE according to the first embodiment of the present invention.
FIG. 6 is a plan view of a principal part for explaining the manufacturing process of T.

FIG. 7 is a vertical power MOSFE according to the first embodiment of the present invention.
It is a figure with which a manufacturing process of T is explained.

FIG. 8 is a vertical power MOSFE according to the first embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view which is provided for describing a manufacturing process of T.

FIG. 9 is a vertical power MOSFE according to the first embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view which is provided for describing a manufacturing process of T.

FIG. 10 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 11 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 12 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 13 is a vertical power MOSF according to the first embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 14 is a vertical power MOSF according to the first embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 15 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 16 is a vertical power MOSF according to the first embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 17 is a vertical power MOSF according to the first embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 18 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 19 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 20 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 21 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 22 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 23 is a result of measuring the impurity concentration from the surface to the depth direction in the first embodiment of the present invention.

FIG. 24 is a vertical power MOSF according to the second embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 25 is a vertical power MOSF according to a third embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

26 (a) is a plan view showing a part of a conventional vertical power MOSFET, and FIG. 26 (b) is a sectional view taken along the line AA of FIG. 26 (a).
FIG.

FIG. 27 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 28 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 29 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 30 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 31 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 32 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 33 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 34 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 35 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 36 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 37 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 38 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 39 is a diagram for explaining a manufacturing process of a conventional vertical power MOSFET.

FIG. 40 is a diagram for explaining the manufacturing process of the conventional vertical power MOSFET.

[Explanation of symbols]

 1 n + type semiconductor substrate 2 n− type epitaxial layer 4 n + type source layer 5 channel 6 n− type drain layer 7 JFET part 8 gate oxide film 9 gate electrode 16 p type base layer 19 source electrode 20 drain electrode 50 U groove 51 U-groove inner wall 65 LOCOS oxide film 601 Oxidation furnace 603 Wafer boat 700 Aqueous solution 702 Discharge tube 703 Reaction chamber 704 Light-shielding cloth

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/316 9274-4M H01L 21/94 A

Claims (9)

[Claims] 1. An oxide film is formed on the surface, and impurities are depleted.
In a method of manufacturing a semiconductor device, which includes a thermal oxidation step of thermally oxidizing the semiconductor surface after removing an oxide film of the semiconductor substrate that has been pinged, the thermal oxidation step includes a first thermal oxidation step and a second thermal oxidation step. The first thermal oxidation step has a step of forming a thin first oxide film on the surface of the semiconductor substrate at a first temperature in an oxidizing atmosphere, and the second thermal oxidation step Is a method for manufacturing a semiconductor device, comprising the step of forming a second oxide film formed by growing the first oxide film to a predetermined thickness in an oxidizing atmosphere at a second temperature. 2. A semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on one main surface side of the semiconductor substrate, and a predetermined region of the semiconductor layer having the low concentration is used as a main surface. A selective oxidation step of forming a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region by selective oxidation; and a channel on the semiconductor layer surface in contact with a side surface of the selective oxide film. A second conductivity type impurity and a first conductivity type impurity are diffused from the main surface to define the length of the channel, and at the same time, the second conductivity type base layer and the first conductivity type source are formed. A step of forming a layer and using the semiconductor layer as a first conductivity type drain layer; a step of removing the selective oxide film to form a groove having the predetermined depth; Including the part that becomes A first thermal oxidation step of forming a thin first oxide film on the inner wall of the groove at a first temperature in an oxidizing atmosphere; and a step of forming the first oxide film at a second temperature in an oxidizing atmosphere at a second temperature. A second thermal oxidation step of forming a second oxide film by growing the oxide film to a thickness of 100 nm, a gate electrode forming step of forming a gate electrode on the second oxide film, and a step of forming a gate electrode on the source layer and the base layer. A method of manufacturing a semiconductor device, comprising: a source / drain electrode forming step of forming a source electrode in electrical contact and a drain electrode in electrical contact with the other main surface side of the semiconductor substrate. 3. The first temperature in the first thermal oxidation step is lower than the second temperature in the second thermal oxidation step, and the first temperature is lower than the second temperature in the second thermal oxidation step. Manufacturing method of semiconductor device. 4. The first thermal oxidation step includes a step of forming a thin first oxide film on a surface of the semiconductor substrate at a first temperature in the oxidizing atmosphere, and the second thermal oxidation step. Is a step of replacing the oxidizing atmosphere with an inert atmosphere at the first temperature, a temperature raising step of raising the temperature from the first temperature to a second temperature, and a step of changing the inert atmosphere at the second temperature. The method further comprises a step of replacing with an oxidizing atmosphere, and a step of forming a second oxide film having a predetermined thickness on the first oxide film at the second temperature in the oxidizing atmosphere. A method of manufacturing a semiconductor device according to claim 1. 5. An oxide film is formed on the surface, and impurities are depleted.
In a method of manufacturing a semiconductor device having a thermal oxidation step of thermally oxidizing the semiconductor surface after removing an oxide film of a semiconductor substrate that has been pinged, the thermal oxidation step includes gradually inserting the substrate into a high-temperature oxidizing atmosphere. And a step of forming the thermal oxide film on the semiconductor substrate. 6. A semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on one main surface side of the semiconductor substrate, and the predetermined region has a surface of the low concentration semiconductor layer as a main surface. A selective oxidation step of forming a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region by selective oxidation, and a channel on the semiconductor layer surface in contact with a side surface of the selective oxide film. A second conductivity type impurity and a first conductivity type impurity are diffused from the main surface to define the length of the channel, and at the same time a second conductivity type base layer and a first conductivity type source are formed. A step of forming a layer and using the semiconductor layer as a first conductivity type drain layer; a step of removing the selective oxide film to form a groove having the predetermined depth; Including the part that becomes A gate oxide film forming step of oxidizing the inner wall of the groove to form a gate oxide film; a gate electrode forming step of forming a gate electrode on the gate oxide film; and a step of electrically forming both the source layer and the base layer. A source electrode in contact with the semiconductor substrate, and a source / drain electrode forming step of forming a drain electrode in electrical contact with the other main surface side of the semiconductor substrate, wherein the thermal oxidation step comprises: A method of manufacturing a semiconductor device, comprising a step of gradually inserting the substrate into a high temperature oxidizing atmosphere to form the thermal oxide film on the semiconductor substrate. 7. An oxide film is formed on the surface, and impurities are depleted.
In a method of manufacturing a semiconductor device having a thermal oxidation step of thermally oxidizing the semiconductor surface after removing an oxide film of a semiconductor substrate that has been pinged, the thermal oxidation step includes placing the substrate in an oxidizing furnace in an oxidizing atmosphere. A method of manufacturing a semiconductor device, comprising the step of increasing the temperature after the step. 8. A semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on one main surface side of the semiconductor substrate, and the predetermined region has a surface of the low concentration semiconductor layer as a main surface. A selective oxidation step of forming a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region by selective oxidation; and a channel on the semiconductor layer surface in contact with a side surface of the selective oxide film. A second conductivity type impurity and a first conductivity type impurity are diffused from the main surface to define the length of the channel, and at the same time, the second conductivity type base layer and the first conductivity type source are formed. A step of forming a layer and using the semiconductor layer as a drain layer of the first conductivity type, an impurity introducing step, a step of removing the selective oxide film to form a groove structure having the predetermined depth, The part that becomes the channel A gate oxide film forming step of forming a gate oxide film by oxidizing the inner wall of the groove including the gate electrode forming step of forming a gate electrode on the gate oxide film, and forming both the source layer and the base layer. A method of manufacturing a semiconductor device, comprising: a source electrode electrically contacting with the source electrode; and a drain electrode forming step of forming a drain electrode electrically contacting the other main surface side of the semiconductor substrate, The gate oxide film in the gate oxide film forming step is formed by placing the semiconductor substrate in an oxidizing furnace in an oxidizing atmosphere and then raising the temperature of the oxidizing furnace. And a method for manufacturing a semiconductor device. 9. The impurity step comprises forming a channel on a surface of the semiconductor layer in contact with a side surface of the selective oxide film,
The impurities of the second conductivity type and the first conductivity type are sequentially double-diffused from the main surface in a self-aligned manner with the selective oxide film, and the length of the channel is defined by the double diffusion, and at the same time, the impurity of the second conductivity type is defined. The method of forming a base layer and a source layer of the first conductivity type, wherein the semiconductor layer serves as a drain layer of the first conductivity type. 9. The method for manufacturing a semiconductor device according to any one of 8.