JP2858411B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for
After removing the oxide film of the semiconductor substrate, the semiconductor substrate is removed.
Method for manufacturing semiconductor device having step of thermally oxidizing plate surface
About.

[0002]

2. Description of the Related Art A vertical power MOSF as a semiconductor device
ET (Metal Oxide Semiconductor Field Effect Trans
istor) has been used in many industrial fields in recent years because it has many features, such as excellent frequency characteristics, high switching speed, and low-power driving. For example, "Nikkei Electronics" published by Nikkei McGraw-Hill
May 19, 1986, pp. 165-188
It is stated that the focus of OSFET development has shifted to low breakdown voltage products and high breakdown voltage products. In addition, this document states that
It is described that the on-resistance of a power MOSFET chip with a withstand voltage of 100 V or less has been reduced to a level of 10 mΩ. This is because the microfabrication of an LSI is used in the manufacture of a power MOSFET or the shape of the cell is changed. It is stated that, by devising, the channel width per area can be increased. Further, this document mainly describes a vertical power MOSFET using a DMOS type (double diffusion type) cell which is a mainstream. The reason is that the DMOS type is manufactured by a planar process characterized in that a flat main surface of a silicon wafer is used as it is for a channel portion, and thus has a manufacturing advantage that the yield is high and the cost is low. .

On the other hand, with the spread of vertical power MOSFETs, lower loss and lower cost have been further required.
The reduction in on-resistance due to fine processing and ingenuity of the cell shape has reached its limit. For example, according to JP-A-63-266882, in the DMOS type, there is a minimum point where the on-resistance does not further decrease even if the size of the unit cell is reduced by fine processing. It has been found that this is an increase in JFET resistance. Further, in the DMOS type, as shown in Japanese Patent Application Laid-Open No. 2-86136, the size of a unit cell where the on-resistance has a minimum point is about 15 μm under the current fine processing technology.

Various structures have been proposed to overcome this limitation. A feature common to them is a structure in which a groove is formed on the element surface and a channel portion is formed on the side surface of the groove, and this structure can greatly reduce the above-described JFET resistance. Further, in the structure in which the channel portion is formed on the side surface of the groove, the increase in the JFET resistance can be ignored even if the unit cell size is reduced, and therefore, as described in JP-A-63-266882. There is no limit that the on-resistance takes a minimum point with respect to the reduction of the unit cell size, and the size can be reduced to 15 μm or less to the limit of fine processing.

As described above, as a conventional manufacturing method of a structure in which a channel portion is formed on the side surface of a groove, for example, International Publication WO93 / 093
There is a manufacturing method disclosed in 3502 and JP-A-62-12167. ISPSD'93 pp.13
Some are shown in 5-140. FIG. 27 is a sectional view of the MOSFET disclosed in WO93 / 03502, and FIGS.
FIG. 8 is a cross-sectional view showing a manufacturing process of the MOSFET in the publication.

Hereinafter, the manufacturing process will be briefly described. First, as shown in FIG. 27, a wafer 21 having an n ⁻ -type epitaxial layer 2 grown on a main surface of a semiconductor substrate 1 made of n ⁺ -type silicon is prepared. This semiconductor substrate 1 has an impurity concentration of about 10 ²⁰ cm ⁻³ . The epitaxial layer 2 has a thickness of about 7 μm and an impurity concentration of about 10 ¹⁶ cm ⁻³ . The main surface of the wafer 21 is thermally oxidized to form a field oxide film 60 having a thickness of about 60 nm, and then a resist film 61 is deposited and formed into a pattern which is opened at the center of a cell formation planned position by a known photolithography process. The resist film 61 is patterned. Then, boron (B ⁺ ) is ion-implanted using the resist film 61 as a mask.

After the resist is removed, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 eventually becomes a part of a p-type base layer 16 described later, and when a high voltage is applied between the drain and the source, a stable breakdown occurs at the bottom of the p-type diffusion layer 62. By raising it, the purpose of improving surge resistance is achieved.

Next, as shown in FIG. 28, a silicon nitride film 63 is deposited on the main surface of the wafer 21 to a thickness of about 200 nm, and the silicon nitride film 63 is patterned to have a pitch a (dimension of the unit cell 15) a. A lattice-shaped opening pattern for opening is formed. This opening pattern is mask-aligned so that the above-described p-type diffusion layer 62 is located at the center of the pitch interval.

Next, as shown in FIG. 29, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and then the n ⁻ -type epitaxial layer 2 has a depth of 1.
The groove 64 is formed by etching about 5 μm. Next, as shown in FIG. 30, the portion of the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask. This is LOCOS (Local O
This is an oxidation method well known as a xidation of silicon method, and a selective oxide film, that is, a LOCOS oxide film 65 is formed by this oxidation, and at the same time, a U-groove is formed on the surface of the n ⁻ -type epitaxial layer 2 covered by the LOCOS oxide film 65. 5
0 is formed, and the shape of the groove 50 is determined.

Next, as shown in FIG. 31, using the LOCOS oxide film 65 as a mask, boron ions for forming the p-type base layer 16 through the thin field oxide film 60 are ion-implanted. At this time, the boundary between the LOCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position,
The region to be implanted is precisely defined. Next, FIG.
As shown in FIG. 2, thermal diffusion is performed to a junction depth of about 3 μm.
Due to this thermal diffusion, the p-type diffusion layer 62 formed in advance in the step shown in FIG. 28 and the boron diffusion layer implanted in the step shown in FIG. 31 are integrated to form one p-type base layer 16. Both end surfaces of the region of the p-type base layer 16 are defined in a self-aligned manner at the positions of the side walls of the U-shaped groove 50.

[0013] Next, as shown in FIG. 33, the p-type base layer 16 is patterned in a pattern left in the center of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a lattice pattern. Using both the resist film 66 and the LOCOS oxide film 65 as a mask, phosphorus ions for forming the n ⁺ -type source layer 4 are ion-implanted through the thin field oxide film 60. In this case as well, as in the case where boron is ion-implanted in the step shown in FIG. 31, the boundary between the LOCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position, and the region to be ion-implanted is accurately defined.

Next, as shown in FIG.
Thermal diffusion is performed by 5 to 1 μm to form an n ⁺ -type source layer 4 and, at the same time, a channel 5 is set. In this thermal diffusion, the end surface of the region of the n ⁺ type source layer 4 which is in contact with the U groove 50 is
Is defined in a self-aligned manner at the position of the side wall. FIG.
34 to determine the junction depth and the shape of the p-type base layer 16.

Next, as shown in FIG. 35, the LOCOS oxide film 65 is removed by wet etching to
The inner wall 51 is exposed and then thermally oxidized to a thickness of 60 n.
A gate oxide film 8 of about m is formed. Next, as shown in FIG. 36, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of the wafer 21.

Next, as shown in FIG. 37, boron for forming the p ⁺ -type base contact layer 17 through the oxide film 67 is ion-implanted using the patterned resist film 68 as a mask. Next, as shown in FIG. 38, thermal diffusion is performed to a junction depth of about 0.5 μm to form ap ⁺ -type base contact layer 17.

[0015] Then, as shown in FIG.
BPSG (Boron Phosphate Silicate)
An interlayer insulating film 18 made of glass is formed, and a part thereof is formed.
Drill a contact hole⁺Mold base contact layer 17
And n⁺The mold source layer 4 is exposed. In addition, aluminum
Forming a source electrode 19 comprising a
P through the hole⁺Base contact layer 17 and n + type saw
Ohmic contact with the semiconductor layer 4. In addition, aluminum
Silicon nitride by plasma CVD etc. to protect the film
Forming a passivation film (not shown) made of
A three-layer film of Ti / Ni / Au is formed on the back surface of the wafer 21.
A drain electrode 20 made of ⁺Type semiconductor substrate
Make ohmic contact with 1.

As described above, the planar type DMOSFE
The gate oxidation process used when manufacturing T is as follows.
In order to easily control the film thickness, the wafer 21 was placed in an oxidation furnace 601 in a nitrogen atmosphere as shown in FIG.
As shown in FIG. 0, the temperature of the wafer surface was stabilized at a predetermined temperature, and then changed to an oxygen atmosphere to perform thermal oxidation.

[0017]

The vertical MOSFET manufactured by the manufacturing method shown in the prior art described above has a low on-state voltage predicted in principle as shown in the document of ISPSD '93, pp. 135-140. Was done. However, the above international publication WO
In the method of manufacturing the structure described in 93/03502,
In the case where the oxidation process in the above-mentioned planar type DMOSFET is used, after the p-type base layer or the n ⁺ -type source layer is ion-implanted, the oxide film on the surface is removed and the gate is exposed in a state where the Si surface is exposed. In order to perform oxidation, the wafer is placed in an oxidation furnace in a nitrogen atmosphere, and impurities introduced in advance are released from the wafer surface to a time during which the temperature of the wafer surface is stabilized at a predetermined temperature. Has a problem that the impurity concentration is lowered. As a result, the resistance between the n ⁺ -type source layer and the source electrode and the diffusion resistance of the n ⁺ -type source layer increase, and the on-voltage increases, and the threshold voltage also becomes higher than a desired value. It has dropped.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device having a thermal oxidation step, in which impurities introduced beforehand are not released from the wafer surface during thermal oxidation. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0019]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate;
The first conductive layer has a lower impurity concentration than the semiconductor substrate on the surface side.
Forming a semiconductor layer of a low-concentration type;
By selectively oxidizing the specified area with
A predetermined distance from the main surface in the semiconductor layer in the predetermined region.
A selective oxidation step of forming an oxide film having a depth, the acid
Forming a channel on the surface of the semiconductor layer in contact with the side surface of the oxide film
In order to remove impurities of the second conductivity type and the first conductivity type,
More spread, this spread defines the length of the channel
At the same time as the second conductive type base layer and the first conductive type saw.
A drain layer of a first conductivity type;
And an oxide film on the surface of the semiconductor substrate.
Oxide film removing process for removing grooves to form grooves having a predetermined depth
And a first oxide film on the surface of the groove in an oxidizing atmosphere.
A first thermal oxidation step of forming
Forming the first oxide film at a higher temperature than the first thermal oxidation step;
Forming a second oxide film grown to a predetermined thickness
A series of steps including the second thermal oxidation step is repeated twice.
A thermal oxidation step having a returning step, and the thermal oxidation step
A gate electrode is formed on the finally formed second oxide film.
Forming a gate electrode, forming the source layer and the
A source electrode in electrical contact with the base layer;
A drain electrode electrically contacting the other main surface of the semiconductor substrate.
Forming a source and drain electrode for forming a pole
A method of manufacturing a semiconductor device.

According to a second aspect of the present invention, a semiconductor layer of a first conductivity type having a lower impurity concentration than that of the semiconductor substrate is provided on one principal surface side of the semiconductor substrate. Forming a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region by selectively oxidizing a predetermined region using the surface of the low-concentration semiconductor layer as a main surface. An oxidation step, in which impurities of the second conductivity type and the first conductivity type are diffused from the main surface to form a channel on the surface of the semiconductor layer in contact with the side surface of the selective oxide film; At the same time, forming a base layer of the second conductivity type and a source layer of the first conductivity type, and introducing an impurity into the semiconductor layer as a drain layer of the first conductivity type; first with a depth A selective oxide film removing step of forming a
An inner wall of the first groove including a portion serving as the channel,
A first thermal oxidation step of forming a first oxide film at a first temperature in an oxidizing atmosphere, and forming the first oxide film at a second temperature higher than the first temperature in an oxidizing atmosphere. Forming a second oxide film by growing to a predetermined thickness;
Thermal oxidation step, and removing the second oxide film to a predetermined depth.
A second oxide film removing step of forming a second groove of said Ji
The inner wall of the second groove including the part to be the channel is oxidized.
Forming a third oxide film at the first temperature in an atmosphere;
A third thermal oxidation step, and forming the third oxide film in an oxidizing atmosphere.
Growing to a predetermined thickness at the second temperature in the air
A fourth heat oxidation step for forming a fourth oxide film Te, the second
4 and the gate electrode forming step of forming a gate electrode on the oxide film, and a source electrode in electrical contact both with the source layer and the base layer, a drain in electrical contact with the other main surface of said semiconductor substrate And forming source and drain electrodes for forming electrodes.

In order to achieve the above object,
The invention according to claim 3 is the invention according to claim 1.
The first thermal oxidation step includes a step of:
Forming the first oxide film on the surface of the semiconductor substrate at a temperature of 1;
And the second thermal oxidation step includes the first thermal oxidation step.
At this temperature, the oxidizing atmosphere is replaced with an inert atmosphere.
Obtaining the first temperature from the first temperature to be higher than the first temperature.
A temperature raising step of raising the temperature to a high second temperature;
Replace the inert atmosphere with an oxidizing atmosphere
And a step in the oxidizing atmosphere at the second temperature.
Forming a second oxide film having a predetermined thickness on the first oxide film;
And a step of

[0022] In order to achieve the above object,
The invention according to claim 4 is the third invention according to claim 2.
The thermal oxidation step is performed at a first temperature in the oxidizing atmosphere.
Forming the third oxide film on the surface of the semiconductor substrate
Has the fourth thermal oxidation process, contact the first temperature
Replacing the oxidizing atmosphere with an inert atmosphere
And a temperature increase for increasing the temperature from the first temperature to the second temperature
Forming the inert atmosphere at the second temperature with an acid.
Replacing with an oxidizing atmosphere;
A predetermined thickness on the third oxide film at the second temperature.
Forming the fourth oxide film.
And

[0023]

[0024]

[0025]

[0026]

[0027]

According to the first aspect of the present invention , a semiconductor device is provided after the impurity introduction step.
The oxide film on the surface of the substrate is removed to form a groove with a predetermined depth.
Oxide film removal process and groove surface in oxidizing atmosphere
A first thermal oxidation step of forming a first oxide film on the substrate;
The temperature of the first thermal oxidation step is higher than that of the first thermal oxidation step in an atmosphere.
Oxide film formed by growing an oxide film to a predetermined thickness
The second thermal oxidation step of forming
A thermal oxidation step having a step of repeating the process twice is performed.
By doing so, the acid formed in the first thermal oxidation step
Of impurities from the wafer surface to the outside due to the oxide film
Can be suppressed. Also, it is finally formed in the thermal oxidation process.
Forming a gate electrode on the second oxide film,
A low on-voltage is realized, and a drop in threshold voltage can be prevented.

According to the second aspect of the present invention, when forming the gate electrode, first, the channel and the
The inner wall of the first groove including the first and second portions
Oxidizing in an oxidizing step to form a second oxide film;
The oxide film is removed to form a second groove, and further, a channel and
The inner wall of the second groove including the portion formed by the third and fourth heat
Oxidation is performed in an oxidation step to form a fourth oxide film.
A gate electrode is formed on the oxide film. As a result,
1. Impurities due to the oxide film formed by the third thermal oxidation process
Objects are prevented from scattering from the wafer surface to the outside. No.
Forming a gate electrode on the oxide film formed by the thermal oxidation process of step 4;
By forming, low ON voltage is realized and the threshold voltage is reduced.
The bottom can also be prevented.

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a plan view of a vertical power MOSFET including a square unit cell according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIGS. 3 to 5, FIGS. 7 to 13, FIGS.
18, 19, 21, and 22 show the vertical power M
It is sectional drawing of the wafer which is a workpiece | work in each stage in manufacture of OSFET, and corresponds to FIG.1 (b). FIG. 4 is a cross-sectional view of a wafer in which boron ions have been implanted to form a central portion of a p-type base layer, and FIG. 5 is a cross-sectional view of a wafer in which a silicon nitride film has been patterned at intervals of a unit cell size a for LOCOS oxidation. FIG. 7, FIG. 7 is a sectional view of a wafer in which a window of a silicon nitride film is etched, FIG. 8 is a sectional view of a wafer on which a LOCOS oxide film is formed, and FIG. 9 is a diagram for forming a p-type base layer using the LOCOS oxide film as a mask. FIG. 10 is a cross-sectional view of a wafer in which boron ions are implanted, FIG. 10 is a cross-sectional view of a wafer in which a p-type base layer is formed by thermal diffusion, and FIG.
FIG. 12 is a cross-sectional view of a wafer in which phosphorus ions are implanted to form an n ⁺ -type source layer using a COS oxide film as a mask, FIG. 12 is a cross-sectional view of a wafer in which an n ⁺ -type source layer is formed by thermal diffusion, and FIG. FIG. 19 is a cross-sectional view of a wafer in which a gate oxide film is formed by thermal oxidation after removal, FIG. 19 is a cross-sectional view of a wafer in which a gate electrode is formed on the gate oxide film,
FIG. 21 is a cross-sectional view of a wafer on which boron ions have been implanted to form a p ⁺ -type base contact layer, FIG. 22 is a cross-sectional view of a wafer on which a p ⁺ -type base contact layer has been formed by thermal diffusion, and FIG. Is a completed sectional view of a wafer on which an interlayer insulating film, a source electrode and a drain electrode are formed.

The vertical power MOSFET of this embodiment is
The main part, that is, the unit cell portion has a structure as shown in FIG. 1, and a large number of the unit cells 15 are arranged regularly and vertically and horizontally on a plane with a pitch width (unit cell size) a. Next, the manufacturing method of this embodiment will be described. In FIG. 1, the wafer 21 has an impurity concentration of 10 ²⁰ c
An n ⁻ -type epitaxial layer 2 having a thickness of about 7 μm and an impurity density of about 10 ¹⁶ cm ⁻³ is formed on a semiconductor substrate 1 made of n ⁺ -type silicon of about m ⁻³ and a thickness of 100 to 300 μm. The unit cell 15 is formed on the main surface of the wafer 21. In order to form a U-groove 50 with a unit cell size a of about 12 μm on the main surface of the wafer 21,
A LOCOS oxide film having a thickness of about 3 μm is formed, and a p-type base layer 16 having a junction depth of about 3 μm and a junction depth of 1 μm are formed by self-aligned double diffusion using the oxide film as a mask.
The n ⁺ type source layer 4 is formed to the extent that the channel 5 is set on the side wall 51 of the U groove 50. The junction depth of the p-type base layer 16 is set to a depth that does not cause breakdown due to breakdown at the edge 12 at the bottom of the U groove 50. In addition, boron is diffused in the central portion of the p-type base layer 16 in advance so that the junction depth of the central portion of the p-type base layer 16 is deeper than the periphery, and a high voltage is applied between the drain and the source. Is set such that a breakdown occurs at the center of the bottom surface of the p-type base layer 16 at the time of the start. After the double diffusion, the diffusion mask and the LOCOS oxide film used for forming the U-groove 50 are removed, and a gate oxide film 8 having a thickness of about 60 nm is formed on the inner wall of the U-groove 50. 40 on top
A gate electrode 9 made of polysilicon having a thickness of about 0 nm and an interlayer insulating film 18 made of BPSG having a thickness of about 1 μm are formed. Further, a p ⁺ -type base contact layer 17 having a junction depth of about 0.5 μm is formed on the central surface of the p-type base layer 16, and a source electrode 19 formed on an interlayer insulating film 18 and an n ⁺ -type source contact The layer 4 and the p ⁺ -type base contact layer 17 are in ohmic contact via the contact holes. Further, a drain electrode 20 is formed so as to make ohmic contact with the back surface of the semiconductor substrate 1.

First, as shown in FIGS. 2 and 3, n ⁺
A wafer 21 is prepared in which an n ⁻ -type epitaxial layer 2 is grown on a main surface of a semiconductor substrate 1 made of type silicon and having a plane orientation of (100). This semiconductor substrate 1 has an impurity concentration of about 10 ²⁰ cm ⁻³ . The epitaxial layer 2 has a thickness of about 7 μm and an impurity concentration of about 10 ¹⁶ cm ⁻³ . Next, as shown in FIG. 4, the main surface of the wafer 21 is thermally oxidized to a thickness of 6 mm.
A field oxide film 60 having a thickness of about 0 nm is formed, and then a resist film 61 is deposited, and the resist film 61 is patterned by a known photolithography process into a pattern opening at a central portion of a cell formation planned position. Then, this resist film 61
Boron (B ⁺⁾ is ion-implanted as a mask.

After the resist is stripped, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 eventually becomes a part of a p-type base layer 16 described later, and when a high voltage is applied between the drain and the source, a stable breakdown occurs at the bottom of the p-type diffusion layer 62. By raising it, the purpose of improving surge resistance is achieved.

Next, as shown in FIG. 5, a silicon nitride film 63 is deposited on the main surface of the wafer 21 to a thickness of about 200 nm, and the silicon nitride film 63 is vertically and parallel to the <011> direction as shown in FIG. Then, a lattice-shaped opening pattern is formed with a pitch width (dimensions of the unit cell 15) a. This opening pattern is mask-aligned so that the above-described p-type diffusion layer 62 is located at the center of the pitch interval.

Next, as shown in FIG. 7, the field oxide film 60 is etched using the silicon nitride film 63 as a mask, and then the n ⁻ -type epitaxial layer 2 is chemically dry-etched in CF ₄ and oxygen gas. And groove 6
4 is formed. Next, as shown in FIG. 8, the portion of the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask. This is an oxidation method well known as a LOCOS (Local Oxidation of Silicon) method.
Oxide film 65 is formed, and at the same time, U-shaped groove 50 is formed on the surface of n ⁻ -type epitaxial layer 2 covered by LOCOS oxide film 65, and the shape of groove 50 is determined.

At this time, the conditions of the chemical dry etching and L are set such that the side surfaces of the grooves are close to the plane orientation (111).
Select the conditions for OCOS oxidation. In this way, LOCOS
The inner wall surface of the U groove 50 formed by the oxidation is flat and has few defects, and the surface state is as good as the initial main surface of the wafer 21 shown in FIG.

Next, as shown in FIG. 9, using the LOCOS oxide film 65 as a mask, boron ions for forming the p-type base layer 16 through the thin field oxide film 60 are ion-implanted. At this time, the boundary between the LOCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position, and the region for ion implantation is accurately defined. Next, FIG.
As shown in FIG. 7, thermal diffusion is performed to a junction depth of about 3 μm. By this thermal diffusion, the p-type diffusion layer 62 formed in advance in the step shown in FIG. 5 and the boron diffusion layer implanted in the step shown in FIG. 9 are integrated to form one p-type base layer 16. Both end surfaces of the region of the p-type base layer 16 are defined in a self-aligned manner at the positions of the side walls of the U-shaped groove 50.

Next, as shown in FIG. 11, patterning is performed in a pattern left in the center of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a lattice pattern. Using both the resist film 66 and the LOCOS oxide film 65 as masks, phosphorus for ion-implanting the n ⁺ -type source layer 4 through the thin field oxide film 60 is implanted. In this case, as in the case where boron ions are implanted in the step shown in FIG.
The boundary between the OCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position, and the region for ion implantation is accurately defined.

Next, as shown in FIG.
Thermal diffusion is performed by 5 to 1 μm to form an n ⁺ -type source layer 4 and, at the same time, a channel 5 is set. In this thermal diffusion, the end surface of the region of the n ⁺ type source layer 4 which is in contact with the U groove 50 is
Is defined in a self-aligned manner at the position of the side wall. FIG.
By the process of FIG. 12, the junction depth and the shape of the p-type base layer 16 are determined. What is important in the shape of the p-type base layer 16 is that the position of the side surface of the p-type base layer 16 is
The shape of the p-type base layer 16 is completely left-right symmetric with respect to the U-shaped groove 50 because it is defined by the 0 side surface and is self-aligned and thermally diffuses.

Next, as shown in FIG. 13, the LOCOS oxide film 65 is terminated with hydrogen in an aqueous solution 700 containing hydrofluoric acid with the pH adjusted to about 5 with ammonium fluoride. While exposing the inner wall 51 of the U groove 50. This removal step is performed under the condition that light does not hit the surface where the selective oxide film is formed. Next, FIG.
As shown in FIG. 5, an oxide film is formed until a (111) plane is formed on the side surface 5 of the U groove of the p-type base layer 16 where a channel is to be formed. By this thermal oxidation step, the flatness in the atomic order of the surface where the channel is to be formed is increased. In this thermal oxidation step, as shown in FIG. 14, an oxidation furnace 60 maintained in an oxygen atmosphere and maintained at about 1000 ° C.
1 is gradually inserted into the wafer 21. This way,
Since the initial stage of the oxidation is performed at a relatively low temperature, the impurities in the p-type base region 16 and the n ⁺ -type source region 4 are prevented from scattering outside the wafer during the thermal oxidation process. next,
As shown in FIG. 16, this oxide film is removed. The removal of the oxide film is also performed in an aqueous solution containing hydrofluoric acid while the pH of the silicon oxide is adjusted to about 5 with ammonium fluoride and the silicon surface is terminated with hydrogen in the same manner as the removal of the selective oxide film. The inner wall 51 of the U-shaped groove 50 formed by such a method
Is a good silicon surface with high flatness and few defects.

Subsequently, as shown in FIG. 18, a gate oxide film 8 having a thickness of about 60 nm is formed on the side and bottom surfaces of the U groove 50 by thermal oxidation. In this thermal oxidation step, as described above, an oxygen atmosphere is maintained as shown in FIG.
The wafer 21 is gradually inserted into the oxidation furnace 601 maintained at 00 ° C. In this case, since the initial stage of the oxidation is performed at a relatively low temperature, the impurities in the p-type base region 16 and the n ⁺ -type source region 4 are prevented from scattering outside the wafer during the thermal oxidation process. FIG. 23 shows the impurity concentration distribution of the n ⁺ -type source layer in the depth direction from the portion where the Al electrode and the n ⁺ -source layer are in contact with each other in the vertical MOSFET of FIG. This is the result of the examination. When the process of the present invention is used, no decrease in the impurity concentration in the surface portion is observed. As a result, a low on-state voltage was realized.
The inner wall 51 of the U-shaped groove 50 formed by such a method is a good silicon surface having high flatness and few defects. Therefore, the quality and thickness of the gate oxide film 8 formed by thermally oxidizing this surface are improved. The uniformity, the interface state density at the interface of the channel 5, and the carrier mobility are as good as those of the conventional DMOS.

Next, as shown in FIG. 19, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of the wafer 21 and the distance between the upper ends of two adjacent U-grooves 50 is larger than the distance b by 2β.
The gate electrode 9 is formed by patterning so as to be separated by a short distance c. Next, oxidation is performed so that the gate oxide film 8 becomes thicker at the end of the gate electrode 9. At this time, FIG.
In view of the mask alignment accuracy and the portion x where the gate oxide film becomes thicker as shown by 0, β is set so that β> x.

As described above, the steps shown in FIGS. 9 to 19 are the most important manufacturing steps in this embodiment.
Using the oxide film 65 as a mask for self-aligned double diffusion, forming the p-type base layer 16, the n ⁺ -type source layer 4 and the channel 5, and then removing the LOCOS oxide film 65,
A gate oxide film 8 and a gate electrode 9 are formed. Next, FIG.
As shown in FIG. 1, boron is ion-implanted for forming the p ⁺ -type base contact layer 17 through the oxide film 67 using the patterned resist film 68 as a mask.

Next, as shown in FIG.
By thermal diffusion of about 5 μm, ap ⁺ type base contact layer 17 is formed. Then, as shown in FIG.
An interlayer insulating film 18 made of BPSG is formed on the main surface of the substrate 1 and a contact hole is formed in a part of the interlayer insulating film 18 to expose the p ⁺ -type base contact layer 17 and the n ⁺ -type source layer 4. Further, a source electrode 19 made of an aluminum film is formed,
P ⁺ type base contact layer 1 through the contact hole
7 and ohmic contact with the n ⁺ -type source layer 4. Further, a passivation film (not shown) made of silicon nitride or the like is formed by a plasma CVD method or the like for protecting the aluminum film.
/ Au is formed as a three-layered drain electrode 20, and n
^An ohmic contact is made to the ⁺ type semiconductor substrate 1.

The effects of the first embodiment of the present invention will be described below. The gate oxidation process is performed in an oxygen atmosphere at about 1000
This is performed by gradually inserting the wafer into an oxidation furnace maintained at a temperature of ° C. During or immediately after the loading, an oxide film (first oxide film) is formed while the temperature of the wafer is low. This oxide film functions to prevent scattering of impurities. As the temperature of the wafer increases, the oxidation rate increases. By doing so, an oxide film can be formed without lowering the concentration of impurities on the wafer surface. As a result, a low on-state voltage is realized, and no lowering of the threshold voltage is observed. Further, it is not necessary to raise or lower the temperature of the oxidation furnace, and the time required for the oxidation step can be shortened. The oxide film thickness is
It can be easily controlled by controlling the oxidation time.

In the first embodiment, an example is shown in which the gate oxidation step uses an oxidation furnace in an oxygen atmosphere, but the same effect can be obtained by replacing the oxygen atmosphere with an oxidation atmosphere. . (Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 24 is a view for explaining the second embodiment. The same parts as those in the first embodiment are omitted, and only the parts different from the first embodiment will be described. As shown in FIG.
A gate oxide film 8 having a thickness of about 60 nm is formed on the side and bottom surfaces of the U groove 50 by thermal oxidation. As shown in FIG. 24, this thermal oxidation step is a first thermal oxidation step in which the temperature of the oxidation furnace is set to a low temperature and the inside of the oxidation furnace is set to an oxygen atmosphere, and a thermal oxidation is performed. After that, a second thermal oxidation step of performing thermal oxidation in an oxidation furnace with an oxygen atmosphere is included.

The effects of the second embodiment of the present invention will be described below. In the gate oxidation step, the temperature of the oxidation furnace is set to a low temperature, a first thermal oxidation step in which the inside of the oxidation furnace is subjected to thermal oxidation in an oxygen atmosphere, and the atmosphere is switched to a nitrogen atmosphere. After the temperature is raised to a predetermined temperature, the inside of the oxidation furnace is cooled. This is performed separately from a second thermal oxidation step in which thermal oxidation is performed in an oxygen atmosphere. Since the scattering of impurities introduced into the wafer in advance to the outside of the wafer is suppressed at lower temperatures,
In the first thermal oxidation step, the concentration of impurities on the wafer surface does not decrease. The second thermal oxidation step is at a high temperature,
Since the oxide film formed in the thermal oxidation step suppresses scattering of impurities to the outside of the wafer, the impurity concentration on the wafer surface does not decrease. Therefore, the concentration of impurities on the wafer surface does not decrease. As a result, a low on-state voltage is realized, and the threshold voltage does not decrease. Further, since the oxide film is formed at a high temperature in the second thermal oxidation step, the oxidation rate is high and a predetermined film thickness can be formed in a short time. In addition, since the second thermal oxidation is started after the temperature is raised to a predetermined temperature and then in an oxygen atmosphere, the oxide film thickness formed in the second thermal oxidation step can be accurately controlled by the oxidation time.

In the second embodiment, an example is shown in which the gate oxidation step uses an oxidation furnace in an oxygen atmosphere, but the same effect can be obtained by replacing the oxygen atmosphere with an oxidation atmosphere. Further, in this embodiment, the description has been made using the nitrogen atmosphere as the inert gas. However, the present invention is not limited to this. For example, an argon atmosphere may be used.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. The same parts as those in the first embodiment are omitted, and only the parts different from the first embodiment will be described. FIG. 25 is a diagram for explaining the third embodiment. FIG.
As shown in FIG. 7, a gate oxide film 8 having a thickness of about 60 nm is formed on the side and bottom surfaces of the U groove 50 by thermal oxidation. This thermal oxidation step is performed by inserting the wafer into an oxidation furnace maintained at about 900 ° C. in an oxygen atmosphere as shown in FIG. 25, and raising the temperature to about 1000 ° C.

The effects of the third embodiment of the present invention will be described below. Since the scattering of impurities to the outside of the wafer is suppressed as the temperature becomes lower, the concentration of impurities on the wafer surface does not decrease in the thermal oxidation process at about 900 ° C. When the temperature is increased to about 1000 ° C., an oxide film formed at about 900 ° C. suppresses the scattering of impurities to the outside of the wafer. Therefore, impurities in the p-type base region 16 and the n + -type source region 4 are removed during the thermal oxidation process. Suppress the scattering to the outside. As a result, a low on-state voltage is realized, and the threshold voltage does not decrease. Further, when the temperature is set to about 1000 ° C., the oxide film is formed at a high temperature, so that the oxidation rate is high and a predetermined film thickness can be formed in a short time.

Here, the low temperature in the claims is about 900
The temperature refers to a temperature equal to or lower than 0 ° C, and the high temperature refers to a temperature equal to or higher than about 1000 ° C. In the third embodiment, an example is shown in which an oxidation furnace is used for the gate oxidation step in an oxygen atmosphere. However, the same effect can be obtained by replacing the oxygen atmosphere with an oxidation atmosphere.

In the first, second and third embodiments, the present invention is applied to a vertical MOS transistor described in WO 93/03502.
Although only the case where the present invention is applied to the FET has been described, the LOCO
Using the S oxide film as a mask, a p-type base layer and an n ⁺ -type
Vertical M with double diffusion by self-aligned ion implantation
The present invention is not limited to the OSFET, and can be applied to, for example, a vertical MOSFET in which a p-type base layer and an n ⁺ -type source layer are ion-implanted and diffused using a resist as a mask.

Further, according to the present invention, the formation of an oxide film for preventing scattering of impurities in the first thermal oxidation step is performed before the ion implantation, and the ion implantation is performed through this oxide film to perform the second thermal oxidation step. Also applicable to As a result, it is possible to prevent the impurities from scattering to the outside of the wafer, and to prevent a decrease in the impurity concentration on the surface. In the above embodiment, the description has been made using the lattice pattern. However, the present invention is not limited to the lattice pattern, and the present invention can be applied to a stripe pattern. Can be obtained.

In the above embodiment, the present invention is applied to a vertical power
Although only the case of application to MOSFET has been described,
It is not limited to this, such a vertical power
It may be applied to a power MOSIC incorporating a MOSFET, and furthermore, an insulated gate bipolar transistor (IGBT) (Insulated Gate Bipolar Transistor)
Can be applied to the above gate structure. Although only the n-channel type has been described in the embodiment, it goes without saying that the same effect can be obtained with a p-channel type in which the types of the n-type and p-type semiconductors are interchanged.

[Brief description of the drawings]

FIG. 1A is a plan view showing a part of a vertical power MOSFET according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line AA of FIG.

FIG. 2 is a vertical power MOSFET according to a first embodiment of the present invention;
FIG. 9 is a diagram provided for explanation of a manufacturing process of T.

FIG. 3 is a vertical power MOSFET according to a first embodiment of the present invention;
It is sectional drawing used for description of the manufacturing process of T.

FIG. 4 is a vertical power MOSFET according to a first embodiment of the present invention;
It is a principal part sectional view with which description of the manufacturing process of T is provided.

FIG. 5 is a vertical power MOSFET according to a first embodiment of the present invention;
It is a principal part sectional view with which description of the manufacturing process of T is provided.

FIG. 6 is a vertical power MOSFET according to the first embodiment of the present invention;
It is a principal part top view with which description of the manufacturing process of T is provided.

FIG. 7 is a vertical power MOSFET according to the first embodiment of the present invention;
FIG. 9 is a diagram provided for explanation of a manufacturing process of T.

FIG. 8 is a vertical power MOSFET according to the first embodiment of the present invention;
It is a principal part sectional view with which description of the manufacturing process of T is provided.

FIG. 9 is a vertical power MOSFET according to the first embodiment of the present invention;
It is a principal part sectional view with which description of the manufacturing process of T is provided.

FIG. 10 is a vertical power MOSF according to a first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 11 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 12 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 13 is a vertical power MOSF according to the first embodiment of the present invention;
FIG. 3 is a diagram provided for explanation of a manufacturing process of ET.

FIG. 14 is a vertical power MOSF according to the first embodiment of the present invention;
FIG. 3 is a diagram provided for explanation of a manufacturing process of ET.

FIG. 15 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 16 is a vertical power MOSF according to the first embodiment of the present invention;
FIG. 3 is a diagram provided for explanation of a manufacturing process of ET.

FIG. 17 is a vertical power MOSF according to the first embodiment of the present invention;
FIG. 3 is a diagram provided for explanation of a manufacturing process of ET.

FIG. 18 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 19 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 20 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 21 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 22 is a vertical power MOSF according to the first embodiment of the present invention;
It is principal part sectional drawing used for description of the manufacturing process of ET.

FIG. 23 shows the result of measuring the impurity concentration in the depth direction from the surface in the first example of the present invention.

FIG. 24 is a vertical power MOSF according to a second embodiment of the present invention;
FIG. 3 is a diagram provided for explanation of a manufacturing process of ET.

FIG. 25 is a vertical power MOSF according to a third embodiment of the present invention;
FIG. 3 is a diagram provided for explanation of a manufacturing process of ET.

FIG. 26 (a) is a plan view showing a part of a conventional vertical power MOSFET, and FIG. 26 (b) is a sectional view taken along line AA of FIG.
It is sectional drawing.

FIG. 27 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 28 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 29 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 30 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 31 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 32 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 33 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 34 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 35 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 36 is a main-portion cross-sectional view for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 37 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 38 is a fragmentary cross-sectional view for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 39 is a view for explaining a manufacturing process of a conventional vertical power MOSFET.

FIG. 40 is a view for explaining a manufacturing process of a conventional vertical power MOSFET.

[Explanation of symbols]

 Reference Signs List 1 n + type semiconductor substrate 2 n− type epitaxial layer 4 n + type source layer 5 channel 6 n− type drain layer 7 JFET section 8 gate oxide film 9 gate electrode 16 p-type base layer 19 source electrode 20 drain electrode 50 U groove 51 Inner wall of U groove 65 LOCOS oxide film 601 Oxidation furnace 603 Wafer boat 700 Aqueous solution 702 Discharge tube 703 Reaction chamber 704 Shading cloth

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 21/316

Claims (4)

(57) [Claims] 1. A semiconductor substrate, comprising : a semiconductor substrate;
Forming a first conductivity type semiconductor layer having a lower impurity concentration
The surface of this low-concentration semiconductor layer is used as the main surface.
By selectively oxidizing the constant region, the half of the predetermined region is
An oxide film having a predetermined depth from the main surface is formed in the conductor layer.
Forming a selective oxidation step, and forming a channel on the surface of the semiconductor layer in contact with a side surface of the oxide film.
Is formed by adding impurities of the second conductivity type and the first conductivity type to the
Diffuses from the main surface, which causes the length of the channel
And a base layer of the second conductivity type and the first conductivity type
A source layer of the first conductivity type;
An impurity introducing step for forming an in-layer, and removing an oxide film on the surface of the semiconductor substrate to have a predetermined depth.
Oxide film removing step to form a groove,
A first thermal oxidation process for forming a first oxide film on the surface of the groove
And the first thermal oxidation step in an oxidizing atmosphere.
Growing the first oxide film at a high temperature to a predetermined thickness.
Said second thermal oxidation step of forming a second oxide film comprising:
Oxidation having a process of repeating a series of processes twice
And the second oxidation finally formed in the thermal oxidation step
A gate electrode forming step of forming a gate electrode on the film; and electrically contacting the source layer and the base layer together.
Source electrode to be electrically connected to the other main surface of the semiconductor substrate.
Source and drain forming a drain electrode in contact with
An electrode forming step.
Production method. 2. A semiconductor layer of a first conductivity type having a lower impurity concentration than that of the semiconductor substrate is formed on one main surface side of the semiconductor substrate, and the surface of the low-concentration semiconductor layer is used as a main surface in a predetermined region. A selective oxidation step of forming a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region by selectively oxidizing the semiconductor layer; and forming a channel on the semiconductor layer surface in contact with a side surface of the selective oxide film. Is formed, impurities of the second conductivity type and the first conductivity type are diffused from the main surface, and the length of the channel is defined by the diffusion, and at the same time, the base layer of the second conductivity type and the source of the first conductivity type are diffused. An impurity introduction step of forming a layer and using the semiconductor layer as a first conductivity type drain layer; a selective oxide film removing step of removing the selective oxide film to form a first trench having a predetermined depth; Including the channel part The inner wall of the first groove,
A first thermal oxidation step of forming a first oxide film at a first temperature in an oxidizing atmosphere ;
A second thermal oxidation step of forming a second oxide film by growing to a predetermined thickness at a second temperature higher than the temperature, and a second groove having a predetermined depth by removing the second oxide film Form
A second oxide film removing step, and an inner wall of the second groove including a portion to be the channel,
Forming a third oxide film at the first temperature in an oxidizing atmosphere;
Forming a third thermal oxidation step, and forming the third oxide film in the oxidizing atmosphere.
Forming a fourth oxide film by growing to a predetermined thickness at a temperature;
A fourth thermal oxidation step, a gate electrode forming step of forming a gate electrode on the fourth oxide film, a source electrode electrically contacting both the source layer and the base layer, A method for manufacturing a semiconductor device, comprising: forming a source electrode and a drain electrode for forming a drain electrode that is in electrical contact with the other main surface. 3. The method according to claim 1, wherein the first thermal oxidation step comprises:
At a first temperature in the air, the surface of the semiconductor substrate
Forming a first oxide film, wherein the second thermal oxidation step includes the step of forming the oxide film at the first temperature.
Replacing the oxidizing atmosphere with an inert atmosphere;
From the first temperature to a second temperature higher than the first temperature
A temperature raising step of raising the temperature, and the inactivation at the second temperature.
Replacing the oxidizing atmosphere with an oxidizing atmosphere;
In the atmosphere, on the first oxide film at the second temperature
Forming a second oxide film having a predetermined thickness.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein: 4. The method according to claim 1, wherein the third thermal oxidation step is performed in the oxidizing atmosphere.
At a first temperature in the air, the surface of the semiconductor substrate
Forming a third oxide film, wherein the fourth thermal oxidation step includes the step of forming the oxide film at the first temperature.
Replacing the oxidizing atmosphere with an inert atmosphere;
A temperature raising step of raising the temperature from the first temperature to the second temperature;
The inert atmosphere is changed to an oxidizing atmosphere at the second temperature.
Exchanging, and the second step in the oxidizing atmosphere.
A predetermined thickness of the fourth oxide film on the third oxide film at a temperature of
Forming an oxide film.
Item 3. A method for manufacturing a semiconductor device according to Item 2 .