JP2015179869A - Mos semiconductor device and mos semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS semiconductor device which does not cause a decrease in breakdown voltage and an increase in on-resistance, and which achieves low manufacturing cost.SOLUTION: A MOS semiconductor device comprises: p base regions 17 which are selectively arranged in a surface layer of an ndrift layer 1 and each of which has a net doping concentration with a shape having a double well region; n first regions 6 which are selectively arranged in a surface layer of each p base region 17; gate electrodes 8 each coated via a gate insulation film 9, on a surface of the p base region 17, which is sandwiched by a surface of the n first region 6 and a surface of the ndrift layer 1; pcontact regions 22 each having a bottom face which is included in the p base region 17 and parallel with a surface of the pcontact regions 22; and a metal electrode 13 conductively contacting the surfaces of the n first regions 6 and the surfaces of the p base regions 17.

Description

The present invention relates to a MOS type semiconductor device such as a MOSFET and an IGBT (Insulated Gate Bipolar Transistor) and a method for manufacturing the MOS type semiconductor device .

Power MOSFETs and IGBTs, which are MOS type semiconductor elements, are known as elements capable of voltage control. FIG. 9 is a cross-sectional view of a main part of a conventional MOSFET. A p base region 17 is formed in the surface layer of the n ⁻ drift layer 1 adjacent to the n ⁺ drain layer 2 serving as the substrate, and the n ⁺ source region 6 and the p ⁺ contact region 22 are formed in the surface layer of the p base region 17. Are selectively formed. The surface layer of the p base region 17 sandwiched between the surface of the n ⁻ drift layer 1 and the surface of the n ⁺ source region 6 becomes the channel forming region 7. A gate electrode 8 is provided on the surface of the channel formation region 7 via a gate insulating film 9. An interlayer insulating film 10 is formed on the gate electrode 8 to maintain insulation from the source electrode 13 covering the interlayer insulating film 10. The source electrode 13 is formed so as to be in common contact with the surface of the p ⁺ contact region 22 and the surface of the n ⁺ source region 6. A drain electrode 12 is formed on the surface of the n ⁺ drain layer 2 on the opposite side.

The joint surface 20 where the p base region 17 and the n ⁻ drift layer 1 are in contact with each other includes a finite radius portion of curvature and a flat base portion. However, as shown in FIG. 13, the base portion of the joint surface 20 is not flat, and a curvature shape in which the depth from the surface to the joint surface 20 is the deepest in the central portion of the p base region 17 can also be formed (patent) Reference 1). If the ion implantation region width when forming the p base region 17 is larger than the range distance of impurity ions, the base becomes flat, and if the width is smaller than the range distance, the base is not flat. Further, as shown in FIGS. 9 and 13, in order to improve the contact property with the source electrode 13 and to reduce the influence of a parasitic bipolar transistor described later, the n ⁺ source region 6 is formed on the surface of the p base region 17. In many cases, a p ⁺ contact region 22 reaching just below is provided.

The conventional MOSFET wafer process shown in FIG. 9 will be described below. n ⁺ drain layer 2 to become the high concentration n-type silicon substrate by epitaxial growth is a high-resistance layer the n ^- using the semiconductor substrate formed with the drift layer 1, n ^- to form the gate insulating film 9 on the drift layer 1 Thereafter, a polycrystalline silicon layer for forming the gate electrode 8 is deposited. A pattern for the gate electrode 8 made of polycrystalline silicon is formed on the polycrystalline silicon layer by photolithography, and boron ions are implanted and heat-treated for the p base region 17 using the gate electrode 8 as a mask through the opening formed at that time. Perform diffusion. Using the oxide film or photoresist (not shown) selectively left in the center of the opening and the pattern of the gate electrode 8 as a mask, a donor such as arsenic (As) is ion-implanted to form the n ⁺ source region 6. Form. After removing the oxide film mask at the center of the opening, a p ⁺ contact region 22 is formed. The entire surface including the gate electrode 8 except for the surface of the n ⁺ source region 6 and the surface of the p ⁺ contact region 22 is covered with an interlayer insulating film 10, and then the source electrode 13 and the n ⁺ source region 6 and A portion connecting p ⁺ contact region 22 is opened. Then, a source electrode 13 that is in common contact with the surface of the n ⁺ source region 6 and the surface of the p ⁺ contact region 22 and is insulated from the gate electrode 8 by the interlayer insulating film 10 is deposited. The main wafer process of the MOSFET is completed by laminating the drain electrode 12 with a plurality of well-known metal films on the surface of the n ⁺ drain layer 2 on the opposite side. The n ⁺ source region 6 and the p ⁺ contact region 22 may be formed in the reverse order.

In this MOSFET, when a positive voltage is applied to the gate electrode 8 with respect to the source electrode 13, a channel is formed in the channel formation region 7 immediately below the gate insulating film 9, and electrons are transferred from the n ⁺ source region 6 to the channel formation region. 7 is injected into n ⁻ drift layer 1 and becomes conductive. Further, the gate electrode 8 functions as a so-called switching element that is in a blocking state by being biased to the same potential as the source electrode 13 or a negative potential with respect to the source electrode 13.

FIG. 10 is a cross-sectional view of a main part of a conventional IGBT. The difference between MOSFET of the above-mentioned FIG. 9, n ⁺ drain layer 2 is p ⁺ collector layer 14 becomes, the p ⁺ collector layer 14 and n ^- that n ⁺ buffer layer 15 is formed between the drift layer 1 It is. When the n ⁻ drift layer 1 and the n ⁺ buffer layer 15 are formed on the p ⁺ collector layer 14 by epitaxial growth, they become semiconductor substrates for forming a MOS structure on the surface thereof. Each region is formed in the surface layer of the n ⁻ drift layer 1 on the semiconductor substrate by the same process as the above-described MOSFET. The operational difference from the MOSFET is that holes are injected from the p ⁺ collector layer 14 and the n ⁻ drift layer 1 undergoes conductivity modulation, resulting in a low resistance.

In the manufacturing process of the MOSFET or IGBT, the n ⁺ source region 6 and the p base region 17 are generally formed by a so-called self-alignment method using the gate electrode 8 as a mask. The p base region 17 is formed by a resist mask. The n ⁺ source region 6 may be formed using polycrystalline silicon as a mask, or the p base region 17 and the n ⁺ source region 6 may be formed using a photoresist mask, respectively (Patent Documents 1 and 3). ).

  As a similar MOSFET, a structure in which an n-well is formed at the center of a p-type channel diffusion layer (the aforementioned p base region 17) in order to prevent element breakdown due to turning on a parasitic bipolar transistor at the time of turn-off in an inductive load circuit Is described (Patent Document 2). There is a description that this structure can prevent the parasitic bipolar transistor from being turned on. Similarly, a structure in which a p-type region (the aforementioned p base region 17) has two concave base portions without forming an n-well is described (Patent Documents 4 and 5).

Japanese Patent Laid-Open No. 9-148666 JP-A-7-235668 JP 2009-277839 A JP-A-6-163909 JP-A-8-204175

However, when the MOSFET or IGBT is used in an inverter device connected to an inductive load, the MOSFET or IGBT is often destroyed when the element is turned off. This destruction occurs by the following mechanism. FIG. 11 is a diagram in which a cross-sectional view of a main part of a MOSFET and an equivalent circuit are overlapped. The MOSFET incorporates a parasitic bipolar transistor 30 including an n ⁺ source region 6, a p base region 17 and an n ⁻ drift layer 1. When the MOSFET is turned off under an inductive load, the channel forming region 7 is in a blocking state, electron injection from the n ⁺ source region 6 into the n ⁻ drift layer 1 is eliminated, and a depletion layer spreads in the n ⁻ drift layer 1. At this time, the voltage applied between the drain and source of the MOSFET may rise above the breakdown voltage of the MOSFET, and an avalanche current flows to consume the energy stored in the inductive load in the MOSFET. That is, as shown in FIG. 12, the curved portion of the p base region 17 becomes an avalanche generating portion 16, and a hole / electron pair is generated. The holes generated in the above portion become an avalanche current 34 as indicated by an arrow in FIG. 12, and flow in the lateral direction in the p base region 17 immediately below the n ⁺ source region. At this time, when the avalanche current increases, a voltage drop caused by the lateral resistance R in the p base region 17 causes a pn junction weir layer voltage (0.7 to 0... 0) between the p base region 17 and the n ⁺ source region 6. 8V). Then, electrons are injected from the n ⁺ source region 6 and the parasitic bipolar transistor 30 is turned on to cause local current concentration, so that the element is destroyed. As a countermeasure, the p ⁺ contact region 22 is arranged in the lateral current path immediately below the n ⁺ source region 6 to reduce the lateral resistance R and reduce the voltage drop below the weir layer voltage. ing. However, when the p ⁺ contact region 22 reaches just below the channel formation region 7, the channel is not formed even if a positive voltage is applied to the gate electrode 8, and the switching function is lost. When designed on the premise, the p ⁺ contact region 22 needs to be separated from the channel forming region 7 to some extent. As a result, the lateral resistance R cannot be sufficiently reduced, and the parasitic bipolar transistor 30 cannot be sufficiently turned on, and the device may be destroyed.

In contrast, MOSFET of FIG. 14, as shown in the cross sectional view of the IGBT of FIG. 15, to form a deeper than p base region 17 second p ⁺ region 21, the second p ⁺ region 21 There is also a method for preventing the turn-on of the parasitic bipolar transistor by concentrating the avalanche current on the base. However, in this structure, another problem arises in that the breakdown voltage decreases because the pn junction surfaces of the p base region 17 and the second p ⁺ region 21 become uneven. Further, when the second p ⁺ region 21 is deeply diffused, the breakdown voltage is lowered even if the thickness of the n ⁻ drift layer 1 between the base portion of the second p ⁺ region 21 and the n ⁺ drain layer 2 is reduced. Problems also arise. On the other hand, the path through which electrons injected into the n ⁻ drift layer 1 from the n ⁺ source region 6 through the channel formation region 7 reach the drain electrode 12 does not change. However, in order to maintain the rated voltage, the on-resistance is increased without increasing the thickness of the n ⁻ drift layer 1 by the amount that the second p ⁺ region 21 is deeper than the p base region 17. In order to maintain the on-resistance value before the increase, the chip size must be increased, and there is an economic problem that the unit price of the chip increases.

  Further, as shown in FIG. 13, the base portion of the p base region 17 is flattened to have a base shape with a finite radius of curvature, the electric field is concentrated at the center portion of the base portion, and the avalanche current is concentrated at the center portion. There is also a method for avoiding the parasitic bipolar transistor from being turned on. In this case, in order to make the base portion have a curvature shape, the width of the opening for ion implantation needs to be narrower than the depth of the p base region 17. However, if the width of the opening is reduced, it is difficult to secure a contact area with the source electrode 13 that is in contact with the opening. In practice, it is difficult to narrow the opening sufficiently and sufficiently, and an avalanche is formed on the base. It is difficult to concentrate the current.

  The present invention has been made in view of the above-described points, and an object of the present invention is to provide a MOS semiconductor device that does not cause a decrease in breakdown voltage and an increase in on-resistance, and is low in manufacturing cost. There is.

In order to achieve the object of the present invention, the present invention provides:
A first conductivity type drift layer;
Two concave portions which are selectively disposed on the surface of the drift layer, and have a pn junction surface with the drift layer, the depths of which are equal and deepest from the surface layer of the drift layer in the depth direction; A second conductivity type base layer comprising at least one double well region sandwiched between two concave portions and having a convex portion whose depth is shallower than the concave portion;
A first conductivity type source layer selectively disposed on a surface layer of the base region;
Embedded in the base layer and selectively disposed on the surface layer of the base layer, having a higher impurity concentration than the base layer, deeper than the source layer, and shallower than the depth of the convex portion of the double well region, A second conductivity type contact layer having a termination located directly under the source layer;
A gate electrode disposed on the surface of the base layer sandwiched between the source layer and the drift layer via a gate insulating film;
An interlayer insulating film covering the gate electrode and having a side edge located on the surface of the source layer;
A source electrode that is in conductive contact with the surface of the source layer and the central surface of the base layer and is insulated from the gate electrode by the interlayer insulating film;
At a predetermined depth deeper than the contact layer in the base layer, the net doping concentration in the upper portion on the surface layer side of the convex portion is lower than the net doping concentration in the upper portion on the surface layer side of the two concave portions. Higher than the net doping concentration under the gate electrode,
On the surface layer side of the deepest concave portion of the double well region, the source electrode, a contact surface in contact with the source electrode and the source layer, and the contact layer in contact with the bottom surface of the source layer are formed. Has been
The bottom surface of the contact layer that is in the upper part of the concave part and is in contact with the source layer at the lower part of the contact surface is a MOS semiconductor device that is parallel to the contact surface.

The present invention also provides a manufacturing method for manufacturing the MOS type semiconductor device,
Selectively forming an oxide film on the surface of the drift layer;
Forming the gate electrode selectively on the surface of the drift layer so as to be separated from the oxide film, and forming an opening exposing the surface of the drift layer between the gate electrode and the oxide film; ,
Second conductivity type impurities are ion-implanted from the opening, and the implanted boron is thermally diffused, so that a second conductivity type well is provided corresponding to each of the two adjacent openings across the oxide film. And forming the base layer constituting the double well region by overlapping the wells;
Forming a source layer on the surface of the base layer by ion-implanting a first conductivity type impurity from the opening after the base layer is formed;
Depositing an interlayer insulating film and selectively etching together with the oxide film to form a contact portion of the source electrode;
A step of ion-implanting a second conductivity type impurity from the contact portion to form the contact layer,
The width of the opening along the direction from the gate electrode toward the oxide film is a MOS semiconductor device manufacturing method that is shorter than the depth of the deepest concave portion of the double well region.

  According to the present invention, it is possible to provide a MOS semiconductor device that does not cause a decrease in breakdown voltage and an increase in on-resistance and that is low in manufacturing cost.

It is principal part sectional drawing which shows the wafer process of MOSFET concerning Example 1 of this invention. It is principal part sectional drawing of MOSFET concerning Example 1 of this invention. It is principal part sectional drawing of MOSFET which shows the wafer process concerning Example 2 of this invention. It is principal part sectional drawing of MOSFET concerning Example 2 of this invention. It is principal part sectional drawing of MOSFET concerning Example 2 of this invention. It is principal part sectional drawing of IGBT concerning Example 3 of this invention. It is a principal part top view of the semiconductor substrate which has a square cell pattern concerning MOSFET of FIG. 1, 2 or FIG. FIG. 4 is a plan view of a principal part of a semiconductor substrate having a striped cell pattern according to the MOSFET of FIG. It is principal part sectional drawing of the conventional MOSFET. It is principal part sectional drawing of the conventional IGBT. It is a superposition figure of the equivalent circuit of the conventional MOSFET, and principal part sectional drawing. It is principal part sectional drawing which shows the path | route through which the avalanche current of the conventional MOSFET flows. It is principal part sectional drawing of the conventional MOSFET. It is principal part sectional drawing of the conventional MOSFET. It is principal part sectional drawing of the conventional IGBT. It is principal part sectional drawing of MOSFET concerning Example 1 of this invention. It is principal part sectional drawing of MOSFET concerning Example 4 of this invention.

  Embodiments of a MOS semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  FIG. 1 and FIG. 2 are cross-sectional views showing the principal parts of a MOSFET wafer process according to Embodiment 1 of the present invention. The same reference numerals are given to the common parts to FIG. 9 referred to in the description of the conventional MOSFET. FIG. 1 is a cross-sectional view of an essential part in a process step of covering the entire surface including the gate electrode 8 with an interlayer insulating film 10 in a MOSFET wafer process.

The case of MOSFET will be described below. Using a semiconductor substrate in which an n ⁻ drift layer 1 which is a high resistance layer is deposited by epitaxial growth on a high concentration n ⁺ silicon substrate to be the n ⁺ drain layer 2, it is formed on the surface layer of the p base region 17 in a later step. An oxide film 31a having a width of the separation distance of the n ⁺ source region is formed. Using the oxide film 31a as a mask, a donor dopant such as phosphorus is shallower than the depth of the p base region 17 and has an impurity concentration that is about one digit lower than the p base region and about two digits higher than the n ⁻ drift layer 1. An n region 32 is formed (FIG. 1A). Note that the lateral diffusion portion of the n region 32 may be connected directly below the oxide film 31a as shown in FIG. A gate insulating film 9 and a polycrystalline silicon layer to be the gate electrode 8 are stacked on the surface of the silicon substrate. The polycrystalline silicon layer is patterned to form the gate electrode 8, and an interval is provided between the gate electrode 8 and the oxide film 31a to form an opening for forming the p base region 17. The width of the opening is narrower than the depth of the p base region 17 in order to form the p base region 17 whose base is not flat.

Since the distance between the openings is narrower than the depth of the p base region 17, the p base region 17 obtains a pn junction surface having a base portion having a curvature peak portion below the opening. Further, since the opening is formed on both sides of the oxide film 31a in the p base region 17, the sectional view shown in FIG. 1 has two curvature peak portions in the p base region 17 (FIG. 1B). . Using this curvature peak as a well region, a p base region 17 having two well regions is formed. Further, as shown in FIG. 16, the p base region 17 is overlapped with the n region 32, particularly at the end of the p base region 17 which is the lower part of the gate electrode 8 in the direction horizontal to the surface of the n ⁻ drift layer 1. And compensation of the donor concentration occurs. Accordingly, in the net doping concentration line 35 immediately below the oxide film 31a where the donor is not diffused, that is, between the two well regions of the p base region 17, the p base region 17 and the n region 32 overlap to cause concentration compensation. The distribution of the curvature of the net doping concentration line 35 is smaller than that of the region in which it is present. Here, the net doping concentration line is a line in which the net concentration obtained by subtracting the acceptor concentration from the donor concentration shows a certain value. In other words, the net doping concentration of the portion between the two well regions in the p base region 17 is the net doping concentration at the end of the p base region 17 which is the lower part of the gate electrode 8 in the direction horizontal to the surface of the n ⁻ drift layer 1. It becomes higher than the concentration.

  It should be noted that the net doping concentration of the p base region 17 sandwiched between the two well regions is equal to that of the two wells regardless of whether the n region 32 is uniformly formed or the n region 32 is not formed. As long as the regions overlap, the net doping concentration at the end of the p base region 17 under the gate electrode 8 becomes higher. In short, when the region where the n region 32 is not diffused is formed using the oxide film 31 a as a mask as described above, the net doping concentration of the p base region 17 sandwiched between the two well regions is p base corresponding to the lower portion of the gate electrode 8. That is, it becomes higher than the net doping concentration at the end of the region 17.

Next, using the gate electrode 8 and the oxide film 31a as a mask again, a donor such as arsenic (As) is ion-implanted to form the n ⁺ source region 6. Subsequently, the entire surface is covered with an interlayer insulating film 10. As shown in the cross-sectional view of FIG. 2, the interlayer insulating film 10 is removed by etching except for the top of the gate electrode 8 by photolithography, and at the same time, the oxide film 31a is also removed to make contact for contact with the source electrode 13. A window 41 is formed.

Boron ions are implanted from the contact window 41 to form the p ⁺ contact region 22. At this time, the surface of the trace where the oxide film 31a shown in FIG. 1 is etched and removed becomes the p ⁺ contact region 22, and the n ⁺ source region 6 has a higher impurity concentration than the p ⁺ contact region 22. N ⁺ source region 6 remains. However, the depth of the p ⁺ contact region 22 is so deep than the n ⁺ source region 6, immediately below the n ⁺ source region 6 p ⁺ contact region 22 is formed. A source electrode 13 that covers the surface of the n ⁺ source region 6 and the surface of the p ⁺ contact region 22 in common and covers the gate electrode 8 via the interlayer insulating film 10 is deposited. Note that the gate electrode 8 is contact-wired to an aluminum gate pad electrode provided at another location (not shown) on the chip surface. When the drain electrode 12 is formed on the surface of the n ⁺ drain layer 2 which is the surface opposite to the surface on the source electrode side, the wafer process for the MOSFET according to the first embodiment of the present invention is completed.

  FIG. 7 is a plan view when the cell pattern of the surface MOS structure of the MOSFET of FIGS. In the wafer process, as a mask for forming the p base region 17, the contact window 41 opened in the polycrystalline silicon layer for forming the gate electrode is formed into a square cell shape so that a cell having a surface MOS structure as shown in FIG. The pattern is a square MOSFET. This square cell pattern can also have other cell shapes such as rectangle, hexagon, triangle and circle. In addition, as shown in FIG. 7, it is preferable that corners of rectangles, hexagons, triangles, and the like have a rounded chamfered curvature, because the electric field intensity is concentrated on the corners when a voltage is applied. .

FIG. 8 is a plan view when the cell pattern of the surface MOS structure of the MOSFET of FIGS. 1 and 2 is a striped cell pattern. In the wafer process, as a mask for forming the p base region 17 in FIG. 2, the shape of the contact window 41 opened in the polycrystalline silicon layer for forming the gate electrode is formed into a stripe shape, whereby p ⁺ as shown in FIG. The contact region 22, the n ⁺ source region 6, the channel formation region 7, the n ⁻ drift layer 1, etc. form a MOS structure cell pattern arranged in parallel in a stripe shape. As described above, the p base region 17 has two concave base portions, but the end portions in the longitudinal direction of the stripe shape are not shown, but are connected at the end like a donut shape, Or you may terminate in a strip shape without connecting. That is, the p base regions 17 may be connected to each other at their end portions to form a single layer, or the individual stripe-shaped or cell-shaped p base regions 17 may be dispersedly arranged. . Note that the p base regions 17 that are a single layer or distributed are basically at the same potential as the source electrode in any case in the off state.

Since the MOSFET according to the present invention has the above-described configuration, as shown in FIG. 2, the avalanche current 34 at the time of breakdown is concentrated on the deepest avalanche generating portion 16 (dotted circle) in the p base region 17. Can do. The p ⁺ contact region 22 is present above the avalanche generating portion 16 and the net doping concentration of the p base region 17 in the portion where the two well regions overlap is the end of the p base region 17 corresponding to the lower portion of the gate electrode 8. Since the decrease in the acceptor concentration is suppressed and the resistance is lowered by the increase in the net doping concentration, the avalanche current 34 is more likely to flow to the center. As a result, the current flowing into the p base region 17 immediately below the n ⁺ source region 6 is suppressed, the parasitic bipolar transistor is prevented from being turned on, and the device is prevented from being destroyed by turn-off with an inductive load. it can.

In the first embodiment, the p base region 17 has two well regions. Of course, the p base region 17 may have two or more well regions. For example, the p base region 17 has three well regions. Then, the avalanche generation region becomes the bottom of the three wells. Of the bottoms of these three wells, the avalanche current generated in the middle well can directly flow into the p ⁺ contact region directly above according to the electrostatic potential. Therefore, almost no avalanche current passes directly under the n ⁺ source region 6. In order to form such two or more wells, a plurality of oxide films 31a as shown in FIG. 1 may be provided.

  3 and 4 are cross-sectional views of the main part of a MOSFET according to Embodiment 2 of the present invention. Portions common to those in FIG. 9 are denoted by the same reference numerals. FIG. 3 is a fragmentary cross-sectional view in a process step of covering the entire surface including the gate electrode 8 with the interlayer insulating film 10 in the MOSFET wafer process.

First, a semiconductor substrate in which an n ⁻ drift layer 1 which is a high resistance layer is formed on an n ⁺ drain layer 2 by epitaxial growth is prepared. Unlike the first embodiment, an oxide film is formed using a LOCOS process so that the Si surface is recessed to form a LOCOS oxide film 31b, and then a donor dopant such as phosphorus is added to the p base region 17 using the LOCOS oxide film 31b as a mask. An n region 32 having an impurity concentration lower than that of the p base region and about one digit lower than that of the p base region and about two digits higher than that of the n ⁻ drift layer 1 is formed. Then, a gate insulating film 9 and a polycrystalline silicon layer to be the gate electrode 8 are sequentially formed on the n ⁻ drift layer 1. The polycrystalline silicon layer is opened as a contact window 41 including the LOCOS oxide film 31b by photolithography to form the gate electrode 8. The LOCOS oxide film 31b is left in the center of the contact window 41. The distance between the LOCOS oxide film 31b and the gate electrode 8 in the contact window 41 is smaller than the distance of the depth of the p base region 17 to be formed next.

Using the formed gate electrode 8 and the LOCOS oxide film 31b as a mask, boron ion implantation for forming the p base region 17 and thermal diffusion are performed. As a result, as shown in FIG. 3, the p base region 17 has a structure including two well regions of an uneven base portion having two concave portions below the opening, and a pn junction surface having the two well regions. Get 20. Further, using the gate electrode 8 and the LOCOS oxide film 31b as a mask again, a donor such as arsenic (As) is ion-implanted to form the n ⁺ source region 6, and then the entire surface is covered with the interlayer insulating film 10 ( So far, FIG. 3). 4, the interlayer insulating film 10 is removed by etching except for the top of the gate electrode 8 by photolithography, and at the same time, the oxide film 31a is also removed to make contact with the source electrode 13. A contact window 41 is formed. The surface of the contact window 41 has an oxide film trace 36 made of a depression formed after the LOCOS oxide film 31b is removed. Boron ions are implanted from the contact window 41 to form the p ⁺ contact region 22. As a result, the base portion of the p ⁺ contact region 22 has a deep concave shape at the center portion 33 of the base portion due to the effect of the depression on the surface, and has a shape having convex curved portions on both sides thereof. A source electrode 13 that is in common contact with the surface of the n ⁺ source region 6 and the surface of the p ⁺ contact region 22 and covers the gate electrode 8 via the interlayer insulating film 10 is formed. Note that the gate electrode 8 is contact-wired to an aluminum gate pad electrode provided at another location (not shown) on the chip surface. When the drain electrode 12 is formed on the surface of the n ⁺ drain layer 2 which is the surface opposite to the surface on the source electrode side, the wafer process for the MOSFET according to the second embodiment of the present invention is completed.

The p base region 17 has a junction surface 20 having two well regions between the n ⁻ drift layer 1 and the n ⁻ drift layer 1. In particular, the bottom of the two well regions has the deepest depth below the midpoint between the oxide film trace 36 from which the LOCOS oxide film 31b has been removed and the end of the gate electrode 8, and the bottom of the well region generates an avalanche. It becomes part 16. As shown in FIG. 4, the p ⁺ contact region 22 has a concave Si portion near the central portion 33 of the base portion of the p ⁺ contact region 22 because the Si surface is recessed due to the oxide film trace 36, as shown in FIG. And it can form in the form which combined the convex part on the both sides. That there is the convex portion, it is possible to form such as projecting a central portion 33 of the base portion of the p ⁺ contact region 22 to be recessed in the depth direction, as shown in FIG. 5, the avalanche current 34 p ⁺ It becomes easy to collect in the contact region 22. Furthermore the p ⁺ contact region 22 by such a concave portion and the convex portion and the combined shape, it is possible to separate the central portion 33 in the depth direction from the n ⁺ source region 6, the depletion layer n ⁺ Reach through to the source region 6 can be effectively suppressed.

As described above, the p base region 17 of the MOSFET according to the second embodiment includes the avalanche generation portion 16 in which the electric field concentration is likely to occur as in the first embodiment. Further, since the base portion of the p ⁺ contact region 22 is not flat and has a deep portion at the central portion 33, most of the current flowing from the avalanche generating portion 16 is generated as shown by the arrow in FIG. ^{+ It} becomes easier to go to the central portion 33 of the contact region 22, and the bipolar transistor operation can be further suppressed as compared with the first embodiment.

Further, a structure in which a p ⁺ collector layer is formed on the surface layer of the n ⁻ drift layer opposite to the surface side described above via an n ⁺ buffer layer, that is, an IGBT can be used. In the case of an IGBT, a parasitic thyristor is built in instead of a parasitic bipolar transistor. Like the parasitic bipolar transistor in the case of a MOSFET, this parasitic thyristor is prevented from being turned on to prevent element destruction. Can do.

Hereinafter, the IGBT according to Example 3 will be described in detail. FIG. 6 is a cross-sectional view of the main part of an IGBT according to Example 3 of the present invention. Portions common to those in FIG. 9 are given the same reference numerals. The collector electrode 12a is different from the MOSFET of FIG. 4 in that the collector electrode 12a is formed on the p ⁺ collector layer 14 via the n ⁺ buffer layer 15 formed on the other surface of the n ⁻ drift layer 1. The name of the n ⁺ source region 6 is changed to the n ⁺ emitter region 6a, and the name of the source electrode 13 is changed to the emitter electrode 13a. As in FIG. 4, the p base region 17 has a shape in which the junction surface 20 with the n ⁻ drift layer 1 has a finite radius of curvature, and the oxide film trace 36 from which the LOCOS oxide film is removed and the end of the gate electrode 8. In the vicinity of the middle point, the depth from the surface to the bonding surface 20 is the deepest, and a concave-convex shape in which the depth from the surface to the bonding surface 20 is the shallowest is formed at the center 33 of the surface of the p ⁺ contact region 22. The

The depth of the p ⁺ contact region 22 surface of the central portion 33 with p ⁺ contact region 22 is deepest. Therefore, the thickness of the n ⁻ drift layer 1 in this portion is the smallest, and the avalanche phenomenon is likely to occur first at the time of reverse bias.

Embodiment 4 of the present invention will be described with reference to FIG. The fourth embodiment has a structure in which the n region 32 is removed from the structure of the first embodiment shown in FIG. Even when the n region 32 is not formed, it is possible to form the p base region 17 having two concave well regions. This is because, even if there is no n region, if boron is ion-implanted from the opening between the oxide film 31a and the gate electrode 8 shown in FIG. This is because the base region 17 can be formed. Therefore, the avalanche generating portion 16 can be shifted to the base portion of the two well regions, and the avalanche current 34 can be passed through the source electrode 13 without passing under the n ⁺ source region 6. Therefore, the above-described problem can be solved even with a configuration without n regions. On the other hand, as already described, it is needless to say that providing the n region is a more preferable means.

According to the MOS semiconductor devices described in the first to third embodiments according to the present invention described above, the p ⁺ contact region 22 is in the p base region 17 and the p base region 17 has a finite radius of curvature. In addition, a recessed avalanche generating portion 16 below the n ⁺ source region 6 or n ⁺ emitter region 6a portion having the deepest depth from the surface of the p base region 17 has two points in cross section. As a result, the parasitic bipolar transistor (or parasitic thyristor) formed by the p base region 17 and the n ⁺ drain layer 2 or the p ⁺ collector layer 14 of the MOS type semiconductor device is prevented from being turned on, and the element breakdown voltage is reduced. The avalanche resistance can be improved without causing a decrease or an increase in on-resistance. In addition, by adopting this structure, the manufacturing cost can be reduced.

1 n ⁻ drift layer 2 n ⁺ drain layer 6 n ⁺ source region 6 a n ⁺ emitter region 7 channel forming region 8 gate electrode 9 gate insulating film 10 interlayer insulating film 12 drain electrode 12a collector electrode 13 source electrode 13a emitter electrode 14 p ⁺ Collector layer 15 n ⁺ Buffer layer 16 Avalanche generating portion 17 p base region 20 junction surface 21 second p ⁺ region 22 p ⁺ contact region 30 parasitic bipolar transistor 31a oxide film 31b LOCOS oxide film 32 n region 33 central portion 34 avalanche current 35 Net doping concentration line 36 Oxide film trace 41 Contact window

Claims (10)

A first conductivity type drift layer;
Two concave portions which are selectively disposed on the surface of the drift layer, and have a pn junction surface with the drift layer, the depths of which are equal and deepest from the surface layer of the drift layer in the depth direction; A second conductivity type base layer comprising at least one double well region sandwiched between two concave portions and having a convex portion whose depth is shallower than the concave portion;
A first conductivity type source layer selectively disposed on a surface layer of the base region;
Embedded in the base layer and selectively disposed on the surface layer of the base layer, having a higher impurity concentration than the base layer, deeper than the source layer, and shallower than the depth of the convex portion of the double well region, A second conductivity type contact layer having a termination located directly under the source layer;
A gate electrode disposed on the surface of the base layer sandwiched between the source layer and the drift layer via a gate insulating film;
An interlayer insulating film covering the gate electrode and having a side edge located on the surface of the source layer;
A source electrode that is in conductive contact with the surface of the source layer and the central surface of the base layer and is insulated from the gate electrode by the interlayer insulating film;
At a predetermined depth deeper than the contact layer in the base layer, the net doping concentration in the upper portion on the surface layer side of the convex portion is lower than the net doping concentration in the upper portion on the surface layer side of the two concave portions. Higher than the net doping concentration under the gate electrode,
On the surface layer side of the deepest concave portion of the double well region, the source electrode, a contact surface in contact with the source electrode and the source layer, and the contact layer in contact with the bottom surface of the source layer are formed. Has been
A MOS type semiconductor device, wherein a bottom surface of the contact layer in contact with the source layer below the contact surface is parallel to the contact surface.   2. The MOS semiconductor device according to claim 1, wherein the surface of the contact layer is located at the same depth as the surface of the source layer. The surface of the contact layer and the bottom surface of the contact layer both have a shape having a depression in the depth direction,
2. The MOS semiconductor device according to claim 1, wherein a surface of the contact layer is deeper than a surface of the source layer.   The MOS type semiconductor device according to claim 3, wherein the recess is located on a surface side of the convex portion. The drift layer surface layer below the gate electrode, and between the adjacent base layers, a first conductivity type low resistance layer having a higher impurity concentration than the drift layer,
The first conductivity type impurity of the low resistance layer extends inside the base layer,
The extended first conductivity type impurity has a lower concentration than the second conductivity type impurity of the base layer,
The concentration of the extended first conductivity type impurity below the source layer is lower than the concentration of the extended first conductivity type impurity in a portion between the two source layers in the base layer. The MOS semiconductor device according to claim 1, wherein the MOS semiconductor device is a semiconductor device.   6. The MOS according to claim 1, wherein the side end of the interlayer insulating film is located closer to the gate electrode than a position where the concave portion is projected onto the surface of the source layer. Type semiconductor device. A manufacturing method for manufacturing the MOS type semiconductor device,
Selectively forming an oxide film on the surface of the drift layer;
Forming the gate electrode selectively on the surface of the drift layer so as to be separated from the oxide film, and forming an opening exposing the surface of the drift layer between the gate electrode and the oxide film; ,
Second conductivity type impurities are ion-implanted from the opening, and the implanted boron is thermally diffused, so that a second conductivity type well is provided corresponding to each of the two adjacent openings across the oxide film. And forming the base layer constituting the double well region by overlapping the wells;
Forming a source layer on the surface of the base layer by ion-implanting a first conductivity type impurity from the opening after the base layer is formed;
Depositing an interlayer insulating film and selectively etching together with the oxide film to form a contact portion of the source electrode;
A step of ion-implanting a second conductivity type impurity from the contact portion to form the contact layer,
The width of the opening along the direction from the gate electrode toward the oxide film is shorter than the depth of the deepest concave portion of the double well region. A manufacturing method of the MOS semiconductor device described.   8. The method of manufacturing a MOS type semiconductor device according to claim 7, wherein the side end of the interlayer insulating film is positioned closer to the gate electrode than the position where the concave portion is projected onto the surface of the source layer. The oxide film is a LOCOS oxide film;
By removing the LOCOS film in the step of forming the contact portion, a recess is formed on the surface sandwiched between two source layers formed on the surface of the base layer,
9. The method of manufacturing a MOS semiconductor device according to claim 7, wherein in the step of forming the contact layer, a second conductivity type impurity is ion-implanted into a surface including the depression.   After the step of forming the oxide film and before the step of forming the opening, the first conductivity type impurity is ion-implanted and diffused using the oxide film as a mask, so that the impurity concentration is higher than that of the drift layer. The method of manufacturing a MOS semiconductor device according to claim 7, wherein the first conductivity type low-resistance layer is formed.