JPH03276638A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the epitaxial film thickness directly under a collector- electrode extraction part thin without increasing the number of processes and to reduce a collector series resistance by a method wherein, when a whole-face base region is formed in a transistor part and polysilicon other than an emitter region is removed, an epitaxial layer in the collector-electrode extraction part is removed simultaneously. CONSTITUTION:Ions at a low energy and at a high dose are implanted into a transistor part to form a base region 6. Then, a resist in an emitter-electrode extraction part 8a and a collector-electrode extraction part 8b is patterned to form the parts; after that, an oxide film 21 directly above the emitter- electrode extraction part 8a and the collector-electrode extraction part 8b is etched to form openings; after that, the resist is removed; polysilicon 7 is deposited on the surface. Then, a patterning operation is executed so as to leave the resist on the polysilicon 7 directly above a part to be used as the emitter region 8a; the polysilicon is removed by an etching operation. At this time, a base region in the part which is not covered with the oxide film and which is to be used as the collector-electrode extraction part is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high-speed bipolar transistor.

<Prior Art> FIGS. 2(a) to 2(a) are schematic cross-sectional views showing a conventional method of manufacturing a bipolar transistor over time.

(a) As shown in the figure, after forming an N-type buried layer 14 and a P-type buried layer 13 on a P-type substrate 10, N-type epitaxial growth is performed on the entire surface to form an N-type epitaxial layer 11. Form. Next, an element isolation region 1 is placed on the P-type buried layer 13.
form 2.

Next, as shown in FIG. 3B, a resist 15 is formed, patterning is performed, and then ion implantation ("B") is performed to form a base region 16.

Next, as shown in the figure (C), the resist 15 is removed and thermal oxidation is performed to form a thermal oxide film 121.

Next, as shown in the figure (d), a resist 15 is formed, and the resist 15 and oxide film 121 are directly above the emitter electrode extension part 17a and the collector electrode extension part 17b.
Openings were made by photoetching, and ion implantation ("As") was performed.
”).

Next, (e) as shown in the figure, non-doped Sin.

is deposited by CVD method, and CVD film 18 is deposited by CVD method.
After forming by a method, annealing is performed.

Finally, as shown in the figure, a metal electrode 19 is formed by a well-known method to form a transistor.

<Problems to be Solved by the Invention> As described above, in the conventional method, the epitaxial film thickness directly below the collector electrode extension part is formed thicker, which increases the collector series resistance and hinders high speed. . An object of the method of the present invention is to solve these problems and provide a method for manufacturing a semiconductor device in which the collector series resistance is reduced without increasing the number of steps.

<Means for Solving the Problems> A method for manufacturing a semiconductor device of the present invention includes forming a buried diffusion layer of a second conductivity type, a buried diffusion layer of a first conductivity type, and a buried diffusion layer of a second conductivity type on a substrate of a first conductivity type. an epitaxial layer, a base region of a first conductivity type on the surface of the epitaxial layer, an emitter region of a second conductivity type in the base region of the first conductivity type, and an emitter region of a second conductivity type on the surface of the epitaxial layer. In a method for forming a collector region of a second conductivity type formed on a buried diffusion layer of a second conductivity type by diffusion of impurities, after forming an epitaxial layer of a second conductivity type, an element isolation film is formed; After forming the base region by ion implantation, an oxide film is formed by thermal oxidation, then openings are made on the substrate that will become the emitter region and collector region, polysilicon is grown on the entire surface, and then the emitter region is covered. After forming a resist pattern, the polysilicon and at least a portion of the epitaxial layer that will become the collector region are successively etched using this as a mask, and then impurities of the second conductivity type are implanted directly under the polysilicon and into the collector region by ion implantation. The emitter region and the collector region are formed by diffusion on the epitaxial layer of the second conductivity type.

<Operation> By forming the entire base region in the transistor part and removing the polysilicon in areas other than the emitter region, the epitaxial layer of the collector electrode extension part is also removed at the same time, so that the collector electrode extension part can be removed without increasing the number of steps. The thickness of the epitaxial film directly below can be reduced, reducing collector series resistance.

<Example> FIGS. 1(a) to 1(f) are schematic cross-sectional views showing an example according to the method of the present invention over time.

First, as shown in figure (a), after forming an N-type buried layer 4 and a P-type buried layer 3 on a P-type substrate 1, N-type epitaxial growth is performed on the entire surface, and an N-type epitaxial layer 5 is formed. Form. Next, the element bone #iI head region 2 is formed on the P゛-shaped buried layer 3.

Next, as shown in FIG. 3B, a base region 6 is formed by low-energy, high-dose ion implantation ("B") into the transistor section.

Next, as shown in the figure (C), thermal oxidation is performed to form an oxide film 21 with increased thickness. This oxide film 21 is
Since it is used as a mask for the next step of ion implantation, it is necessary to make the film thick enough to withstand the implantation energy. Next, after resist patterning is formed for the emitter electrode extension part 8a and the collector electrode extension part 8b, the emitter electrode extension part 8a and the collector electrode extension part 8 are
An opening is created by etching the oxide film 21 directly above b, then the resist is removed, and then polysilicon 7 is deposited on the surface.

Next, as shown in the figure (a), patterning is performed so as to leave a resist on the polysilicon directly above the portion that will become the emitter region 8a, and the polysilicon is removed by etching. At this time, the portion of the base region that is not covered with the oxide film and will become the collector electrode extension portion 8b is also removed. Next, after removing the resist, "As" ions are implanted into the polysilicon region directly above the emitter region 8a and the collector electrode extension part 8b to form the collector electrode extension part 8b.

Next, as shown in figure (e), undoped SiO□ is
After the CVD film 9 is formed by deposition using the VD method, an emitter region 8a is formed by performing annealing.

Next, as shown in the figure (f), contact holes are formed directly above the emitter region 8a, base region 6, and collector region 8b by photoetching, and then a metal electrode 101 is formed by a well-known method. A transistor according to the method is completed.

<Effects of the Invention> According to the present invention, since the N゜ region base region of the collector electrode extension portion is separated, good transistor characteristics can be obtained without affecting the collector-base breakdown voltage. Furthermore, since the collector series resistance is reduced, a high-speed device can be realized. Further, the above manufacturing method does not require an increase in the number of steps.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are schematic cross-sectional views showing examples according to the method of the present invention over time, and FIGS. 2(a) to (f) are
It is a schematic cross-sectional view showing a conventional method over time. 1... P-type substrate 2... Element isolation region 1... Oxide film (SiO□) 3... P'-type buried layer 4... N'-type buried layer 5... N-type Epitaxial layer 6...Base region 7...Polysilicon 8a...Emitter (polysilicon) 8b...Collector electrode extension portion 9...CVD film 01...Metal electrode region

Claims (1)

[Claims] A buried diffusion layer of a second conductivity type, a buried diffusion layer of a first conductivity type, and an epitaxial layer of a second conductivity type are formed on a substrate of a first conductivity type, and a base region of a first conductivity type is formed on a surface of the epitaxial layer. and a second conductivity type emitter region is formed in the first conductivity type base region, and a second conductivity type buried diffusion layer is formed on the second conductivity type buried diffusion layer by diffusion of second conductivity type impurities on the surface of the epitaxial layer. In a method for forming a collector region of a conductivity type, an epitaxial layer of a second conductivity type is formed, an element isolation film is formed, a region to become a base is formed by ion implantation, and an oxide film is formed by thermal oxidation. Then, after opening the substrate that will become the emitter and collector regions, polysilicon is grown over the entire surface, and then a resist pattern is formed to cover the emitter region, and this is used as a mask to grow polysilicon and the collector region. At least a portion of the epitaxial layer is subsequently etched, and then a second layer is etched by ion implantation.
1. A method of manufacturing a semiconductor device, comprising: forming an emitter region and a collector region by diffusing conductivity type impurities directly under polysilicon and onto a second conductivity type epitaxial layer that will become a collector region.