KR0135175B1 - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device

Info

Publication number
KR0135175B1
KR0135175B1 KR1019890012027A KR890012027A KR0135175B1 KR 0135175 B1 KR0135175 B1 KR 0135175B1 KR 1019890012027 A KR1019890012027 A KR 1019890012027A KR 890012027 A KR890012027 A KR 890012027A KR 0135175 B1 KR0135175 B1 KR 0135175B1
Authority
KR
South Korea
Prior art keywords
oxide film
collector
forming
emitter
base
Prior art date
Application number
KR1019890012027A
Other languages
Korean (ko)
Other versions
KR910005396A (en
Inventor
안형근
Original Assignee
문정환
엘지반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체주식회사 filed Critical 문정환
Priority to KR1019890012027A priority Critical patent/KR0135175B1/en
Publication of KR910005396A publication Critical patent/KR910005396A/en
Application granted granted Critical
Publication of KR0135175B1 publication Critical patent/KR0135175B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

A fabrication method of semiconductor devices is disclosed. The method comprises the steps of: forming an N+ buried layer(2) on a P-type substrate(1); growing an epi-layer(3) having a thickness of 1.5-3um; etching the silicon substrate(1) to isolate devices and ion-implanting; depositing an oxide layer(4) on the etched portion and ion-implanting to form a base region(5); ion-implanting phosphorous ions and boron ions, thereby forming an emitter region(6) and a collector region(7), respectively; forming a base contact(8) and a collector contact(10); and depositing a metal film on the resultant structure.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

제 1도는 본 발명의 반도체소자 제조공정도1 is a manufacturing process diagram of the semiconductor device of the present invention

제 2도는 종래의 반도체소자 제조공정도2 is a manufacturing process diagram of a conventional semiconductor device

＊도면의 주요부분에 대한 부호의 설명＊＊ Description of symbols for main parts of the drawings ＊

1 : P형 기판, 2 : N+매립형,1: P type substrate, 2: N + buried type,

3 : 에치택셜층, 4,41 : 산화막,3: etchant layer, 4,41: oxide film,

42 : 격리용 산화막, 5 : 베이스,42: oxide film for isolation, 5: base,

6 :에미터, 7 : 콜렉터,6: emitter, 7: collector,

8 : 베이스전극, 9 : 에미터전극,8: base electrode, 9: emitter electrode,

9a : 콜렉터전극9a: collector electrode

본 발명은 격리용 산화막을 이용하여 소자간 격리 및 에미터와 콜렉터간 격리를 하여 줌으로써 누설전류와 접합 캐패시턴스를 줄여주는 반도체소자 제조방법에 관한 것이다.The present invention relates to a semiconductor device manufacturing method that reduces leakage current and junction capacitance by isolation between devices and isolation between emitter and collector using an isolation oxide film.

종래의 반도체소자 제조방법은 제2도에 도시된 바와 같다.The conventional semiconductor device manufacturing method is as shown in FIG.

제2도(가)와 같은 P형 기판(10)에 제2도(나)와 같이 기판으로 n형 불순물을 주입하여 매립층(20)을 형성하고, 그 위에 제2도 (다)와 같이 n형 에피층(30)을 성장시킨다.The buried layer 20 is formed by implanting n-type impurities into the P-type substrate 10 as shown in FIG. 2A, as shown in FIG. 2B, and n is formed thereon as shown in FIG. The type epitaxial layer 30 is grown.

이후 제2도 (라)와 같이 격리층(40)을 형성하고, 제2도(마),(바)와 같이 베이스 마스크패턴을 이용하여 P형 불순물을 에피택셜층(30)으로 이온주입하여 베이스(50)를 형성한 후 에미터 및 콜렉터 마스크패턴을 이용하여 n형 불순물을 베이스영역(30)과 에피택셜층(30)으로 이온주입하여 에미터(60) 및 콜렉터(100)를 차례로 형성한다.Thereafter, the isolation layer 40 is formed as shown in FIG. 2 (d), and P-type impurities are implanted into the epitaxial layer 30 using the base mask patterns as shown in FIGS. 2 (e) and (f). After the base 50 is formed, n-type impurities are ion-implanted into the base region 30 and the epitaxial layer 30 using the emitter and collector mask patterns to form the emitter 60 and the collector 100 in sequence. do.

이어서, 제2도(사)와 같이 기판전면에 절연막(110)을 형성하고, 에미터(60), 베이스(50) 및 콜렉터(100)상의 절연막(110)을 제거하여 콘택홀을 형성한 후 금속막을 형성하여 각각의 전극(70-90)을 형성한다. 이로써, 전형적인 바이폴라 트랜지스터를 제조한다.Subsequently, as shown in FIG. 2, the insulating film 110 is formed on the entire surface of the substrate, and the contact hole is formed by removing the insulating film 110 on the emitter 60, the base 50, and the collector 100. Metal films are formed to form respective electrodes 70-90. This produces a typical bipolar transistor.

상기한 종래의 바이폴라 트랜지스터는 전자가 에미터(60)로 주입되어 베이스(50)와 N+형 매립층(20)을 거텨 콜렉터(100)로 흐를 때 연속적으로 연결되었으며, 격리층(40)에 의해 소자가 전기적으로 격리되도록 하였다.The conventional bipolar transistor is continuously connected when electrons are injected into the emitter 60 and flow through the base 50 and the N + type buried layer 20 through the collector 100, and by the isolation layer 40. The device was electrically isolated.

그러나, 상기한 같은 종래의 구조는 에피텍셜층(30)이 4-15㎛정도의 두께로 콘트롤되어 일반가정용 기기에 사용되므로, 단위이득이 1 GHZ미만인 소자에만 이용되 문제점이 있었다.However, the conventional structure described above has a problem that the epitaxial layer 30 is controlled to a thickness of about 4-15 μm and used in general household devices, so that only the device having a unit gain of less than 1 GHZ is used.

본 발명은 이와같은 종래의 문제점을 해결하기 위한 것으로서, 소자간과 에미터와 콜렉터간을 격리용 산화막을 이용하여 격리하여 줌으로써 누설전류와 접합 캐패시턴스를 감소시켜 줄수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and provides a method of manufacturing a semiconductor device that can reduce leakage current and junction capacitance by isolating between devices and emitters and collectors using an isolation oxide film. There is a purpose.

첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 발명의 실시예에 따른 반도체소자의 제조공정도를 도시한 것이다.1 shows a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

먼저, 제1도(가)와 같은 P형 기판(1)에 제1도(나)와 같이 N+매립형(2)을 형성하고, 제1도(다)와 같이 1.5-3㎛의 두께를 갖는 에피택셜층(3)을 N+매립층(2)을 포함한 기판상에 성장시킨다.First, the N + buried type 2 is formed on the P-type substrate 1 as shown in FIG. 1 (a), as shown in FIG. 1 (b), and the thickness of 1.5-3 μm as shown in FIG. The epitaxial layer 3 having is grown on the substrate including the N + buried layer 2.

이어서 제1도(라)와 같이 에피택셜층(3)상에 패드산화막(31)과 질화막(32)을 순차 형성하고, 소자 격리영역과 소자영역내의 베이스와 콜렉터를 격리시켜 주기 위한 격리영역이 형성될 부분의 질화막(32)과 패드질화막(31)을 선택 식각하여 에피택셜층(3)을 노출시킨다.Subsequently, as shown in FIG. 1D, a pad oxide film 31 and a nitride film 32 are sequentially formed on the epitaxial layer 3, and an isolation region for isolating the device isolation region and the base and the collector in the device region is provided. The nitride film 32 and the pad nitride film 31 of the portion to be formed are selectively etched to expose the epitaxial layer 3.

노출된 에피택셜층(3)을 선택 식각하여 격리영역을 형성하고, 산화공정을 수행하여 제1도(마)와 같이 에피택셜이 제거된 격리영역에 격리용(41)을 형성하고, 남아있는 질화막(32)과 산화막(31)을 제거한다. 그리고, 기판전면에 걸쳐 산화막(4)을 형성한다.Selectively etching the exposed epitaxial layer 3 to form an isolation region, and performing an oxidation process to form an isolation 41 in the isolation region from which epitaxial has been removed as shown in FIG. The nitride film 32 and the oxide film 31 are removed. Then, an oxide film 4 is formed over the entire surface of the substrate.

제1도(바)와 같이 마스크작업을 하여 베이스영역을 한정하고 P형 불순물을 에피택셜층(3)으로 이온주입하여 베아스(5)을 형성하고, 이어서 제1도(사)와 같이 마스크작업을 하여 에미터영역과 콜렉터영역을 한정하고 인과 비소이온을 해당 영역으로 각각 주입하여 에미터(6)와 콜랙터(7)를 형성한다.As shown in Fig. 1 (bar), the base area is defined to limit the base region, and p-type impurities are implanted into the epitaxial layer 3 to form the beas 5, and then the mask is shown as in Fig. 1 (g). The work defines the emitter region and the collector region and injects phosphorus and arsenic ions into the corresponding regions to form the emitter 6 and the collector 7.

제1도(아)와 같이 기판전면에 화학증착법(CVD)를 이용하여 다시 산화막(42)을 증착하고, 베이스, 에미터 및 콜렉터(5-7)상의 산화막(42)을 제거하여 에미터콘택, 베이스콘택 및 콜렉터콘택을 형성하며, 금속막을 기판상에 증착하고 패터닝하여 각 콘택에 베이스전극(8), 에미터전극(9) 및 콜렉터전극(9a)을 형성한다.As shown in FIG. 1 (h), the oxide film 42 is deposited on the entire surface of the substrate by chemical vapor deposition (CVD), and the emitter contact is removed by removing the oxide film 42 on the base, emitter, and collector 5-7. , Base contacts and collector contacts are formed, and a metal film is deposited and patterned on a substrate to form a base electrode 8, an emitter electrode 9, and a collector electrode 9a at each contact.

상기와 같은 공정에 의하여 제조되는 본 발명의 반도체소자는 전자가 에미터(6)로 주입되어 3부위가 산화막(42)과 격리용 산화막(41)에 의해 완전 차단되어 있으므로 접합 캐패시턴스가 감소되며, 또한, 콜렉터(7)도 베이스(5), 에미터와 N+매립층(2)을 통하지 않고도 산화막에 의해 3부위가 격리되어 있는 상태로서 상대적으로 누설전류가 줄어들어 고품질의 디바이스와 고속용소자를 제조할 수 있음은 물론 제조공정이 단순하게 시간절약을 가져올 수 있는 특징이 있다.In the semiconductor device of the present invention manufactured by the above process, since the electrons are injected into the emitter 6 and the three sites are completely blocked by the oxide film 42 and the isolation oxide film 41, the junction capacitance is reduced. In addition, the collector 7 is also in a state in which three sites are separated by an oxide film without passing through the base 5, the emitter and the N + buried layer 2, and the leakage current is relatively reduced, thereby producing high quality devices and high-speed devices. Of course, there is a feature that the manufacturing process can bring a simple time-saving.

Claims (1)

P형 기판(10)에 N+매립층(2)을 형성하는 공정과, N+매립층(2)을 포함한 기판상에 에피택셜층(3)을 성장시키는 공정과, 에피택셜층(3)상에 패드산화막(31)과 질화막(32)을 순차 형성하는 공정과, 소자간 격리영역 및 에미터와 콜렉터간의 격리영역에 해당하는 패트산화막(31)과 질화막(32)을 선택 식각하는 공정과, 패드산화막(31)과 질화막(32)의 제거에 노출된 에피택셜층(3)을 제거하는 공정과, 산화공정으로 에피택셜층(3)이 제거된 격리 영역에 격리용 산화막(41)을 형성하는 공정과, 남아 있는 패드산화막(31)과 질화막(32)을 제거한 후 기판전면에 산화막(4)을 형성하는 공정과, 베이스에 해당하는 에피택셜층으로 불순물을 이온주입하여 베이스(5)를 형성하는 공정과, 에미터와 콜렉터에 해당하는 에피택셜층으로 불순물을 이온주입하여 에미터(6)와 콜렉터(7)를 형성하는 공정과, 기판전면에 산화막(42)을 형성한 후 에미터(6), 베이스(5), 콜렉터(7)상의 산화막(42)을 제거하여 콘택을 형성하는 공정과, 각 콘택(8)(9)(10)에 베이스전극(8), 에미터전극(9) 및 콜렉터전극(9a)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자 제조방법.Forming an N + buried layer 2 on the P-type substrate 10, growing an epitaxial layer 3 on the substrate including the N + buried layer 2, and on the epitaxial layer 3. A step of sequentially forming the pad oxide film 31 and the nitride film 32, a step of selectively etching the pat oxide film 31 and the nitride film 32 corresponding to the isolation region between the elements and the isolation region between the emitter and the collector, and the pad; Removing the epitaxial layer 3 exposed to the removal of the oxide film 31 and the nitride film 32, and forming an isolation oxide film 41 in an isolation region from which the epitaxial layer 3 has been removed by the oxidation process. A step of removing the remaining pad oxide film 31 and the nitride film 32 and forming an oxide film 4 on the front surface of the substrate, and implanting impurities into the epitaxial layer corresponding to the base to form the base 5. And impurity ions are implanted into the epitaxial layer corresponding to the emitter and the collector to form the emitter 6 and the collector 7. A step of forming and forming a contact by removing the oxide film 42 on the emitter 6, the base 5, and the collector 7 after the oxide film 42 is formed on the front surface of the substrate, and each contact 8 And (9) (10) forming a base electrode (8), an emitter electrode (9) and a collector electrode (9a).
KR1019890012027A 1989-08-23 1989-08-23 Fabrication method of semiconductor device KR0135175B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890012027A KR0135175B1 (en) 1989-08-23 1989-08-23 Fabrication method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890012027A KR0135175B1 (en) 1989-08-23 1989-08-23 Fabrication method of semiconductor device

Publications (2)

Publication Number Publication Date
KR910005396A KR910005396A (en) 1991-03-30
KR0135175B1 true KR0135175B1 (en) 1998-04-25

Family

ID=19289182

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890012027A KR0135175B1 (en) 1989-08-23 1989-08-23 Fabrication method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0135175B1 (en)

Also Published As

Publication number Publication date
KR910005396A (en) 1991-03-30

Similar Documents

Publication Publication Date Title
KR100275540B1 (en) Super self-aligned bipolar transistor and its fabrication method
EP0076106B1 (en) Method for producing a bipolar transistor
KR100379586B1 (en) Self aligned double poly BJT formation method using SiGe spacers as extrinsic base contacts
JPS6028134B2 (en) Method of forming semiconductor structure
JP3098848B2 (en) Self-aligned planar monolithic integrated circuit vertical transistor process
KR900005123B1 (en) Bipolar transistor manufacturing method
JPH04234130A (en) Manufacture of self-aligned heterojunction bipolar transistor
GB2209872A (en) A method for fabricating a bipolar transistor
US4464825A (en) Process for fabrication of high-speed radiation hard bipolar semiconductor devices
KR0135175B1 (en) Fabrication method of semiconductor device
JPS5947468B2 (en) Bipolar transistor manufacturing method
KR100249168B1 (en) Manufacturing method of semiconductor device
JP2618921B2 (en) Method for manufacturing semiconductor device
KR950000137B1 (en) Manufacturing method of semiconductor device
KR0129194B1 (en) Fabrication method of bipolar junction transistor
KR940007658B1 (en) Manufacturing method of self-aligned homo, hetero-junction bipplar transistor using thin film crystal growth method
KR940007657B1 (en) Manufacturing method of high-speed bipolar transistor
KR930011542B1 (en) Manufacturing method of bipolar transistor
JPS5984469A (en) Manufacture of semiconductor device
KR100346822B1 (en) A method for fabrication of semiconductor devices comprising bipolar transistor and resistors
KR940005448B1 (en) Manufacturing method of bipolar npn transistor
JPH0433343A (en) Bipolar type semiconductor device and manufacture thereof
KR900000827B1 (en) Semiconductor device manufacturing method
JP3083542B2 (en) Manufacturing method of bipolar semiconductor integrated circuit device
KR930007189B1 (en) Manufacturing method of bipolar device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20051219

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee