KR930007189B1 - Manufacturing method of bipolar device - Google Patents

Manufacturing method of bipolar device Download PDF

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KR930007189B1
KR930007189B1 KR1019900012369A KR900012369A KR930007189B1 KR 930007189 B1 KR930007189 B1 KR 930007189B1 KR 1019900012369 A KR1019900012369 A KR 1019900012369A KR 900012369 A KR900012369 A KR 900012369A KR 930007189 B1 KR930007189 B1 KR 930007189B1
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KR920005379A (en
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정문모
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

The bipolar device is mfd. by (a) forming a buried layer (2), an epitaxial layer (3) and an isolated layer (4) on the fixed part of the substrate (1), (b) forming an oxide film (5) on the whole surface, and then selectively etching it to expose a base region, (c) forming an epitaxial layer (6) on the base region, and a polysilicon layer (7) on the film (5), (d) ion-implanting an impurity into the layers (6,7), (e) etching the fixed part of the layer (7) and the film (5) to expose the collector region, (f) forming an oxide film (8), (g) etching the fixed part of the film (8) to expose a base connection region (9), an emitter connection region (10) and a collector connection region (11), (h) ion-implanting an impurity into the regions (10,11) to form an emitter region (13) and a collector region (14), and (i) forming a base electrode (15), an emitter electrode (16) and a collector electrode (17).

Description

바이폴라 소자 제조방법Bipolar Device Manufacturing Method

제1도는 종래의 공정을 나타낸 단면도.1 is a cross-sectional view showing a conventional process.

제2도는 본 발명의 공정을 나타낸 단면도.2 is a sectional view showing a process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 대몰층1 substrate 2 large layer

3 : 에피택셜층 4 : 격리층3: epitaxial layer 4: isolation layer

5, 7 : 산화막 6 : 배이스영역5, 7: oxide film 6: bass area

7 : 폴리실리콘 9 : 에미터 영역7: polysilicon 9: emitter area

10 : P/R 11 : 금속10: P / R 11: metal

본 발명은 바이폴라 소자 제조방법에 관한 것으로, 특히 베이스영역을 에피택셜 성장에 의한 방법으로 형성하며 베이스 영역측면을 통해 베이스 콘택을 이룸으로써 디바이스 특성의 향상과 집적화에 적합하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar device manufacturing method, and in particular, the base region is formed by epitaxial growth, and the base contact is made through the side of the base region, thereby making it suitable for improving and integrating device characteristics.

종래 바이폴라 트랜지스터의 제조방법은 제1도 (a)에 도시된 바와같이 기판(1)에 매몰층(2), 에피택셜층(3), 격리층(4)을 형성하고 그 위해 산화막(5)을 성장시켜 베이스영역을 형성하기 위해 선택적으로 식각한다.In the conventional method of manufacturing a bipolar transistor, as shown in FIG. 1 (a), the buried layer 2, the epitaxial layer 3, and the isolation layer 4 are formed on the substrate 1, and the oxide film 5 is formed therefor. Is selectively etched to form a base region by growing.

그리고(b)와 같이 에피택셜층(3)에 P형 이온을 주입하여 베이스영역(6)을 형성한다.As shown in (b), the base region 6 is formed by implanting P-type ions into the epitaxial layer 3.

다음에 (c)와 같이 CVD 산화막(8)을 성장시키고 (d)와 같이 에미터영역 형성을 위해 CVD 산화막(8)을 선택적으로 식각한 다음, N형 이온을 주입하여 에미터영역(9)을 형성한후, (e)와 같이 배선(11)을 형성한다.Next, as shown in (c), the CVD oxide film 8 is grown, and as shown in (d), the CVD oxide film 8 is selectively etched to form an emitter region, and then N-type ions are implanted to emit the emitter region 9. After forming the wiring 11, the wiring 11 is formed as shown in (e).

이와같이 제조되는 바이폴라 트랜지스터는 베이스-에미터 순방향 바이어스, 베이스-콜랙터 역방향 바이어스 연결상태로 증폭작용 및 스위칭 역할을 하게 된다.The bipolar transistor thus manufactured serves as an amplification and switching function with a base-emitter forward bias and a base-collector reverse bias connection.

그러나, 상기와 같은 종래기술에 있어서는 베이스영역을 기판내에 형성함에 따라 후속공정에서 형성되는 에미터나 접합부분이 되는 표면에 손상을 입게되어 소자의 특성이 악화되는 문제가 있었다.However, in the prior art as described above, as the base region is formed in the substrate, there is a problem in that the surface of the emitter or the junction portion formed in the subsequent process is damaged and the characteristics of the device are deteriorated.

본 고안은 이와같은 종래의 결점을 해결하기 위한 것으로, 이를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.The present invention is to solve such a conventional defect, it will be described in detail with reference to the accompanying drawings, Figure 2 as follows.

먼저 (a)와 같이 P형 기판(1)에 "N"매몰층(2), N형 에피택셜층(3), 격리층(4)을 형성하고 그 위에 산화막(5)을 성장시킨 다음 베이스영역이 형성될 부분을 식각한다.First, as shown in (a), an “N” buried layer 2, an N-type epitaxial layer 3, and an isolation layer 4 are formed on a P-type substrate 1, and then an oxide film 5 is grown thereon. Etch the part where the region is to be formed.

그리고 (b)와 같이 상기 산화막(5)이 식각된 부분에 에피택셜 성장시키게 되면 에피택시(Epitaxy)공정특성상 산화막(5)이 식각된 부분에는 에피택셜층(6)이 형성되며 산화막(5) 위에는 폴리실리콘층(7)이 형성된다.When the oxide film 5 is epitaxially grown on the etched portion as shown in (b), an epitaxial layer 6 is formed on the portion where the oxide film 5 is etched due to the epitaxial process characteristic. The polysilicon layer 7 is formed thereon.

이어서, 고농도의 P형 이온을 상기 에피택셜층(6) 및 폴리실리콘층(7)에 주입하여 베이스영역(6)과 베이스 콘택 역할을 하는 폴리실리콘층(7)을 형성한다.Subsequently, a high concentration of P-type ions are implanted into the epitaxial layer 6 and the polysilicon layer 7 to form a polysilicon layer 7 serving as a base contact with the base region 6.

다음에 (c)와 같이 상기 폴리실리콘층(7) 및 산화막(4)의 소정부분을 식각하여 콜렉터영역을 오픈시킨 다음 CVD 공정을 이용하여 전면에 산화막(8)을 성장시킨다.Next, as shown in (c), predetermined portions of the polysilicon layer 7 and the oxide film 4 are etched to open the collector region, and then the oxide film 8 is grown on the entire surface by a CVD process.

이어서, (d)와 같이 사진식각 공정에 의해 상기 산화막(8)의 소정부분을 식각하여 상기 폴리실리콘층(7) 상의 베이스 콘택영역(9)과 상기 베이스영역(6)상의 에미터 콘택영역(10) 및 상기 에피택셜층(3)상의 콜렉터 콘택영역(11)을 동시에 오픈시킨다.Subsequently, as shown in (d), a predetermined portion of the oxide film 8 is etched by a photolithography process so that the base contact region 9 on the polysilicon layer 7 and the emitter contact region on the base region 6 ( 10) and the collector contact region 11 on the epitaxial layer 3 are simultaneously opened.

이어서 전면에 P/R을 입힌후 베이스 콘텍영역(9) 부위의 P/R(12)만 남기고 모두 제거한 상태에서 전면에 이온주입을 실시하여 에미터영역(13) 및 콜렉터영역(14)을 형성한다.Subsequently, after the P / R is coated on the front surface, ion implantation is performed on the front surface with only the P / R (12) in the base contact region (9) being removed, thereby forming the emitter region (13) and the collector region (14). do.

이때, 베이스 접합영역은 별도로 형성하지 않으며, 상기 베이스영역(6) 형성시 측면에 형성된 폴리실리콘층(7)을 베이스 접합영역으로 이용하게 된다.In this case, the base bonding region is not separately formed, and the polysilicon layer 7 formed on the side surface of the base region 6 is used as the base bonding region.

다음에 (e)와 같이 상기 P/R(12)을 제거한후 금속을 증착하고 소정 패턴으로 패터닝하여 상기 베이스영역(6) 측면의 폴리실리콘층(7)을 통해 베이스영역(6)과 콘택을 이루는 베이스(15)와 에미터(16) 및 콜렉터(17)를 가진 바이폴라 트랜지스터를 완성시킨다.Next, as shown in (e), the P / R 12 is removed, and then metal is deposited and patterned in a predetermined pattern to make contact with the base region 6 through the polysilicon layer 7 on the side of the base region 6. A bipolar transistor with base 15, emitter 16 and collector 17 is completed.

이와같이 제조되는 본 발명의 바이폴라 트랜지스터는 베이스영역을 기판상에 에피택셜 성장에 의한 양질의 에피택셜층으로 형성하여 디바이스 특성을 향상시킬 수 있으며, 에피텍셜 성장시 측면에 함께 형성되는 폴리실리콘층에 의해 베이스(15)와 베이스영역(6)간의 베이스 콘택이 이루어지므로써 집적도를 높일 수 있을 뿐만 아니라 측면 폴리실리콘이 그대로 베이스 접합영역이 되므로 접합영역을 한정 할 필요가 없게 되어 콘택영역 형성을 위한 사진식각공정시 발생되는 오정렬(Misalign) 부분을 제거할 수 있음과 아울러 마스크 층수를 줄일 수 있는 효과가 있다.The bipolar transistor of the present invention manufactured as described above can improve the device characteristics by forming the base region as a high quality epitaxial layer by epitaxial growth on the substrate, and by the polysilicon layer formed together on the side during epitaxial growth. Since the base contact between the base 15 and the base region 6 is made, not only the degree of integration can be increased but also the side polysilicon becomes the base joint region as it is, thus eliminating the need to limit the joint region. In addition to eliminating misalignment during the process, the number of mask layers can be reduced.

Claims (2)

제1도전형의 기판(1)의 소정부분에 제2도전형의 매몰층(2)과 제2도전형의 에피택셜층(3) 및 격리층(4)을 각각 형성하는 공정과, 상기 결과물 전면에 산화막(5)을 형성한후 선택적으로 식각하여 베이스영역을 노출시키는 공정, 에피택시 공정을 통해 상기 노출된 베이스영역상에 에피택셜층(6)을 형성함과 동시에 상기 산화막(5)상에 폴리실리콘층(7)을 형성하는 공정, 상기 에피택셜층(6) 및 폴리실리콘층(7)에 제1 도전형의 불순물을 이온주입하는 공정, 상기 폴리실리콘층(7) 및 산화막(5)의 소정부분을 식각하여 콜렉터영역을 노출시키는 공정, 상기 결과물 전면에 산화막(8)을 형성하는 공정, 상기 산화막의 소정부분을 식각하여 베이스 접합영역(9)과 에미터 접합영역(10) 및 콜렉터 접합영역(11)을 동시에 노출시키는 공정, 상기 베이스 접합영역을 제외한 영역에 불순물을 이온주입하여 에미터영역(13) 및 콜렉터영역(14)을 형성하는 공정, 및 상기 베이스 접합영역, 에미터영역 및 콜렉터영역상에 각각 베이스 전극(15), 에미터 전극(16) 및 콜렉터 전극(17)을 형성하는 공정을 구비하여 구성된 것을 특징으로 하는 바이폴라 소자 제조방법.Forming the buried layer 2 of the second conductive type, the epitaxial layer 3 and the isolation layer 4 of the second conductive type, respectively in a predetermined portion of the substrate 1 of the first conductive type, and the resultant product. Forming an epitaxial layer 6 on the exposed base region through an epitaxial process, and then selectively etching and forming an oxide film 5 on the entire surface. Forming a polysilicon layer 7 on the substrate, ion implanting impurities of a first conductivity type into the epitaxial layer 6 and the polysilicon layer 7, the polysilicon layer 7 and the oxide film 5 Exposing a collector region by etching a predetermined portion of the substrate; forming an oxide film 8 on the entire surface of the resultant; etching a predetermined portion of the oxide film to form a base junction region 9 and an emitter junction region 10; Exposing the collector junction region 11 simultaneously; an area excluding the base junction region Implanting impurities into the emitter region 13 and the collector region 14, and the base electrode 15 and the emitter electrode 16 on the base junction region, emitter region and collector region, respectively. And forming a collector electrode (17). 제1항에 있어서, 상기 베이스 접합영역은 상기 베이스영역(6) 측면에 상기 제1도전형의 불순물이 주입된 폴리실리콘층(7)으로 형성되는 것을 특징으로 하는 바이폴라 소자 제조방법.2. A method according to claim 1, wherein the base junction region is formed of a polysilicon layer (7) implanted with impurities of the first conductivity type on the side of the base region (6).
KR1019900012369A 1990-08-11 1990-08-11 Manufacturing method of bipolar device KR930007189B1 (en)

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KR930007189B1 true KR930007189B1 (en) 1993-07-31

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