JPH0529328A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate a need for the patterning process, of a semiconductor layer for emitter use, which has been required in conventional cases, to reduce the uneven part of a device and to flatten the device. CONSTITUTION:Carbon and As are ion-implanted into a p-type Si layer 25 for base use on an n-type Si substrate 21; an n-type SiC layer 29 for emitter use is formed in the Si layer 25. Consequently, it is not required to pattern the SiC layer 29, unlike conventional cases, and a process can be simplified. The surface of the SiC layer 29 does not protrude from the Si layer 25, the uneven part of a device can be reduced as compared with conventional cases and the device can be flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bipolar transistor and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view of a bipolar transistor which is a conventional semiconductor device.
9 to 662.

As shown in FIG. 6, an n-type Si layer 2 is epitaxially grown on an n ⁺ -type Si substrate 1 serving as a collector, and insulating films 3 and 4 are laminated and formed on the surface thereof. Of the base forming region is selectively etched to form the opening 5, the n-type Si layer 2 is exposed in the opening 5, and then the n-type Si layer exposed in the opening 5 is formed by low temperature epitaxial growth such as photo-CVD. A base p-type Si layer 6 is deposited and formed on the insulating film 4 and the insulating film 4.

At this time, the n-type Si layer 2 exposed in the opening 5
The p-type Si layer 6 formed on top of the p-type Si layer 6 becomes a single crystal reflecting the crystallinity of the underlying Si layer 2, but the p-type Si layer 6 formed on the insulating film 4 is formed.
The type Si layer 6 becomes polycrystalline, and the polycrystalline portion of the p-type Si layer 6 can be used as a lead-out electrode of the base.

Further, after the p-type Si layer 6 is patterned, an insulating film 7 is deposited on the p-type Si layer 6, and the opening 8 is formed in the insulating film 7 on the single crystal Si layer 6 in the opening 5 portion.
Is formed to expose the lower p-type Si layer 6, and an n-type polycrystalline SiC layer 9 for emitter is deposited and formed on the p-type Si layer 6 and the insulating film 7 exposed in the opening 8. An n-type polycrystalline Si layer 10 is provided on the crystalline SiC layer 9 for ohmic contact between the SiC layer 9 and the emitter electrode.
After being laminated, the polycrystalline SiC layer 9 and the polycrystalline Si layer 10 are patterned so as to remain only in the upper portion of the opening 5.

After that, the lower p-type Si layer 6 in which the opening 11 is formed in the insulating film 7 on the polycrystalline Si layer 6 on the insulating film 4 is formed.
Are exposed and an emitter electrode 12 made of aluminum or the like is formed on the polycrystalline Si layer 10, and a base electrode 13 made of aluminum or the like is formed on the p-type Si layer 6 exposed in the opening 11.

By the way, in the case of the above structure, since the p-type Si layer 6 for the base is deposited by the low temperature epitaxial growth method, the p-type Si layer 6 can be formed extremely thin,
Further, since the n-type polycrystalline SiC layer 9 is used for the emitter, the band gap of the SiC layer 9 for the emitter is wider than that of the Si layer 6 for the base, and the junction between the emitter and the base is a heterojunction. As a result, even if the impurity concentration of the base is increased to reduce the resistance of the base in order to increase the speed,
There is an advantage that it is possible to suppress the reverse injection of holes into the emitter, obtain a desired amplification factor, and enable high speed operation.

[0008]

In the conventional case, the polycrystalline SiC layer 9 for the emitter has to be deposited and formed and then patterned, which requires a patterning step.
There is a problem that the process becomes complicated.

Further, since the polycrystalline SiC layer 9 is deposited, the thickness of the SiC layer 9 is added as the thickness of the entire device, so that the unevenness of the device becomes large.

The present invention has been made to solve the above-mentioned problems, and eliminates the conventional patterning step of the semiconductor layer for the emitter, and further reduces the unevenness of the device for planarization. The purpose is to be able to achieve.

[0011]

According to another aspect of the present invention, there is provided a semiconductor device having a first conductivity type semiconductor substrate which serves as a collector, a second conductivity type base semiconductor layer deposited and formed on the semiconductor substrate, It is characterized in that the semiconductor layer for base is provided with an emitter semiconductor layer having a wider bandgap than the semiconductor layer for base formed by introducing carbon and impurities of the first conductivity type.

In addition, the manufacturing method includes a step of forming a first insulating film on a semiconductor substrate of the first conductivity type serving as a collector, and an opening is formed in the first insulating film to form the semiconductor substrate. Exposing step, depositing and forming a second conductive type base semiconductor layer on the exposed semiconductor substrate and the first insulating film, and forming a second insulating film on the base semiconductor layer And exposing the base semiconductor layer by forming an opening in the second insulating film, and introducing carbon and a first conductivity type impurity into the exposed base semiconductor layer to form the base semiconductor layer. It is advantageous to include the step of forming an emitter semiconductor layer having a wider band gap than the semiconductor layer, and the step of forming a first conductivity type semiconductor layer on the emitter semiconductor layer and the second insulating film. Target.

[0013]

In the semiconductor device of the present invention, since the emitter semiconductor layer having a wider bandgap than the base semiconductor layer is formed in the base semiconductor layer on the semiconductor substrate, the emitter semiconductor layer is patterned as in the conventional case. In addition, the surface of the semiconductor layer for the emitter does not protrude beyond the semiconductor layer for the base, and planarization can be achieved with less unevenness of the device than before.

Further, carbon and impurities of the first conductivity type are introduced into the base semiconductor layer exposed in the opening of the second insulating film to form an emitter semiconductor layer having a wider band gap than the base semiconductor layer. An emitter semiconductor layer is formed in the base semiconductor layer.

[0015]

1 to 5 are sectional views showing an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention, and the manufacturing process thereof will be described below.

First, as shown in FIG. 1, two layers of insulating films 22 and 23 are laminated as a first insulating film on the surface of a Si substrate 21 which is an n-type semiconductor substrate serving as a collector. The base forming regions of 22 and 23 are selectively etched to form an opening 24, and an n-type Si is formed in the opening 24.
After a part of the surface of the substrate 21 is exposed, as shown in FIG. 2, p-type Si as a base semiconductor layer is formed on the n-type Si substrate 21 and the insulating film 23 exposed in the opening 24 by an epitaxial growth method. The layer 25 is formed by stacking, and the second insulating film 26 is formed on the p-type Si layer 25.

At this time, the p-type Si layer 25 formed on the n-type Si substrate 21 exposed in the opening 24 becomes a single crystal reflecting the crystallinity of the underlying Si substrate 21, as in the conventional case. The p-type Si layer 25 formed on 23 becomes polycrystalline, and the polycrystalline portion of the p-type Si layer 25 can be used as a lead-out electrode of the base. Si for use as an extraction electrode
After the layer 25 is patterned, a second layer is formed on the Si layer 25.
The insulating film 26 is formed.

Further, as shown in FIG. 3, a photoresist 27 is applied and formed on the second insulating film 26, and an opening 24 is formed.
An opening 28 is formed in the photoresist 27 and the second insulating film 26 on the portion of the single crystal Si layer 25, and p is formed in the opening 28.
-Type Si layer 25 is exposed, and p-type Si exposed in opening 28
Ion implantation introduces into the layer 25 n-type impurities such as carbon ions with a dose of 10 ¹⁸ cm ^-2 and arsenic (As) ions with a dose of 10 ¹⁴ to 10 ¹⁶ cm ^-2 .

After that, the photoresist 27 is removed, and a heat treatment is performed. As shown in FIG. 4, p-type Si for the base is used.
An n-type emitter SiC layer 29 having a wider band gap than Si is formed in the layer 25, and ohmic contact between the SiC layer 29 and an emitter electrode described later is formed on the SiC layer 29 and the second insulating film 26. N-type S to obtain
After the i layer 30 is formed, this polycrystalline Si layer 30 is patterned so as to remain only in the upper portion of the opening 24.

Then, as shown in FIG. 5, an opening 31 is formed in the second insulating film 26 on the polycrystalline Si layer 25 on the insulating film 23.
Is formed to expose the lower p-type Si layer 25, and the emitter electrode 3 made of aluminum or the like is formed on the polycrystalline Si layer 30.
2 is formed, and the base electrode 33 made of aluminum or the like is formed on the p-type Si layer 25 exposed in the opening 11 to complete a bipolar transistor which is a semiconductor device.

Therefore, the Si for the base on the Si substrate 21
Since the SiC layer 29 for the emitter is formed in the layer 25,
Since the conventional patterning of the SiC layer 29 is not necessary, a heterojunction emitter / base junction can be formed by a simpler process than the conventional one, and a desired bipolar transistor capable of high-speed operation can be obtained.

Further, by forming the SiC layer 29 for the emitter in the Si layer 25 for the base, the surface of the SiC layer 29 does not protrude from the Si layer 25, and the unevenness of the device can be reduced as compared with the conventional case. Therefore, it becomes possible to achieve flattening.

Further, by ion-implanting n-type impurities such as carbon and As into the Si layer 25 for base exposed in the second insulating film 26, Si for emitter is formed in the Si layer 25.
The C layer 29 can be formed to obtain a heterojunction emitter-base junction.

Of course, the emitter SiC layer 29 formed in the base Si layer 25 may be polycrystalline as in the conventional case.

[0025]

As described above, according to the present invention, the emitter semiconductor layer having a wider bandgap than the base semiconductor layer is formed in the base semiconductor layer on the semiconductor substrate. Since the patterning of the semiconductor layer for use is unnecessary, the process can be simplified compared to the conventional method, and the surface of the semiconductor layer for the emitter does not protrude more than the semiconductor layer for the base. Therefore, it is suitable as a bipolar transistor or the like that can operate at high speed.

Further, by introducing carbon and impurities of the first conductivity type into the base semiconductor layer exposed in the opening of the second insulating film, an emitter semiconductor layer having a wider bandgap than the base semiconductor layer is formed. The semiconductor layer for emitter can be formed in the semiconductor layer for base.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

21 Si substrate 22, 23 First insulating film 24 openings 25 Si layer for base 26 Second insulating film 29 SiC layer for emitter 30 Polycrystalline Si layer

Claims (2)

[Claims] 1. A first-conductivity-type semiconductor substrate serving as a collector, a second-conductivity-type semiconductor layer deposited on and formed on the semiconductor substrate, carbon in the base-semiconductor layer, and a first-conductivity type A semiconductor device for an emitter having a wider bandgap than the semiconductor layer for a base, which is formed by introducing the impurity of 1. 2. A step of forming a first insulating film on a semiconductor substrate of the first conductivity type which serves as a collector, a step of forming an opening in the first insulating film to expose the semiconductor substrate, and an exposing step. A second layer on the semiconductor substrate and on the first insulating film
Depositing and forming a conductive type semiconductor layer for base; forming a second insulating film on the semiconductor layer for base;
A step of forming an opening in the second insulating film to expose the base semiconductor layer; and introducing carbon and a first conductivity type impurity into the exposed base semiconductor layer so that the base semiconductor layer is more exposed than the base semiconductor layer. A semiconductor device comprising: a step of forming an emitter semiconductor layer having a wide bandgap; and a step of forming a first conductivity type semiconductor layer on the emitter semiconductor layer and the second insulating film. Manufacturing method.