JPH04312926A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce a junction capacitance between the base and collector of a bipolar transistor. CONSTITUTION:The first oxide film 220 covering a collector layer of the second conductive type is provided. By the solid phase epitaxial growth using a gas containing impurities that are able to become the first conductive impurities and hetero materials, and selectively formed simultaneously in a self-alignment manner are, respectively, an intrinsic base layer 18 of the first conductive type consisting of a monocrystal hetero base layer on the collector layer through a selective opening portion of the first oxide film 110 and an external base electrode takeoff layer 19 of the first high-impurity concentration conductive type consisting of a polycrystal line hetero base layer on the first oxide film 110 in conformity with the intrinsic base layer 18. Also, the second oxide film 112 covering the intrinsic base layer 18 is provided, and the second high-impurity concentration conductive emitter layer 21 is selectively formed on the intrinsic base layer 18 through a selective opening portion in the second oxide film 112.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device and a method for manufacturing the same.
tor. A semiconductor device having a HBT (hereinafter referred to as HBT),
and its manufacturing method.

0002

2. Description of the Related Art The general structure of a conventional HBT of this kind is schematically shown in FIG. 7, and the main manufacturing steps of the HBT are sequentially schematically shown in FIGS. 8 to 11.

First, the configuration of a conventional HBT shown in FIG. 7 will be described.

That is, in the device configuration of the HBT shown in FIG. 7, numeral 1 is an n+ type silicon substrate;
, 6, and 5 are a collector layer made of an n-type epitaxial layer formed by sequentially depositing and selectively molding on the n+ type silicon substrate 1, a base layer made of a p-type heteroepitaxial layer, and an n+ The emitter layer 8 made of a type epitaxial layer is a p+ type base electrode extraction layer (external base layer) selectively formed within the p type base 6. Further, 100 is an oxide film coated on each layer, and 200 and 201 are oxide films 10 and 201.
An emitter electrode and a base electrode are respectively connected to the n+ type emitter layer 5 and the p+ type base electrode extraction layer 8 through through holes selectively opened to zero.

Next, the manufacturing process of the conventional HBT shown in FIGS. 8 to 11 corresponding to the structure shown in FIG. 7 will be described.

A conventional HBT having the configuration shown in FIG.
In the first step (corresponding to FIG. 8), n
On a + type silicon substrate 1, an n- type epitaxial layer 2, a p-type heteroepitaxial layer 3, and an n+ type silicon epitaxial layer 4 are successively deposited in sequence by molecular beam epitaxy or the like.

In the second step (corresponding to FIG. 9), a patterned resist film 5 is formed by photolithography.
0 as a mask, the n+ type silicon epitaxial layer 4 is selectively etched away, thereby forming the n+ type emitter layer 5.

In the third step (corresponding to FIG. 10), similarly to the above, a patterned resist film 51 is used as a mask by photolithography to remove n-type from the p-type heteroepitaxial layer 3. By selectively etching away part of the epitaxial layer 2,
A p-type base layer 6 and an n-type collector layer 7 are formed respectively.

In the fourth step (FIG. 11), an oxide film 100, which will become an interlayer insulating film, is deposited on the entire surface at a low temperature so as to cover each of the layers.

Subsequently, in the fifth step, as shown in FIG. 7, the oxide film 100 is patterned with a resist film (
(not shown) as a mask, the n+ type emitter layer 5,
and each through hole 20 corresponding to the p-type base layer 6
0a and 201a are opened, p-type impurities are ion-implanted at low energy to reduce the base contact resistance, and activated by low-temperature annealing to form p+-type impurities on the p-type base layer 6. The base electrode extraction layers 8 are selectively formed.

[0011] At this time, n
Similarly, p-type impurities are ion-implanted into the n+-type emitter layer 5, but in this case, no particular problem arises because the n+-type emitter layer 5 itself has a high concentration.

Thereafter, as is well known, the emitter electrode 200 and each base electrode 201 are connected to the n+ type emitter layer 5 and each p+ type base electrode extraction layer 8 through the through holes 200a and 201a, respectively. A collector electrode (not shown here) is taken from the back side of the substrate, and in this way a conventional HBT with the desired configuration is obtained.

[0013]

[Problems to be Solved by the Invention] However, in the conventional HBT configured as described above, since the junction capacitance between the base and the collector is large due to each p+ type base electrode extraction layer (external base layer), the base There is a problem in that the resistance increases, which reduces the speed improvement of the bipolar transistor.

[0014] This invention was made in order to improve these conventional problems, and its purpose is to reduce the junction capacitance between the base and collector of a bipolar transistor to increase its speed. This type of semiconductor device and its manufacturing method are described here.
An object of the present invention is to provide a semiconductor device having T and a method for manufacturing the same.

[0015]

Means for Solving the Problems In order to achieve the above object, a semiconductor device and a method for manufacturing the same according to the present invention provide a first conductivity type collector layer covering a second conductivity type collector layer in an HBT.
A single-crystal hetero base layer is formed on the collector layer through a selective opening in the first oxide film by solid-phase epitaxial growth using a gas containing impurities of the first conductivity type and impurities that can become a hetero material. In accordance with the first conductivity type intrinsic base layer consisting of and the intrinsic base layer,
On the first oxide film, each of the high concentration first conductivity type external base electrode extraction layers made of a polycrystalline heterobase layer is simultaneously selectively formed in a self-aligned manner, and a second oxide film covering the intrinsic base layer is formed. A high concentration emitter layer of the second conductivity type is selectively formed on the intrinsic base layer through the selective opening of the second oxide film.

That is, the present invention provides a semiconductor device having a hetero bipolar transistor, which includes a collector layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type;
By solid-phase epitaxial growth using a gas containing an impurity of the first conductivity type and an impurity that can become a hetero material, the material is selectively formed on the collector layer through a selective opening in the first oxide film covering the collector layer in a self-aligned manner. A first conductivity type intrinsic base layer consisting of the formed single crystal hetero base layer, and a polygonal layer connected to the intrinsic base layer and simultaneously selectively formed on the first oxide film in a self-aligned manner. A highly concentrated external base electrode extraction layer of the first conductivity type consisting of a crystalline heterobase layer and a selective opening of a second oxide film covering the intrinsic base layer are selectively formed on the intrinsic base layer. The semiconductor device is characterized in that it includes at least an emitter layer of a second conductivity type.

The method of the present invention is also a method for manufacturing a semiconductor device having a hetero-bipolar transistor, which comprises: depositing a collector layer of a second conductivity type on a semiconductor substrate of a first conductivity type; a step of forming an element isolation oxide film reaching the inside of the substrate from the surface, and a step of covering the collector layer with a first oxide film and selectively opening a portion corresponding to the active region in the first oxide film. and depositing a silicon layer of the first conductivity type on the first oxide film including the opening by solid-phase epitaxial growth using a gas containing impurities of the first conductivity type and an impurity that can become a hetero material. , in the deposited portion on the collector layer through the opening, a single-crystal heterobase layer is grown using the single crystal of the collector layer as a growth nucleus to form a first conductivity type intrinsic base layer in a self-aligned manner; and at the same time,
In the deposited portion on the first oxide film, a step of growing a polycrystalline heterobase layer having an arbitrary crystal direction to selectively form a highly concentrated first conductivity type external base electrode extraction layer in a self-aligned manner; covering the first oxide film including the intrinsic base layer and the external base electrode extraction layer with a second oxide film, and selectively opening a portion of the second oxide film corresponding to the intrinsic base layer; A method of manufacturing a semiconductor device is characterized in that it includes at least the steps of selectively forming a highly doped emitter layer of a second conductivity type on the intrinsic base layer through the opening.

[0018]

[Operation] Therefore, in the semiconductor device and the manufacturing method thereof according to the present invention, the first oxide film covering the collector layer of the second conductivity type is provided in the HBT, and in this state, impurities of the first conductivity type and By solid-layer epitaxial growth using a gas containing impurities that can become a hetero material, an intrinsic base layer of the first conductivity type consisting of a single crystal hetero base layer is formed on the collector layer through a selective opening of the first oxide film; In accordance with the intrinsic base layer, the highly concentrated first conductivity type external base electrode extraction layer made of a polycrystalline heterobase layer is selectively formed on the first oxide film at the same time, so that the external base electrode extraction layer and the collector A first oxide film is interposed between the first oxide film and the first oxide film to reduce the base-collector junction capacitance, and the intrinsic base layer and the external base electrode extraction layer can be selectively formed in a self-aligned manner.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to FIGS. 1 to 6.

FIG. 1 is a sectional view schematically showing the general structure of a semiconductor device, in this case an HBT, to which an embodiment of the present invention is applied, and FIGS. 2 to 6 show the main manufacturing steps of the HBT. FIG. 3 is a cross-sectional view schematically illustrating the steps sequentially.

First, the configuration of the HBT according to the embodiment shown in FIG. 1 will be described.

That is, the HBT according to the embodiment shown in FIG.
In this configuration, reference numeral 11 is a p-type semiconductor substrate, for example, a p-type silicon substrate, and 12 and 13 are an n+-type floating collector layer and an n- This is an epitaxial layer of the type. Reference numeral 14 indicates each inter-element insulating groove selectively dug from the n-type epitaxial layer 13 through the n+-type floating collector layer 12 to reach the p-type silicon substrate 11, and 15 indicates each inter-element insulating groove. 14 is a P+ type layer for channel cutting selectively diffused and formed in each substrate portion corresponding to the groove bottom, and 16 is an isolation oxide film that fills the inside of each inter-element insulating groove 14.

Further, 17 indicates an n+ type collector wall layer which is selectively diffused in a predetermined region of the n- type epitaxial layer 13 and is in contact with the n+ type floating collector layer 12, and 18 indicates the first oxide film 110 of
Single crystal SiGe (
It is a p-type intrinsic base layer based on a heterobase) layer,
Reference numeral 19 denotes a p+ type external base electrode extraction layer made of a polycrystalline silicon layer connected to the p type intrinsic base layer 18 and selectively formed on the oxide film 110.

Furthermore, reference numeral 20 denotes each of the second and first oxide films 11.
2,110 through the n+ type collector wall layer 17
21 is a polycrystalline silicon layer selectively formed to be in contact with the p-type intrinsic base layer 18 through the second oxide film 112. n+ by layer
This is the emitter layer of the mold.

Furthermore, 210, 211, and 212
are base electrodes connected to the p+ type external base electrode extraction layer 19 through the third oxide film 114, respectively;
A collector electrode is connected to the n+ type collector electrode extraction layer 20, and an emitter electrode is connected to the n+ type emitter layer 21.

Next, the manufacturing process of the HBT in the embodiment shown in FIGS. 2 to 6, which corresponds to the structure shown in FIG. 1, will be described.

In the case of the HBT having the embodiment configuration shown in FIG. 1, in the first step (corresponding to FIG. 2), on a p-type semiconductor substrate, for example, p-type silicon substrate , an n+ type floating collector layer 12 is deposited, and then an n- type semiconductor layer, for example an n- type epitaxial layer 13, is deposited.

Further, selective etching is performed on the corresponding both sides of the n- type epitaxial layer 13 using a patterned resist film (not shown) as a mask, so that the n+-type floating collector layer 12 is etched.
Each of the inter-element insulation grooves 14 reaching into the p-type silicon substrate 11 is selectively dug, and a P+ type layer 15 for channel cutting is selectively diffused into each substrate portion corresponding to the bottom of the groove. By depositing an oxide film on the entire surface, the inside of each of these inter-element insulation grooves 14 is filled with the oxide film, and individual isolation oxide films 16 are selectively formed, and the deposited oxide film is etched on the entire surface. The surface of the n-type epitaxial layer 13 is exposed by backing it up.

Next, the n-type epitaxial layer 13
Similarly, using a patterned resist film (not shown) as a mask,
The n+ type collector wall layer 1 is formed by ion-implanting n-type impurities, such as arsenic, at a high concentration and by heat treatment.
7, a first oxide film 110 is deposited on the entire surface of the n-type epitaxial layer 13 including these parts, and a corresponding part 110a of the first oxide film 110 that will later become an active region is formed. is selectively etched away to form an opening, and the surface of this n-type epitaxial layer 13 is exposed again.

In the second step (corresponding to FIG. 3), the entire surface of the first oxide film 110, including the opening portion 110a, is treated with p-type impurities, such as boron, and impurities that can become a hetero material. , for example, by solid-layer epitaxial growth using a gas containing germanium (Ge), for example, by growing and depositing silicon at a reduced pressure of SiH4 gas of about 50 Torr and a high temperature of about 1000° C., the opening portion 110a is formed. Regarding the deposited portion that is in contact with the n-type epitaxial layer 13 through the layer, the single crystal in the n-type epitaxial layer 13 becomes a growth nucleus, and single-crystal SiGe (heterobase) is grown.
In this case, the p-type intrinsic base layer 18 is selectively grown, while the crystal orientation of the oxide film 110 is oriented in the deposited portion that is in contact with the first oxide film 110. Since this is arbitrary, a polycrystalline SiGe (heterobase) layer having an arbitrary crystal direction, in this case a p+ type polycrystalline silicon layer 111, is selectively grown.

In the third step (corresponding to FIG. 4), the p+ type polycrystalline silicon layer 111 is selectively etched using a patterned resist film (not shown) as a mask to form a corresponding region that will later become a base region. By leaving only a portion of the p-type intrinsic base layer 18 and the molded polycrystalline silicon layer 111, the other portions are selectively removed and molded. Therefore, each of the p+ type external base electrode extraction layers 19 can be selectively formed simultaneously and in a self-aligned manner.

In the fourth step (corresponding to FIG. 5), after depositing the second oxide film 112 on the surface of each part, similarly, a patterned resist film (not shown) is used as a mask. Depending on the selective etching used, the n+
Opening 112a, 1 reaching mold collector wall layer 17
10b and the opening 112b reaching the p-type intrinsic base layer 18 are selectively opened, respectively, and the entire surface including each of these openings is covered with n+ type polycrystalline silicon doped with n-type impurities at a high concentration. Deposit layer 113.

In the fifth step (corresponding to FIG. 6), the n+ type polycrystalline silicon layer 113 is selectively formed by selective etching using a patterned resist film (not shown) as a mask. An n+ type collector electrode extraction layer 20 in contact with the collector wall layer 17 and an n+ type emitter layer 21 in contact with the p type intrinsic base layer 18 are selectively formed.

Subsequently, in the sixth step, the process shown in FIG.
As can be seen, a second oxide film 1 is formed on the surface of each part.
14, the p+ type external base electrode extraction layer 19,n is similarly etched by selective etching using a patterned resist film (not shown) as a mask.
Openings 114a and 11 corresponding to the + type collector electrode extraction layer 20 and the n+ type emitter layer 21, respectively
4b and 114c are opened, and the base electrode 210 is connected to the p+ type external base electrode extraction layer 19, the collector electrode 211 is connected to the n+ type collector electrode extraction layer 20, and the n+ Emitter electrodes 212 are selectively formed for each of the mold emitter layers 21.

That is, in this way, the HBT structure in the embodiment shown in FIG. 1 can be manufactured as expected.

Therefore, in this embodiment, after providing the first oxide film 110 covering the n-type epitaxial layer 13, solid-layer epitaxial growth is performed using a gas containing p-type impurities and impurities that can become a hetero material. Through the selective opening 110a of the first oxide film 110,
A p-type intrinsic base layer 18 made of a single-crystal heterobase layer is formed on the n-type epitaxial layer 13, and a polycrystalline hetero-base layer is formed on the first oxide film 110 in accordance with the p-type intrinsic base layer 18. Since the p+ type external base electrode extraction layer 19 and the n+ type external base electrode extraction layer 19 are selectively formed at the same time, the p+ type external base electrode extraction layer 19 and
A first oxide film 110 between the - type epitaxial layer 13
is interposed between the p-type intrinsic base layer 1 and the junction capacitance between the base and collector is effectively reduced, thereby improving the high-speed operation of the transistor.
8 and p+ type external base electrode extraction layer 19 can be selectively formed in a self-aligned manner.

[0037]

[Effects of the invention] As described above in detail through the examples,
According to the semiconductor device and the manufacturing method thereof according to the present invention, the first oxide film covering the collector layer of the second conductivity type is provided in the HBT, and in this state, impurities of the first conductivity type and hetero By solid-layer epitaxial growth using a gas containing impurities that can be used as a material, an intrinsic base layer of the first conductivity type consisting of a single-crystal heterobase layer is formed on the collector layer through a selective opening in the first oxide film, and this intrinsic base layer is formed on the collector layer. The external base electrode extraction layer is selectively formed at the same time as the highly concentrated first conductivity type external base electrode extraction layer made of a polycrystalline heterobase layer on the first oxide film according to the layer. Since the first oxide film is interposed between the layer and the collector layer, the junction capacitance between the base and the collector is reduced, which significantly improves the high-speed operation of the transistor. Since the intrinsic base layer and the external base electrode extraction layer can be selectively formed at the same time in a self-aligned manner, there are advantages such as miniaturization of the element structure itself and, in turn, the ability to easily achieve high integration of the device. It has several features.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view schematically showing an outline of the configuration of a main part of a hetero-bipolar transistor (HBT) to which an embodiment of a semiconductor device according to the present invention is applied.

FIG. 2 is a schematic cross-sectional view showing an outline of a first step in manufacturing the HBT according to the embodiment configuration of FIG. 1;

FIG. 3 is a schematic cross-sectional view showing an outline of the second step of the same as above.

FIG. 4 is a schematic cross-sectional view showing an outline of the third step of the same.

FIG. 5 is a schematic cross-sectional view showing an outline of the fourth step of the same.

FIG. 6 is a schematic cross-sectional view showing an outline of the fifth step of the same.

FIG. 7 is a cross-sectional view schematically showing the configuration of the main parts of the HBT according to the conventional example.

8 is a schematic cross-sectional view showing an outline of the first step in manufacturing the HBT according to the conventional configuration shown in FIG. 7; FIG.

FIG. 9 is a schematic cross-sectional view showing an outline of the second step of the same.

FIG. 10 is a schematic cross-sectional view showing an outline of the third step of the same.

FIG. 11 is a schematic cross-sectional view showing an overview of the fourth step of the same.

[Explanation of symbols]

11 p-type silicon substrate 12 n+ type floating collector layer 13 n-
type epitaxial layer 14 Inter-element insulation groove 15 P+ type layer 16 for channel cut Isolation oxide film 17 N+ type collector wall layer 18 P type intrinsic base layer 19 P+ type external base electrode extraction layer 20 n+
type collector electrode extraction layer 21 n+ type emitter layer 110 first oxide film 111 p+ type polycrystalline silicon layer 112 second oxide film 113 n+ type polycrystalline silicon layer 114 third oxide film 210 base electrode 211 collector electrode 212 emitter electrode

Claims (2)

[Claims] 1. A semiconductor device having a hetero bipolar transistor, comprising a collector layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, an impurity of a first conductivity type, and an impurity that can become a hetero material. A first conductive layer consisting of a single crystal heterobase layer selectively formed on the collector layer in a self-aligned manner through a selective opening in a first oxide film covering the collector layer by solid-layer epitaxial growth using a gas containing a highly concentrated first conductivity type intrinsic base layer consisting of a polycrystalline heterobase layer connected to the intrinsic base layer and simultaneously selectively formed on the first oxide film in a self-aligned manner; It comprises at least an external base electrode extraction layer and a highly concentrated emitter layer of a second conductivity type selectively formed on the intrinsic base layer through a selective opening in a second oxide film covering the intrinsic base layer. What is claimed is: 1. A semiconductor device comprising: 2. A method for manufacturing a semiconductor device having a hetero bipolar transistor, comprising depositing a collector layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and depositing a collector layer of a second conductivity type from the surface of the collector layer into the substrate. a step of forming an inter-element isolation oxide film that reaches the top of the collector layer, a step of covering the collector layer with a first oxide film, and selectively opening a portion corresponding to the active region in the first oxide film, and a step of forming the opening. A silicon layer of the first conductivity type is deposited on the first oxide film containing the first conductivity type by solid-phase epitaxial growth using a gas containing an impurity of the first conductivity type and an impurity that can become a hetero material, and the opening is In the deposited portion on the collector layer passed through, a single crystal heterobase layer is grown using the single crystal of the collector layer as a growth nucleus to form an intrinsic base layer of the first conductivity type in a self-aligned manner, and at the same time, In the deposited portion on the first oxide film, a step of growing a polycrystalline heterobase layer having an arbitrary crystal direction to selectively form a highly concentrated first conductivity type external base electrode extraction layer in a self-aligned manner; A first layer including an intrinsic base layer and an external base electrode extraction layer.
oxide film is covered with a second oxide film, and the second oxide film is covered with a second oxide film;
at least the steps of: selectively opening a portion of the oxide film corresponding to the intrinsic base layer; and selectively forming a highly concentrated emitter layer of the second conductivity type on the intrinsic base layer through the opening. A method for manufacturing a semiconductor device, characterized by: