JPS5852817A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form an integrated circuit having analog and digital circuit co-existing therein, at a high degree of integration, by providing a metal electrode in a window by emplying a self-alignment method using as a mark a polycrystalline silicon layer and a silicon oxide film layer surrounding the former. CONSTITUTION:Nitride films, 4, 6 are formed on the whole surface. Then, windows 7 are opened therein, and polycrystalline silicon layers 8, 9 are formed on the whole surface. After N type impurities are introduced, a pattern is formed. Since a silicon layer 2 is covered with the nitride film 4, there is not possibility of growth of any oxide film due to oxidation, and only the polycrystalline silicon layers 8, 9 are selectively oxidized to form an oxide film layer 10 thicker than an oxide film 3 as a ground. During the oxidation, the N type impurities are diffused into a single crystal silicon layer to form a diffused layer 11. The nitride film 4 and the oxide film 3 on the base are removed by a self-alignment method using as a mask the polycrystalline silicon layer 9 and the oxide film layer 10 surrounding the former, to open a window 12 for leading out a base terminal. Thereby, thin oxide and nitride films 3 and 4 are left in some parts between the layer 9 and the base silicon layer 2, preventing a poor junction or short-circuit between the base and emitter. Ions are implanted to form a graft base 13, and an electrode metal 14 is deposited thereon and patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device manufactured using a self-alignment technique (self-alignment method) and a manufacturing method thereof.

In the field of digital circuits, there is a strong demand for faster integrated circuits and higher integration density. It is a well-known fact that higher speed and higher integration density have the same technical content, and that speed is also improved as junction capacitance and diffusion capacitance are reduced by miniaturization of elements.

Therefore, technological developments regarding miniaturization of device structures such as bipolar (MOS) and transistor (MOS) devices are being carried out in various places.

It goes without saying that the direct technology that contributes to the miniaturization of device structures is the lithography technique used when forming device patterns. However, with the rapid trend toward finer patterns in recent years, it has become difficult to form ultra-fine patterns using conventional exposure techniques using light.

An exposure technology that uses electron beams has been proposed as an alternative to light exposure technology, and although this technology enables pattern formation of 1 μm or less, electron beam exposure technology is a processing technology for each element pattern. However, the processing speed is significantly slower than the conventional optical exposure technology that processes each semiconductor wafer. The element pattern formation process (photoresist process) is performed every time in the entire semiconductor manufacturing process, prior to the etching/diffusion process, etc., so the slow processing time in the photoresist process will reduce the time it takes to complete all processes in semiconductor manufacturing. This means that it becomes significantly longer.

Another important point in miniaturizing elements is pattern alignment with the previous process in the photoresist process. In other words, in the next step, the next pattern is formed in accordance with the pattern formed in the previous step. In this case, there is a limit to the accuracy of etching technology, diffusion technology, etc. in the previous and next steps, and there is also a limit to the accuracy of pattern alignment, so there is a gap between the patterns in the previous and next steps. We need to provide some leeway. This margin is usually called a mask alignment margin, and is required to be at least 1 μm or more. The mask margin between the successive previous process and the next process has the above-mentioned value, but the mask margin between the consecutive processes becomes even larger because it becomes an accumulation of the mask margins.

As described above, it is becoming difficult to miniaturize elements simply by relying on conventional exposure techniques. In addition to the above-mentioned exposure technique, there is a self-alignment technique as an effective means for miniaturization. This technique does not form a pattern using a mask, but rather uses the pattern itself formed on the semiconductor wafer in the previous process as a mask to perform the next process. Therefore, since the present technique does not require a mask, the above-mentioned mask margin is not required, and it is possible to form fine elements using conventional light exposure techniques.

The present invention provides a fine device structure and manufacturing method using the above-mentioned self-alignment technology. Prior to explaining the present invention, the prior art and one problem thereof will be explained. In order to simplify the explanation and the drawings, the conductivity type of each semiconductor layer and the material of each part are specified, and the description of the structure of the layer that is not directly related to the present invention is omitted (hereinafter, 1. The same applies to the explanation).

Figure 1 shows a cross section of a 2L element with a conventional Selfaline structure (References: IEEE, TRANSACT-
LON8 ON ED, VOL, ED-27, No
, 8. August 1980. ).

In the figure, 1 is an n-type semiconductor (silicon) substrate, 2 is an n-type semiconductor (silicon) substrate, and 2 is an n-type semiconductor (silicon) substrate.
type semiconductor (silicon) layer, 5 is a silicon oxide film (hereinafter referred to as
It is written as an oxide film. ), 9 is a polycrystalline silicon layer, 10 is a silicon oxide film layer (hereinafter referred to as an oxide film layer), 11 is an n-type semiconductor region (diffusion layer), 16 is a high concentration n-type semiconductor layer (diffusion layer), 14 is gold for electrode (metal electrode).

In the I2L having the structure shown in FIG. 1, the collector electrode is taken out by the polycrystalline silicon layer 9, and the base electrode is taken out by the metal 14. In this structure, in order to take out the base electrode from very close to the collector terminal for the purpose of reducing the base resistance, a self-alignment method is used using the polycrystalline silicon layer 9, which will become the collector terminal, and the oxide film layer 1° attached thereto as a mask. A hole for a base terminal is made and a metal electrode 14 is attached thereto. The self-alignment hole drilling described above is performed in the following steps.

A polycrystalline silicon layer is deposited on the silicon layer 2 exposed on the surface, and this polycrystalline silicon layer is impregnated with a high concentration of impurities and then patterned to form a polycrystalline silicon layer as shown in FIG. Form layer 9. When oxidation is performed after this, a thick oxide film layer 1o is formed on the polycrystalline silicon layer containing high concentration impurities, and a thin oxide film is formed on the low concentration silicon layer 2. Therefore, if etching is performed under the condition that the thin oxide film is completely removed from this state and the thick oxide film remains, it is possible to form a hole for the base electrode in the self-line.

In such a conventional structure, the following problem occurs at the portion ioo shown in FIG.

First, it is difficult to form the oxide film layer 10 to an arbitrary thickness. In other words, when oxidizing a highly-concentrated polycrystalline layer and a lightly-concentrated silicon layer, it is difficult to create a significant difference in the thickness of the oxide film between the two. Further, since the entire surface is etched after oxidation, the oxide film layer 10 is etched at the same time as the oxide film on the silicon and becomes thin. This increases the possibility that polycrystalline silicon layer 9 and metal electrode 14 will be short-circuited.

Next, the distance between the metal electrode 14 and the polycrystalline silicon layer 9 or the diffusion layer 11 is determined only by the thickness of the oxide film layer 10. The thickness of the oxide film layer 10 is usually at most 1000A~
5000A, and the diffusion layer 11 extends downward and also in the lateral direction (the depth of the diffusion layer is set to 6000~
If it is about 5000A, the horizontal elongation is 2400~4
000 A), there is a very high risk that the metal electrode 14 and the diffusion layer 11 will be short-circuited.

Furthermore, since the distance between the high-concentration diffusion layers 15 and 11 cannot be arbitrarily designed, there is a high possibility that breakdown voltage deterioration will occur due to high-concentration diffusion.

As described above, the conventional invention has various problems, and these problems lead to fatal defects in the integrated circuit.

The present invention provides a structure and manufacturing method that can eliminate these problems. According to the technology of the present invention, a normal bipolar transistor and a 2L element (In
integrated injection logic
) can be easily formed on the same substrate, making it analog.

It becomes possible to configure digital coexistence integrated circuits with high integration density.

In order to achieve the above object, the main parts of the semiconductor device of the present invention have the following configuration. That is, a silicon oxide film (Sin) and a silicon nitride film (Si, N4
), and the two layers surrounding the polycrystalline silicon layer are insulated using a self-alignment method using the polycrystalline silicon layer and the surrounding silicon oxide film layer as masks. A metal electrode is provided in a window hole formed in at least a portion of the window.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 shows the first embodiment of the present invention, in order of main manufacturing steps (a
) to (f) are structural cross-sectional views of the semiconductor device of the present invention. This will be explained step by step in correspondence with the diagram. Note that this embodiment relates to an npn transistor with a vertical structure. In the figures, the same reference numerals as those above refer to the same numbers.
or equivalent parts shall be indicated.

(a): 1 is an n-type semiconductor (silicon) substrate, 2 is npn
) An n-type semiconductor (silicon) layer for forming the base portion of the transistor, 6 is a thin (for example, about 500A thick) silicon oxide film (hereinafter referred to as oxide film), 4 and 6 are silicon nitride films (hereinafter referred to as oxide film). , nitride film), 5 is thick (
For example, it is an oxide film (with a thickness of about 1 μm). The n-type semiconductor substrate 1 is formed on an n-type semiconductor substrate (not shown) on an integrated circuit.

A heavily doped n-type buried layer and an element isolation layer (none of which are shown) are also required to lower the collector resistance, but as described above, these are omitted for the sake of simplifying the drawings and explanation. Note that although the figure shows the case where the nitride film 4°6 is partially present, the case is different when the nitride film used as a mask material is also used in a later process when forming the thick oxide film 5. As an example, if the thickness of the nitride film 4.6 is to be precisely controlled, it is also possible to once remove the nitride film used for selective oxidation and then form a new nitride film.

In this case, the nitride film 4.6 in FIG. 2(a) is formed over the entire surface.

(b) A portion (window hole) 7 of the oxide film 3 and nitride films 4 and 6 that will become the emitter and collector of a transistor in the future is removed (opened).

(C): After the window opening, a polycrystalline silicon layer is formed on the entire surface, and an n-type impurity is introduced into the polycrystalline silicon layer, followed by pattern formation. In the figure, 8°9 is the polycrystalline silicon layer, 8 is the part that will become the collector in the future, and 9 is the part that will become the collector in the future.
is the part that becomes the emitter terminal. The pattern of the portion that will become the emitter terminal here is formed larger than the emitter window hole 7 in (b) so that the underlying silicon layer is not exposed to the surface.

(d): After the step (c), polycrystalline silicon layer 8
Oxidize ゜9. 10 in the figure is an oxide film layer formed by oxidizing polycrystalline silicon. The first feature of the present invention is this step. In other words, in this step, the silicon layers other than the polycrystalline silicon that will become the emitter or collector are covered with the nitride film 4, so no oxide film grows due to oxidation in this step, and only the polycrystalline silicon layers 8 and 9 are covered. can be selectively oxidized. The oxide film layer 10 of the polycrystalline silicon layer is formed here to be thicker than the underlying oxide film (for example, about 2000 to 5000 λ in thickness). Also, many.

During the oxidation of crystalline silicon, n-type impurities introduced in advance from the polycrystalline silicon layer diffuse into the single-crystal silicon layer (p-type semiconductor layer 2 and n-type semiconductor substrate 1), forming a diffusion layer (n+ semiconductor layer) 11 (emitter and collector). ) is formed.

Here, we have described a manufacturing method in which a polycrystalline silicon layer is deposited after forming a hole in step (b), but after step (b), an n-type semiconductor region that will become an emitter is formed through the window hole by diffusion or ion implantation. In order to form a polycrystalline silicon layer, step C') of depositing a polycrystalline silicon layer may be performed.

(e) 2 The nitride film 4 and oxide film 3 on the base (p-type semiconductor layer 2) are removed, and a window hole 12 for extracting the base terminal is opened. This step has the second feature of the present invention. That is, in this step, the nitride film 4 on the base is formed using a self-alignment method using the polycrystalline silicon layer 9 that will become the emitter and the oxide film layer 10 surrounding it as a mask. It becomes possible to remove the oxide film 3. Since the oxide film 6 on the base is sufficiently thinner than the oxide film layer 10 of the polycrystalline silicon layer, the nitride film and oxide film on the base can be removed without removing the oxide film layer 10. At this time, a thin oxide film 6. A nitride film 4 remains. As will be described later, the remaining oxide film and nitride film play an important role in maintaining a proper distance between the emitter and the base and preventing base-emitter junction defects and short circuit defects.

(f): High concentration boron is diffused or ion implanted through the window hole 12 from which the nitride film and oxide film have been removed to form a graft base (high concentration p-type semiconductor layer) 1! Form I. Thereafter, electrode metal 14 is deposited and patterned.

Through the above steps, a vertically structured npn (npn) transistor (in the figure, it is a multi-emitter transistor) is completed.

In the case of this embodiment, as can be seen from FIGS. 2(e) and 2(f), there is no need for a mask for opening the contact hole (window hole 12) for extracting the base terminal. Further, the base terminal can be taken out from the periphery immediately adjacent to the emitter, and the transistor is entirely covered with the metal electrode 14.

Next, the features and advantages of the npn) transistor structure of the present invention shown in FIG. 1(f) will be explained.

In this structure, the base terminal and emitter terminal can be drawn out using a self-alignment method without taking mask margins. Therefore, the base electrode can be formed near the emitter electrode. The base electrode is drawn out from several points around the emitter, and these points are connected by metal electrodes. All of these features mean that it is possible to significantly reduce base series resistance, which is an impediment to high-speed operation of transistors. In particular, in conventional multi-emitter transistors, the speed of the emitter located far from the base terminal was extremely low due to the series resistance of the base, but in the structure of the present invention, the metal electrode is formed on the entire surface of the base. In addition, multiple emitter transistors can all operate at the same speed.

This structure is similar to the extraction of metal electrodes from the base.
A highly concentrated p shadow region for the base (16) can be formed between the emitter region and the emitter region in a self-aligned manner. This has a significant effect on reducing the base resistance as described above.

As mentioned above, the fact that the base and emitter can be formed using a self-alignment method means that there is no need for mask alignment.
Fine elements can be easily formed.

In this structure, the emitter is formed of polycrystalline silicon, so
npn) In the case of a transistor, the conductivity type is n type. As is well known, the layer resistance of an n-type polycrystalline silicon layer can be made to have a much lower resistance value than that of a p-type layer. Therefore, in a transistor that uses a polycrystalline silicon layer for the emitter like this structure, this layer is
It has the advantage that it can be used as an under wiring. In a transistor using a polycrystalline silicon layer as a base, the conductivity type of the polycrystalline layer is p-type, so the resistance value cannot be lowered, and it is difficult to use it for cross wiring. The fact that a polycrystalline silicon layer can be used for cross wiring as in the present invention has an important meaning in constructing an integrated circuit. Generally, as the scale of an integrated circuit increases, the wiring area in the integrated circuit rapidly increases and occupies a much larger area than the element area. In such a case, the effect of the polycrystalline silicon layer of the present invention (furthermore, this polycrystalline silicon layer is not specially formed for wiring (it can be formed at the same time as emitter formation) becomes noticeable, As mentioned above, problems with the conventional technology include base-emitter junction defects and short-circuit defects, which can play a major role in reducing the area of integrated circuits.This is because the base and emitter are formed using a self-aligned method. Contact between the high-concentration semiconductor layers of the base and emitter causes a bonding failure.Also, if the base terminal exit hole and the emitter layer are too close together, the metal for the base terminal becomes too close to each other due to lateral diffusion of the emitter semiconductor layer. was often short-circuited to the emitter.In the present invention, as shown in Fig. 1(e)
, (f), the distance between the emitter and base electrodes is properly maintained by the nitride film 4 and the oxide film layer, so that defects unlike conventional self-aligned transistors do not occur.

Furthermore, in the present invention, it is of course unnecessary to provide a separate contact hole for taking out the emitter terminal.

Next, we will discuss the process features.

In the present invention, the nitride film 4 is left on the base as shown in FIG. 2, and is used to prevent the terminal lead-out portion on the base from being oxidized when the polycrystalline silicon layer for the emitter is oxidized. Preventing.

Furthermore, a mask is used for patterning and forming the polycrystalline silicon layer for the emitter. At this time, the emitter diffusion window (portion 7 in FIG. 2(b)) should also be patterned to be slightly thicker.

This provides a diffusion margin between the base and emitter later.

FIGS. 6(a) to 6(d) are diagrams showing the second embodiment of the present invention in order of steps. In this embodiment, the horizontal p
This relates to np transistors. Note that FIG. 6 shows the process starting from the step corresponding to (d) in FIG. 2.

First, the manufacturing method will be described in order of steps.

(a): In the npn) transistor, a window for the emitter was opened in the step shown in FIG. Leave it behind, pattern it, and oxidize it to form oxide film layer 1.
form 0. Further, no p-type semiconductor layer is formed under the nitride film 4° oxide film 6.

(b) This step is the same as the graft base formation for npn). polycrystalline silicon layer 9
and a nitride film 4. using the oxide film layer 1o as a self-alignment mask.
After removing the oxide film 6, a highly concentrated p-type semiconductor layer (diffusion layer) 16 is formed.
form.

(C): A metal electrode 14 for terminal extraction is formed.

Through the above steps, a horizontal pnp transistor is constructed.

The lateral pnp transistor leaves the polycrystalline silicon layer 9 floating/low, but provides a specific potential.

Particularly when the metal electrode 14 on the emitter side of the lateral pnp transistor is connected to the polycrystalline silicon layer 9, this is effective in preventing parasitic channels. The configuration in this case is shown in Figure 3 (
d).

(d): The metal electrode 14 and the polycrystalline silicon layer 9 were connected at the part (connection part) shown by 16 in the figure. In this way, the structure can be easily configured without increasing the element area.

FIGS. 4(a) to 4(C) are diagrams showing the third embodiment of the present invention in the order of steps. This embodiment, like the second embodiment (FIG. 3), relates to a horizontal 1)np) transistor. The steps will be explained below in order.

(a) - Nitride film 4. A p-type semiconductor layer 2, which is the same as the intrinsic base of the npn transistor, is formed under the oxide film layer as shown in the figure. Next, a polycrystalline silicon layer 9 is formed so as to straddle the two p-type semiconductor layers 2, and is oxidized to form an oxide film layer 10.

(b): Similar to the step of forming the graft base of npn) transistor, polycrystalline silicon layer 9 and oxide film layer 1 are formed.
Perform high concentration p-type diffusion using 0 as a self-aligned mask,
A heavily doped p-type semiconductor layer 16 is formed.

(C): Finally, the metal electrode 14 is formed.

The features of this structure are as follows.

In this structure, the base width of the pnp transistor can be shortened. In the structure of Fig. 3, the emitter,
Since the collector is formed of a highly doped deep p-type semiconductor layer, the base width cannot be shortened. Also, since the metal/electrode 14 of the emitter and collector needs to cover the extraction window, the base width is the distance between the metal electrodes (1).
It cannot be made smaller. On the other hand, in the structure of FIG. 4 of the present invention, the base width can be determined by the shallow p-type semiconductor layer 2 with a low concentration, so that the base width can be made small. In this embodiment, the distance between metal electrodes <1) can be maintained by the polycrystalline silicon layer 9. As a result, the performance of the pnp (pnp) transistor of this embodiment can be significantly improved.

FIGS. 5(a) to 5(C) are diagrams showing the fourth embodiment of the present invention in order of steps. Although this embodiment also relates to a horizontal pnp (pnp) transistor, it has a structure with higher performance than that of the sixth embodiment (FIG. 4). The steps will be explained below in order.

(a): Nitride film 4. Under the oxide film 6 is a low concentration shallow p-type semiconductor layer 2 which becomes the intrinsic base of the npn) transistor.
Form it. Next, after patterning the polycrystalline silicon layer 9, it is oxidized to form an oxide film layer 10. Next, use photoresist 17 or the like as a mask.

Nitride film at part 18 (window hole) in the figure 4. The oxide film 6 is removed to form a window hole. At this time, the nitride film 4. Oxide film 6 is removed by a self-alignment method using polycrystalline silicon layer 9 as a mask. In this state, n-type impurity ions are implanted, or after the photoresist is removed, n-type impurity is diffused.

In this case, the masks for actual ion implantation and diffusion are not the photoresist film but the polycrystalline silicon layer 9 and the thick oxide film 5, so there is no need for precision alignment of the masks used, and the self-alignment method It has become.

(b): The other nitride film 4° without the polycrystalline silicon layer 9 and the oxide film 3 are removed to form a highly concentrated deep p-type semiconductor layer 13.
13' is formed. This high concentration p-type semiconductor layer 15.13
' is npn) It is also possible to form the graft base of the transistor at the same time. Nitride film 4 at this time. Needless to say, the oxide film 6 is removed by the self-alignment method. Further, the p-type semiconductor layer 16 in the portion where the n-type semiconductor layer 19 is formed and another p-type semiconductor layer 16' are formed simultaneously.

(C): Finally, attach the metal electrode 14.

The features of this embodiment will be described below.

In the structure of this embodiment, the p-type semiconductor layer 13 is used as an emitter, and 16' is used as a collector. In this case, since the n-type semiconductor layer 19 and the p-type semiconductor layer 15 are double-diffused 20, it is possible to form the base width to sub-micron precision with high accuracy. In particular, in the case of a pnp transistor, since the n-type semiconductor layer 19 serving as the base layer has a concentration gradient from the emitter to the collector, it becomes a high-speed, high-performance transistor with a high current amplification factor.

FIGS. 6(a) and 6(b) are diagrams showing the fifth embodiment of the present invention in the order of steps. This embodiment relates to a Schottky diode. The steps will be explained below in order.

(a): The process is the same as that of forming the emitter and collector of a pnp transistor. However, the p-type semiconductor layer 13 is formed so as to surround the polycrystalline silicon layer 9.

(b): Oxide film layer 10. Polycrystalline silicon layer9. Nitride film 4. The oxide film 6 is removed and a metal electrode 14 is attached to the entire surface.

The features of this embodiment will be described below.

In the conventional Schottky diode with guard ring,
Since the guard ring was formed using a mask, the area of the Schottky diode became very large.

To form the structure of an embodiment of the invention, a guard ring (
- Since the p-type semiconductor layer 13) can be formed by a self-alignment method,
A guard ring with a narrow width can be easily formed, and a Schmittkey diode with a small area can be formed. FIG. 7 is a diagram showing a sixth embodiment of the present invention.

This embodiment relates to resistance. That is, FIG. 7 shows a cross-sectional view of the structure of a resistor that can be formed simultaneously with the npn transistor of the present invention. For this resistor, npn
) A shallow, low-concentration p-type semiconductor layer 2 used as an intrinsic paste of a transistor is used as a resistor.

The length of the resistor is determined by the polycrystalline silicon layer 9.

The holes for taking out both terminals of the resistor are determined in a self-aligned manner by the polycrystalline silicon layer 9, as in the case of a transistor.
A high-concentration 1p type semiconductor layer 16 is formed here, and at the same time, a terminal is extracted from the same extraction hole by means of a metal electrode 14.

In the case of this embodiment, it is the p-type semiconductor layer 2 that determines the actual resistance value, and the p-type semiconductor layer 13 provides good low-resistance ohmic contact between the metal electrode and the semiconductor layer. used to obtain In the case of the p-type semiconductor layer 2 used as the intrinsic paste, a shallow junction is formed with a low concentration, so in this embodiment, it is possible to easily obtain a high resistance that is difficult to realize in an integrated circuit.

The resistor of this embodiment also has advantages not found in conventional resistors. In many conventional integrated circuit resistors, different masks were used for forming a semiconductor region to serve as a resistor layer and for making holes for taking out electrodes. For this reason, it is necessary to provide a margin between the two masks above for mask alignment.
The area of the semiconductor layer must always be designed to be larger than the metal electrode extraction hole, and as a result, the resistance value usually deviates from the designed value due to the current sinking effect from the semiconductor layer surrounding the metal electrode extraction hole. Met.

In the embodiment of the present invention, the electrode extraction hole is formed in the underlying semiconductor layer 1.
3 and by a self-alignment method, it is possible to minimize the current looping effect at the end of the metal electrode, making it easy to design a precise resistor.

FIG. 8 is a diagram showing a seventh embodiment of the present invention.

This embodiment relates to capacitance, and describes three structures (a), (b), and (C) of integrated capacitance.

FIG. 8(a) shows a structure of capacitance between a polycrystalline silicon layer 9 and a semiconductor layer (semiconductor substrate 1) through an insulating film (nitride film 4, oxide film 6).

According to the present invention, a capacitance via an insulating film can also be easily formed as shown in the figure. Since the dielectric constant of the nitride film 4 is about twice as large as that of the oxide film, it has the advantage that a large capacitance value can be obtained with a small area.

FIG. 8(b) shows a capacitance structure between the polycrystalline silicon layer 9 and the semiconductor layer (silicon layer 2) via an insulating film (nitride film 4, oxide film 3).

The features and advantages of this structure are the same as those of FIG. 8(a), but by using a semiconductor layer (silicon layer 2), the loss resistance of the capacitance on one electrode side is reduced. In addition, in the structure of FIG. 8(a), since the n-type semiconductor substrate 1 is used as one electrode, if a large number of capacitors are required, each capacitor must be separated by a separation layer, which reduces the area. This increases the parasitic capacitance between the thick substrate and the underlying p-type substrate (not shown).
)], since the p-type semiconductor layer 2 is used as one electrode, there is no problem as described above, and the parasitic capacitance is
and only the junction capacitance of the n-type semiconductor substrate 1. Since the impurity concentration of the p-type semiconductor layer 2 is low, this parasitic capacitance can also be kept low.

In addition to the structure shown in FIG. 8(b), FIG. 8(C) shows a capacitance structure with an oxide film layer 10 between the polycrystalline silicon layer 9 and the metal electrode 140. In this way, it is possible to obtain a larger capacity even with the same area.

In the above embodiment, an example was described in which the nitride film 4 and the oxide film 5 were used as the insulating film of the capacitor, but the nitride film 4 in the capacitor part was removed and the capacitor had an insulating film of only the thin oxide film 3. Needless to say, it is easy to obtain.

FIG. 9 is a diagram showing an eighth embodiment of the present invention.

This example concerns I2L, and includes six structures (a) (
Let us now discuss b) and (C).

By combining the npn transistor shown in the embodiment of FIG. 2 with the pn9) transistor shown in the embodiment of FIGS. 3, 4, and 5,
The 2L structure shown in c) can be easily obtained.

■ In the case of the 2L structure shown in this example, Figs.
upn) transistor pnp mentioned in the embodiment shown in the figure
) It goes without saying that the advantages of the transistor apply as is. In addition, the 2La structure of this embodiment has the following particularly important advantages.

(2) In the 2L structure, the npn transistor uses the upper n-type semiconductor region 11 as a collector. In this way, transistors used in the reverse mode generally have a low current amplification factor. This means that among the electrons injected from the emitter region (substrate 1) to the p-shade region of the base, only the electrons injected from directly below the collector region (11) reach the collector and become a collector current, and are injected from other parts. This is because every single electron generated becomes base current. Therefore, in order to increase the current amplification factor of the transistor used in the reverse mode, the collector region (11) and the base region (p-type semiconductor layer 216)
It is necessary to make the area ratio as close to 1 as possible. It is also necessary to increase the concentration of the base region other than directly below the collector region to reduce the injection of electrons into this region.

In the case of this embodiment, since the base terminal can be taken out by a self-alignment method, it is possible to significantly reduce the area of the base region other than the coherent region. Furthermore, since high concentration (7)p shadow regions are formed in all base terminal lead-out portions, it is possible to increase the current amplification factor of the npn transistor.

Further, the construction 2L is a one-manpower, multi-output logic circuit, and requires a large number of collector terminals. ■When a conventional 2L structure has a large number of collector outputs, the effect of the series resistance of the base causes the sink current of the collector located far from the pnp transistor to drop significantly at large currents, resulting in an extremely slow operating speed. As described above, especially in the 2L, the high series resistance of the base has a very negative effect on operating margin and operating speed.

2L of the structure of this example, as shown in Fig. 9, the base terminal is taken out from the vicinity of each collector by means of metal electrodes, so the series resistance of the base is so low that it can be ignored. Differences in characteristics due to differences in position are eliminated.This eliminates the difference in characteristics due to positional differences.
In contrast to the fact that the speed of L was limited by the slowest operating collector, the present invention allows all collectors to operate at the same high speed, making it possible to further increase the operating speed of the integrated circuit. It means something.

In the case of I2L of this embodiment, since polycrystalline silicon is used to extract the number of collector terminals, compared to the case where polycrystalline silicon is used to extract the paste terminals, the polycrystalline silicon layer can be extended beyond the adjacent gate. It can be used as a wiring layer for wiring.

This provides a large degree of freedom in layout design when considering the design of integrated circuits including wiring, and is also very effective in reducing chip area.

FIG. 10 is a diagram showing a ninth embodiment of the present invention.

In this embodiment, the structure of a Schottky clamp transistor which is a combination of the npn (npn) transistor described in FIG. 2 and the Schottky diode described in FIG. 6 will be described.

FIG. 10(a) is a cross-sectional view of the structure of a Schottky clamp transistor, and L(b) is its circuit.

As can be seen from the structural cross-sectional view, it can be seen that this transistor can be easily formed by combining the transistor shown in FIG. 2 and the Schottky diode shown in FIG. 6. 10th
In Figure (a), the junction 2o is a Schottky diode made of metal 14 and silicon. Needless to say, the advantages of this structure are the same as those described in the embodiments of FIGS. 2 and 6.

Although the advantages of the present invention have been described above with reference to a number of embodiments, the scope of the present invention is not limited to only the forms shown in the embodiments, and the present invention also includes numerous modifications of the embodiments. Needless to say, it is included in

For example, it goes without saying that the present invention can be applied even if the conductivity types of the semiconductor layers shown in the embodiments are switched between p-type and n-type.

Further, it goes without saying that a structure in which some of the embodiments shown in the present invention are combined is also included within the scope of the present invention. Furthermore, in the embodiments of the present invention, illustrations of the p-type substrate and the n-type semiconductor buried layer, which are commonly used in integrated circuits, are omitted; however, as mentioned above, this is done in order to clearly illustrate the main points of the present invention. It goes without saying that structures including these p-type substrates and n-type semiconductor buried layers are also included in the present invention.

Summary: Embodiments of a semiconductor device and its manufacturing method according to the present invention are shown below.

■ In an npn transistor with a vertical structure, the base region has a lightly doped n-type semiconductor region 2 and a highly doped n-type semiconductor region 16, and at least one emitter region is provided in the lightly doped n-type semiconductor region 2. On the emitter region, there is a polycrystalline silicon layer 9 covering the emitter region hole for taking out the emitter terminal, and a portion of the polycrystalline silicon layer 9 that is larger than the emitter region hole and the underlying base region. There is a nitride film 4 and a thin oxide film 6 between them, the polycrystalline silicon layer 9 is covered with an oxide film layer 10, the base terminal is taken out from the high concentration p-type semiconductor layer 13 by a metal electrode 14, and the metal electrode Reference numeral 14 denotes a semiconductor device (see FIG. 2) characterized in that it has a structure in which wiring is provided on the polycrystalline silicon layer 9 for the emitter electrode via an oxide film layer 10.
.

■ In the semiconductor device described in ■ above, a horizontal PNP transistor that can be formed on the same substrate in the same process as the semiconductor device described above.
and a nitride film 4, and on the nitride film 4 there is a polycrystalline silicon layer 9 covered with an oxide film layer 10 having the same width as the polycrystalline silicon layer 9, and the emitter and collector regions are n-type semiconductor regions (13 or 2), and has a structure in which the metal electrode 14 is extracted from the n-type semiconductor region (see Figure 3.4.5).

(2) A semiconductor device as described in (1) above, characterized in that the n-type semiconductor region is a highly doped p-type semiconductor layer (see FIG. 6).

■ In the semiconductor device described in ■ above, the n-type semiconductor region has a composite structure of a low-concentration p-type semiconductor layer (region) and a high-concentration p-type semiconductor layer (region), and between the low-concentration n-type semiconductor regions A semiconductor device (see FIG. 4) characterized in that the distance is shorter than the distance between high concentration n-type semiconductor regions and the width of the polycrystalline silicon layer is also shorter.

■ In the semiconductor device described in ■ above, the base region and the emitter region are formed by diffusion or ion implantation through the same window hole, and the emitter region of the n-type semiconductor region is a highly doped n-type semiconductor region, and the collector region is a high concentration n-type semiconductor region. A semiconductor device (see FIG. 5) characterized in that it has a composite structure of low concentration and high concentration n-type semiconductor regions, and the low concentration n-type semiconductor region is closer to the emitter than the high concentration n-type semiconductor region.

■ As a resistance element that can be formed in the same process and on the same substrate as the semiconductor device described in ■ above, the low concentration n-type semiconductor region 2 and the high concentration n-type semiconductor region 16 are used in the resistance part, and the low concentration n-type semiconductor region 2 is formed on the low concentration n-type semiconductor region 2. The oxide film 6 and the nitride film 4 have the same length.
, and on the nitride film 4 there is a polycrystalline silicon layer 9 covered with an oxide film layer 10 having the same length as the nitride film.
A semiconductor device characterized in that it has a structure in which a metal electrode 14 is taken out from the entire surface of a shaped semiconductor region 15 (see FIG. 7).

■ As a capacitive element that can be formed in the same process and on the same substrate as the semiconductor device described in ■ above, a nitride film 4 and an oxide film 3 are used as an insulating film.
Alternatively, it has an oxide film, one electrode is a polycrystalline silicon layer 9, and the other electrode is an n-type semiconductor region (substrate 1) or a low concentration n-type semiconductor region 2 and a high concentration n-type semiconductor region 13,
Alternatively, a semiconductor device characterized by having a structure in which a metal electrode 14 is used (see FIG. 8).

(2) A semiconductor device having a structure in which the high concentration n-type semiconductor region 13 is used as a guard ring and the Schottky junction between the metal electrode 14 and the n-type semiconductor region (substrate 1) is used as a diode (see FIG. 6).

(2) A semiconductor device having a structure that combines the semiconductor device described above and the semiconductor device described in (2) (see FIG. 10).

[Phase] A semiconductor device characterized by having a 2L structure (see FIG. 9) in which the semiconductor device described in (1) above and the semiconductor devices described in (1) to (2) are integrated into one.

■ In the method for manufacturing a semiconductor device described in (1) to [phase] above, the emitter or collector of an NPN transistor is formed by forming a thin oxide film and a nitride film on the oxide film by opening a window 10, and then depositing a polycrystalline silicon layer. , and pnT) transistor, a polycrystalline silicon layer is deposited on the resistor without removing the oxide film and nitride film, and the window hole portion of the emitter or collector or both of the n'pn) transistor is covered. After patterning is performed to expose the nitride film underlying the polycrystalline silicon/layer, oxidation is performed. After removing the thin oxide film and nitride film, the external base region of the npn transistor, the emitter and collector region of the pnp transistor, and the electrode extraction region of the resistor are formed using a high concentration n-type semiconductor layer, and then metal is deposited. 1. A method for manufacturing a semiconductor device, characterized in that the base-x terminals of an npn) transistor, the emitter and collector terminals of a pnp transistor, and both terminals of a resistor are taken out in a self-aligned manner by forming a pattern.

(PNP described in 0 above) In the method for manufacturing a transistor, a low concentration is uniformly applied between the emitter and the collector before forming the high concentration n-type semiconductor region.

A type semiconductor region is formed in advance, and the collector region is masked so that the portion that will become the emitter is determined in a self-aligned manner using an oxidized polycrystalline silicon layer, and an n-type semiconductor region is formed from the region that will become the emitter. A method for manufacturing a semiconductor device 0, characterized in that after removing a mask material, a high concentration n-type semiconductor layer is formed to form an emitter and a collector of a PNP transistor. A manufacturing method comprising a step of forming a highly doped n-type semiconductor region using a polycrystalline silicon layer as a mask, then removing the polycrystalline silicon layer, a nitride film thereunder, and a thin oxide film, and depositing a metal layer.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a conventional 2L element with a self-line structure, Fig. 2 (a) to (f) are structural cross-sectional views showing the order of manufacturing steps of the npn transistor of the present invention, and Fig. 3 (a) to (f).
(d), Figure 4 (a) to (c), Figure 5 (a) to
(C) is a structural sectional view showing the horizontal type 1)n+)) transistor of the present invention in the order of manufacturing process, and Fig. 6(a) to (
b) is a structural cross-sectional view showing the manufacturing process order of the Schottky diode of the present invention, FIG. 7 is a structural cross-sectional view of the resistor of the present invention, and FIGS. Structural sectional views of the capacitor of the invention, FIGS. 9(a), (b) and (
C) is a structural cross-sectional view of T2I of the present invention, No. 10, respectively.
Figure (a) is a cross-sectional view of the structure of the Schottky clamp transistor of the present invention, and figure (b) is its circuit. 1... N-type semiconductor substrate (substrate) 2... N-type semiconductor layer (silicon layer) 5... Silicon oxide film (oxide film) 4.6... Silicon nitride film (nitride film) 5...・Silicon oxide film (oxide film) 7.12.18...Window hole 8.9...Polycrystalline silicon layer 10...Silicon oxide film layer (oxide film layer) 11...n
shaped semiconductor region (silicon layer, diffusion layer) 13.13'...
・High concentration n-type semiconductor layer (high concentration diffusion layer) 14...Metal (metal electrode) 15...Collector portion of transistor 16...Connection portion 17...Photoresist 19...N-type semiconductor layer 20・・・Joining Part Agent Patent Attorney Tsuginosuke Nakamura 11 Figure 1'2 (.) (d) 1-2 Figure 1jZ ll II Ij 5 Figure 16 (Q) 1-7 Figure 8 (Q ) 131 1'9 figure (Q) 1 so Z l;j I
Figure II1-10 (Q) (b) Continued from page 1 0 Inventor Setsuo Ogura 111 Nishiyokotecho, Takasaki City, Hitachi, Ltd. Takasaki Factory 0 Inventor Takahiro Okabe 280 Higashi Koigakubo-chome, Kokubunji City Stock Company Hitachi, Ltd. Central Research Laboratory 0 Inventor: Jo Nagata 280 Higashikoigakubo-chome, Kokubunji City, Hitachi, Ltd. Central Research Laboratory

Claims (2)

[Claims] (1) An insulating film consisting of two layers of a silicon oxide film and a silicon nitride film is provided at least in part between the silicon layer and the polycrystalline silicon layer provided at a predetermined location on the surface of the substrate including the silicon layer, and Formed by removing at least a portion of the two layers of insulating film around the polycrystalline silicon layer using a self-alignment method using a polycrystalline silicon layer and a silicon oxide film layer surrounding the polycrystalline silicon layer as a mask. A semiconductor device characterized in that a metal electrode is provided in a window hole. (2) forming a silicon oxide film on the substrate surface; forming a silicon nitride film on the silicon oxide film;
A process of making a window hole in the two-layer insulating film of silicon nitride film and silicon oxide film formed by the above two steps, and after making the window hole, a polycrystalline silicon layer is deposited to cover the window hole part and patterned. a step of oxidizing the polycrystalline silicon layer to form a silicon oxide film layer surrounding it; and a self-alignment method using the polycrystalline silicon layer and the surrounding silicon oxide film layer as masks. A method for controlling a semiconductor device, comprising the steps of: forming a window in the two peripheral insulating films; and providing a metal electrode in the window hole formed in the step.