JPH0143468B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a complementary insulated gate field effect transistor having an N-channel and a P-channel insulated gate field effect transistor integrally.

Conventionally, a complementary insulated gate field effect transistor using a so-called silicon gate has a P-type transistor on one main surface of an N-type semiconductor substrate 1, as shown in FIG.
A type semiconductor island region 2 is provided, and within this island region 2, N
A gate electrode 6 is formed on a gate insulating layer 5 of SiO ₂ or the like by diffusion forming a source region 3 and a drain region 4 of the mold.
A source electrode 7 and a drain electrode 8 are formed of an N-type polycrystalline silicon layer to constitute an N-channel insulated gate field effect transistor (N-MOS),
Further, a P-type source region 9 and a drain region 10 are formed by diffusion on the surface of the substrate 1, and a gate electrode 11, a source electrode 12, and a drain electrode 13 on the gate insulating layer 5 are formed of a P-type polycrystalline silicon layer. P channel insulated gate field effect transistor (P
- MOS), and is constructed by ohmicly connecting the connecting portions of the drain electrodes 8 and 13 of both transistors, which are made of polycrystalline silicon layers with mutually different conductivity types, with a metal layer 14 such as Al. . 15
and 16 are insulating layers such as SiO ₂ .

However, in such a configuration, a P-channel insulated gate field effect transistor (P-
Since the gate electrode 11 in the MOS) is formed from a P-type polycrystalline silicon layer in the process, there is instability in the gate of the P-channel insulated gate field effect transistor, and the P-type polycrystalline silicon layer is High performance is hindered by the fact that it is difficult to achieve low resistance with respect to the type polycrystalline silicon layer, and the metal layer 14 is formed on the connecting portion of both drain electrodes 8 and 13.
Because of the presence of aluminum, wiring using Al or the like cannot be done in and around that area, making it difficult to achieve high density. Furthermore, an N-type polycrystalline silicon layer and a P
When the polycrystalline silicon layers are simultaneously etched (plasma etched), there is a difference in etching speed between the P-type polycrystalline silicon layer and the N-type polycrystalline silicon layer due to the potential difference between them. Therefore, when patterning such a polycrystalline silicon layer, as shown in FIG.
8 and N-type polycrystalline silicon layer 19, that is, the connection portion between both drain electrodes 13 and 8, while the P-type polycrystalline silicon layer 18 is etched off with a mask width of _d1. There was a drawback that side etching of the N-type polycrystalline silicon layer 19 progressed, and the widths of both polycrystalline silicon layers 18 and 19 eventually became different from d ₁ and d ₂ , respectively.

The present invention provides a method for manufacturing such a complementary insulated gate field effect transistor, which improves the above-mentioned drawbacks and enables higher performance and higher density.

Hereinafter, a method for manufacturing a complementary insulated gate field effect transistor according to the present invention will be described in detail with reference to FIG.

First, as shown in FIG. 3A, a semiconductor island region 2 of a second conductivity type, that is, a P type, is formed on one main surface of a semiconductor substrate 1 of a first conductivity type, for example, a silicon semiconductor substrate 1 of an N type. An N-type source region 3 and a drain region 4 are formed by diffusion on the surface of the island region 2, a P-type source region 9 and a drain region 10 are formed on the surface of the substrate 1, and the respective source and drain regions 3 are formed by diffusion. and SiO ₂ between 4, 9 and 10
A gate insulating layer 5 is formed by etching. 16 is
It is an insulating layer such as SiO ₂ . Here, the impurity concentration near the surface of at least the portions of the P-type source region 9 and drain region 10 that are ohmicly connected to the polycrystalline silicon layer serving as electrodes is set to 10 ¹⁸ to 10 ¹⁹ atoms/cm ³ or more.

Next, the insulating layer 16 is photoetched to form each of the N-type source region 3 and drain region 4 and the P-type source region 9 and drain region 10.
window holes 21, 22, 23 and 2 for taking out the electrodes, respectively.
4 and then 10 ¹⁸ to 10 ¹⁹ atoms/cm ³ to the entire surface including each gate insulating layer 5 and each window hole 21 to 24.
A polycrystalline silicon layer 25 having an N-type impurity (eg, phosphorus) concentration of about 100% is deposited (FIGS. 3B and 3C). As will be clear from the discussion below, N is also present at the gate of the P channel insulated gate field effect transistor.
type using a polycrystalline silicon layer. Therefore, in this case, the N-type polycrystalline silicon layer 25 and the gate insulating layer
The impurity concentration near the interface of SiO ₂ 5 is 10 ¹⁸ ~
The threshold voltage may be lower than 10 ¹⁹ atoms/cm ³ or due to fluctuations in the work function difference due to variations in this concentration.
Since this causes variation in Vth, the N-type polycrystalline silicon layer needs to contain impurities of 10 ¹⁸ to 10 ¹⁹ atoms/cm ³ . Also, when depositing this N-type polycrystalline silicon layer 25, a P-type source region 9
In the drain region 10, since the P-type impurity concentration at the surface thereof is higher than the impurity concentration of the N-type polycrystalline silicon layer 25, a PN junction cannot be formed in the regions 9 and 10.

Next, at predetermined positions on the N-type polycrystalline silicon layer 25, that is, P-type source region 9 and drain region 1.
A SiO ₂ layer selectively doped with a P-type impurity, for example, borosilicate glass (BSG) 26, is formed at a position corresponding to the part where the electrode is drawn out from zero, and then a diffusion process is performed to remove N immediately below the borosilicate glass 26. The polycrystalline silicon layer 25 is converted into a P-type polycrystalline silicon layer 27 (FIG. 3D).

Next, after depositing a metal layer 28 such as Al, Pt, Mo, etc. on the entire surface including the N-type and P-type polycrystalline silicon layers 25 and 27 (FIG. 3E), a polycrystalline silicon layer is formed together with the metal layer 28. 25 and 27 are simultaneously selectively etched into a predetermined pattern, and a gate electrode 29 made of N-type polycrystalline silicon is formed on each gate insulating layer 5.
and 30, a source electrode 31 made of an N-type polycrystalline silicon layer in the N-type source region 3, a source electrode 32 made of a P-type polycrystalline silicon layer in the P-type source region 9, and between both drain regions 4 and 10. A drain connection wiring 33 is formed by forming the N-type polycrystalline silicon layer 25 and the P-type polycrystalline silicon layer 27 at the portions connected to the regions 4 and 10, respectively. When forming this drain connection wiring 33, N-type polycrystalline silicon layers 25 having different etching speeds are used.
The metal layer 28 deposited over the P-type polycrystalline silicon layer 27 electrically shoots both layers 25 and 27, eliminating the potential difference. By etching, both layers 25 and 27 are etched to the same width. By leaving the metal layer 28 even after etching, both layers 2
The ohmic connection between 5 and 27 is automatically made. Thereafter, the entire surface is covered with an insulating layer 34 of SiO ₂ or the like.

Thus, as shown in FIG. 3F, an N-channel insulated gate field effect transistor (N-MOS) having an N type source region 3 and drain region 4 is formed
and a P-channel insulated gate field effect transistor (P-MOS) having a P-type source region 9 and a drain region 10, and gate electrodes 29 and 30 of both transistors are both made of an N-type polycrystalline silicon layer. Furthermore, a P-type polycrystalline silicon layer is used for the ohmic connection between the source and drain regions 9 and 10 of the P-channel transistor (P-MOS), and the source and drain of the N-channel transistor (N-MOS). An N-type polycrystalline silicon layer is used for the ohmic connection between the regions 3 and 4, and the drain region 4 is connected to the drain region 4 in the drain connection wiring 33 made of the polycrystalline silicon layer that connects the drain regions 4 and 10 of both transistors. and 10, exhibiting N-type and P-type, and forming a metal layer 28 on at least the PN junction end of the silicon layer of the wiring 33 to achieve the desired complementary insulated gate field effect. Transis is obtained.

In the process shown in FIG. 3D, borosilicate glass 26 is selectively deposited on the N-type polycrystalline silicon layer 25 and P
Although the polycrystalline silicon layer on the type source region 9 and drain region 10 is converted to P type, other methods as shown in FIG. 3G or FIG. 3H may also be used. In the case of Fig. 3G, N-type polycrystalline silicon layer 2
A SiO 2 layer 40 is deposited on the entire surface of the SiO ₂ layer 40 except for the portions corresponding to the source and drain regions 9 and 10, and P-type impurities are diffused through the window holes 41 and 42 using the SiO ₂ layer 40 as a mask. , the N-type polycrystalline silicon layer 25 in the portions corresponding to the source and drain regions 9 and 10 is converted into a P-type polycrystalline silicon layer 27. In the case of FIG. 3H, a pure polycrystalline silicon layer 4 that is not doped with impurities
3, this polycrystalline silicon layer 43 is deposited.
A phosphosilicate glass layer is formed on the entire surface except for the portions corresponding to the source and drain regions 9 and 10, and the polycrystalline silicon layer immediately below it is made into an N type by using this phosphosilicate glass layer 44 as a diffusion source. , and P-type impurities are diffused through the window holes 45 and 46 of the phosphosilicate glass layer 44 to form a P-type polycrystalline silicon layer in the portions corresponding to the source and drain regions 9 and 10.

Furthermore, the P-type source region 9 and drain region 10 can be formed separately only at the portions that are ohmicly connected to the polycrystalline silicon layer. FIG. 4 is an example (only the source region 9 is shown for convenience of explanation),
A window hole 52 of an insulating layer 51 such as SiO ₂ is formed at a position adjacent to the P-type source region 9 formed in advance, and a polycrystalline silicon layer 44 that is not doped with impurities is formed including this window hole 52. , its window hole 5
In the same manner as described above, P-type impurities are selectively diffused into the polycrystalline silicon layer 44 in the portion corresponding to 2 to convert it into a P-type polycrystalline silicon layer 27. through the base 1
The high concentration region 53 of the same conductivity type is formed at a position in contact with the source region 9. The other portion of the polycrystalline silicon layer is converted to N type.

According to the present invention described above, since the gate electrode 30 in the P-channel insulated gate field effect transistor (P-MOS) is formed of an N-type polycrystalline silicon layer similarly to the N-channel insulated gate field effect transistor, A more stable gate can be obtained in a P-channel insulated gate field effect transistor than in the prior art. In addition, since most of the electrode wiring is made of N-type polycrystalline silicon, except for a part that makes ohmic connection with the source and drain regions 9 and 10 of the P-channel transistor (P-MOS), the resistance of the electrode wiring is low. It becomes possible.

Furthermore, in the drain connection wiring 33 made of a polycrystalline silicon layer exhibiting N-type and P-type in contact with the respective drain regions 4 and 10, a metal layer is formed to cover the PN junction end of the polycrystalline silicon layer. Since the entire layer 28 is formed by plasma etching, polycrystalline silicon layers of different conductivity types can be formed with the same width, and by leaving the metal layer 28 as it is after etching, both polycrystalline silicon layers of different conductivity types can be formed. layers 25 and 27
are automatically connected ohmicly by the metal layer 28. Therefore, there is no need to connect again using a metal layer such as Al as in the conventional case, and a multilayer wiring is formed also on the PN junction end via an insulating layer 34 such as SiO ₂ . Therefore, according to the present invention, an integrated circuit of complementary insulated gate field effect transistors with high density and high performance can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of a complementary insulated gate field effect transistor using a conventional silicon gate, FIG. 2 is a plan view showing an etched state of the drain connection wiring portion, and FIGS. 3 A to F are in accordance with the present invention. 3G and H are sectional views showing another example of the manufacturing method, and FIG. 4 is a sectional view of the main part showing still another example of the present invention. FIG. 3 and 4 are N-type source and drain regions;
9 and 10 are P-type source and drain regions;
25 is N-type polycrystalline silicon, 27 is P-type polycrystalline silicon, 29 and 30 are gate electrodes, 28 is a metal layer, and 33 is a drain connection wiring.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device having an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, including electrode extraction portions for the source and drain on the gate insulating film of both transistors. forming a conductive semiconductor layer on the entire surface of the conductive semiconductor layer, with only the source and drain electrode extraction portions of the P-channel insulated gate field effect transistor being P type and the rest being N type; forming a metal layer; patterning the conductive semiconductor layer including the metal layer to form gate electrodes of both transistors;
A method for manufacturing a semiconductor device, comprising a step of forming a source electrode, a drain electrode, and a drain connection wiring.