JPS605067B2 - MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a MOS type semiconductor device using a semiconductor substrate formed on an insulating substrate.

Compared to bipolar integrated circuits, MOS integrated circuits (MOSICs) have the advantage of higher integration density and lower cost, but have the disadvantage of slower calculation speed.

Therefore, various methods have recently been proposed to increase the calculation speed of MOSIC. That is, using the gate electrode as a diffusion mask, the source-drain distance (channel length) of the MOS transistor is determined by a so-called self-alignment method that automatically determines the positions of the source and drain regions.
A method of shortening the distance and increasing mutual conductance,
A method of increasing calculation speed by forming elements on an insulating substrate and reducing the stray capacitance of the wiring part of the MOS [
SOS (Silicon Saphire) MOSI
C] has been proposed. However, when using the SOSMOSIC method, the semiconductor substrate is electrically floating, so
Voltage fluctuations due to leakage current occur between the insulating substrate and the semiconductor substrate layer, resulting in fluctuations in threshold voltage (V ratio),
It has unstable factors such as fluctuations in the dependence of drain current on drain voltage. This invention has been made in view of the above points, and by connecting a source region and a semiconductor substrate through a conductive region, fluctuations in Vth can be reduced.
It is an object of the present invention to provide an SOSMOB type semiconductor device that eliminates unstable factors such as fluctuations in the dependence of drain current on drain voltage.

The present invention will be explained below with reference to Examples.

FIG. 1 shows an n-channel MO which is an embodiment of the present invention.
It is a figure which shows the manufacturing process of an S-type transistor.

The manufacturing process of the embodiment will be explained with reference to FIG. As shown in FIG. 1a, on an insulating substrate 1 made of sapphire or the like, an epitaxial layer 2 made of p-type silicon is formed by epitaxial growth to a thickness of about 1 inch. A resist film 4 is deposited by photolithography on the semiconductor substrate 3, which is a p-type silicon region forming the source region, drain region, and channel region of the epitaxial layer 2, and a plasma etching method is used to deposit the resist film 4. The epitaxial layer 2 other than the semiconductor substrate 3 is removed. Next, as shown in FIG. 1b, the resist film 4 is removed and heated in an oxidizing atmosphere to form silicon dioxide (Si0) as a gate insulating film.
2) Form the film 5. Subsequently, a polycrystalline silicon layer for forming a gate electrode is formed on this Si02 film 5 by vapor phase growth, and the polycrystalline silicon layer other than the portion that will become the gate electrode 6 is removed by photolithography. Next, as shown in FIG. 1c, using the gate electrode 6 as a mask, the Si02 film 5 is removed by etching to remove the gate electrode 5 and the portions of the semiconductor substrate 3 on both sides of the gate electrode that are to become source and drain regions. Phosphorus or arsenic is diffused into the n+ type gate electrode 5, source region 7, and drain region 8. Next, the gate electrode 6, the source electrode 7, and the drain region 8
, and an insulating substrate 1 from which the epitaxial layer 2 has been removed.
A Sj02 film 9 is deposited thereon, and a hole 1 is formed in the Si02 film 9 for later depositing metal for electrodes and wiring in the drain region 8.
0 is formed by photolithography, and platinum 11 is deposited on the drain region 8 and Si02 film 9 exposed in this hole. Next, as shown in FIG. 1d, heat treatment is performed at a temperature of about 500 q0 to form a platinum-silicon alloy layer 12 only in the region in contact with the drain region 8. Next, as shown in Figure 1e, platinum and
Platinum other than the silicon alloy layer 12 is removed, followed by L and S.
A hole for contact between the source region 7 and the electrode/wiring metal, and a hole for contact between the gate electrode 6 and the wiring metal are formed in the i02 film 9 [
This hole is formed in the Si029 above the extension of the gate electrode 6 perpendicular to the paper plane shown in FIG. 1e. Therefore, Fig. 1 e
is not represented. ) to form. Next, as shown in FIG. 1f, aluminum is deposited and wiring for the gate electrode 6, source electrode 13 and drain electrode 14, and wiring therefor are formed by photolithography. Subsequently, heat treatment is performed at a temperature of about 400-500°C in order to improve electrical contact between the gate electrode 6, source region 7, and drain region 8 and the aluminum. FIG. 2 is a sectional view of the main part of the completed n-channel MOB type transistor.

In FIG. 2, the same reference numerals as those shown in FIG. 1 represent the same elements, 15 is an aluminum-silicon alloy layer formed in the source region 7 by heat treatment after aluminum deposition, and 16 is the same drain layer. A platinum-aluminum-silicon alloy layer formed in region 8 is shown. 0. When the source region 7 and drain region 8 are formed in an n-domain shape that is shallower than the fall, as shown in FIG.
The silicon alloy layer 15 is formed deeper than the source region 7, electrically shorting the semiconductor substrate 3 and the source region 7 via the aluminum-silicon alloy layer 15, and floating the potential between the semiconductor substrate 3 and the source region 7. This can eliminate the drawbacks of SOSMOS type transistors.

In the drain region 8, the platinum-silicon alloy layer 12 changes to a platinum-silicon-aluminum alloy layer 16. In this case, the platinum-silicon-aluminum alloy layer 16 can be made shallow, so that the drain region 8 and the semiconductor substrate A normal pn junction is formed between 3 and 3. In the above embodiment, platinum was used as the metal for the metal-silicon alloy layer formed in the drain region, but a metal that can make the alloy layer thinner, such as palladium or hafnium, may also be used.

Further, in the above embodiment, the present invention is applied to an n-channel SO
Although the case where the present invention is applied to an SMOS type transistor has been described, it goes without saying that the present invention is similarly applicable to a p-channel SOSMOS type transistor.

Furthermore, in the above embodiment, the case where the present invention is applied to an SOSMOS type transistor is described, but the SOS
This invention is similarly applicable to M061C.

As detailed above, in the SOSMOS type semiconductor device according to the present invention, a metal forming an alloy layer containing more semiconductor, which is a constituent material of the semiconductor substrate, than a constituent material of the drain electrode is used as a constituent material of the source electrode. Since the p-n junction is electrically short-circuited by the alloy layer only in the source region, the calculation speed is increased and there are no problems such as fluctuations in Vth due to electrical floating of the semiconductor substrate and fluctuations in the dependence of the drain current on the drain voltage. This has the effect of removing stable elements.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
FIG. 2 is a sectional view of the main parts of the completed embodiment. In the figure, 1 is an insulating substrate, 3 is a semiconductor substrate, and 5 is S
i02 waist, 6 a gate electrode, 7 a source region, 8 a drain region, 9 an Si02 film, 13 a source electrode, 14 a drain electrode, 15 an aluminum-silicon alloy layer,
16 is a platinum-aluminum-silicon alloy layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. An insulating substrate, a semiconductor substrate formed on the insulating substrate, a source region and a drain region provided on the surface of the semiconductor substrate and forming a pn junction with the semiconductor substrate, and the source In the device comprising a source electrode and a drain electrode deposited on the respective surfaces of the region and the drain region, the source electrode contains more of the semiconductor that is the constituent material of the semiconductor substrate than the constituent material of the drain electrode. A MOS type semiconductor device, characterized in that a pn junction is short-circuited by the alloy layer only in the source region, using a metal forming an alloy layer containing the metal. 2. Claim 1, characterized in that the source electrode is made of aluminum, and the drain electrode is made of platinum deposited on the surface of the drain region and aluminum deposited on the platinum. MOS described in section
shaped semiconductor device. 3. Claim 1, characterized in that the source electrode is made of aluminum, and the drain electrode is made of palladium deposited on the surface of the drain region and aluminum deposited on the palladium. MOS type semiconductor device as described in 2. 4. Claim 1, wherein the source electrode is made of aluminum, and the drain electrode is made of hafnium deposited on the surface of the drain region and aluminum deposited on the hafnium. MOS type semiconductor device as described in 2.