JPS605068B2 - MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a MOS type semiconductor device using a semiconductor substrate formed on an insulating substrate.

Compared to bipolar integrated circuits, MOS integrated circuits (MOSICs) have the advantage of higher integration density and lower cost, but have the disadvantage of slower calculation speed.

Therefore, various methods have recently been proposed to increase the calculation speed of MOSIC. In other words, by using the gate electrode as a diffusion mask and using the so-called self-alignment method that automatically determines the thickness of the source and drain regions of a MOS transistor, the distance between the source and drain (channel length) is shortened and the mutual conductance is increased. A method that increases the calculation speed by forming an element on an insulating substrate and reducing the stray capacitance of the MOSIC wiring section [SOS (Silicon Sapphire) MO
SIC] has been proposed. However, SOSM061
When using the C method, since the semiconductor substrate is electrically floating, leakage current occurs between the insulating substrate and the semiconductor substrate layer, resulting in fluctuations in threshold voltage (V) and drain current with respect to drain voltage. It has unstable elements such as fluctuations in the degree of dependence. This invention has been made in view of the above points, and by connecting the source region and the semiconductor substrate through a conductive region, it is possible to prevent instability such as fluctuations in the V ratio and fluctuations in the dependence of the drain current on the drain voltage. The purpose of this invention is to provide an SOSMOS type semiconductor device without any elements.

The present invention will be explained below with reference to Examples.

FIG. 1 shows an n-channel MO which is an embodiment of the present invention.
It is a figure which shows the manufacturing process of an S type transistor.

The manufacturing process of the embodiment will be explained with reference to FIG. As shown in FIG. 1a, on an insulating substrate 1 made of sapphire or the like, an epitaxial layer 2 made of p-type silicon is formed by epitaxial growth to a thickness of about 1 inch. A resist film 4 is deposited by photolithography on the semiconductor substrate 3, which is a p-type silicon region forming the source region, drain region, and channel region of the epitaxial layer 2, and a plasma etching method is used to deposit the resist film 4. The epitaxial layer 2 other than the semiconductor substrate 3 is removed. Next, as shown in FIG. 1b, the resist film 4 is removed and heated in an oxidizing atmosphere to form silicon dioxide (Sj0) as a gate insulating film.
2) Form the film 5. Next, as shown in FIG.
Remove membrane 5. Next, as shown in FIG. 1d, a polycrystalline silicon layer is formed by vapor phase epitaxy to cover the insulating substrate 1, the semiconductor substrate 3 from which the Si02 film has been removed, and the remaining Si02 film 5, and becomes a gate electrode. The polycrystalline silicon layer is removed by photolithography except for the portion that should become the drain region of the semiconductor substrate 3, and the portion that should become the lead-out portion from the drain region. Next, as shown in FIG. 1e, the Si02 film 5 is removed by etching using the remaining polycrystalline silicon as a mask. Subsequently, phosphorus or arsenic is applied to the portion of the polycrystalline silicon layer that is to become the gate electrode and the portion that is to be the lead-out portion from the drain region, and also to the portion of the semiconductor substrate 3 that is to become the source region and the drain region. is diffused to form a gate electrode 6, a lead-out portion 7, a source region 8, and a drain region 9, which are n+ regions. In this case, since the diffusion rate of phosphorus or arsenic in the polycrystalline silicon layer is several times faster than the diffusion rate in the single crystal semiconductor substrate 3, the polycrystalline silicon layer has a thickness commensurate with the diffusion rate ratio. can be used. Next, as shown in FIG.
A hole for contact between the gate electrode 6 and the wiring metal, and a hole for contact between the lead-out portion 7 and the source region 8 and the electrode/wiring metal are formed by photolithography [Contact between the gate electrode 6 and the wiring metal] A hole is formed in the Si02 film above the extension of the gate electrode 6 perpendicular to the plane of the paper as shown in FIG. 1f. Therefore, it is not represented in FIG. 1f. ]. Subsequently, aluminum is vapor deposited, and wiring for the gate electrode 6, source electrode 11 and drain electrode 12, and wiring for these are created by photolithography. Poke the gate electrode 6
In order to improve electrical contact between the source region 8 and drain region 9 and aluminum, heat treatment is performed at a temperature of about 400 to 50 psi. FIG. 2 is a cross-sectional view showing the state of formation of the alloy layer. In FIG. 2, the same symbols as those shown in FIG. 1 represent the same things, 13 and 14.
2A and 2B show aluminum-silicon alloy layers formed in the source region 8 and the lead-out portion 7, respectively, by heat treatment after aluminum deposition. 0. & When a shallower source region is formed, the aluminum-silicon alloy layer 13 is formed deeper than the source region, as shown in FIG. By electrically short-circuiting the semiconductor substrate 3 and the source region 8, it is possible to eliminate the drawback of the SOSMOS transistor that the potential between the semiconductor substrate 3 and the source region 8 floats.

In the drain region 9, the drain electrode 12 is not on the drain region 9 but on an extension of the lead-out portion 7 on the insulating substrate 1; therefore, the aluminum-silicon alloy layer 14 is Even if formed, this aluminum-silicon alloy layer 14 is
It does not electrically short the pn junction of the
A junction is formed. In the above embodiment, the present invention is applied to an n-channel SOSMOS type transistor, but it goes without saying that the present invention is similarly applied to a p-channel SOSMOS type transistor.

Further, in the above embodiment, the case where the present invention is applied to an SOSMOS type transistor is described, but the SOSM
The present invention is similarly applicable to OSIC.

As described in detail above, in the SOSMOS type semiconductor device according to the present invention, a lead-out portion from a drain region made of a highly impurity-concentrated semiconductor and a drain electrode attached to the surface of this lead-out portion are provided. , since the pn junction is short-circuited by an alloy layer consisting of the electrode metal and the semiconductor of the semiconductor substrate, the calculation speed is increased, and the fluctuation of Vth due to the electrical floating of the semiconductor substrate and the dependence of the drain current on the drain voltage are reduced. This has the effect of eliminating unstable factors such as temperature fluctuations.

[Brief Description of the Drawings] Fig. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
FIG. 2 is a cross-sectional view showing the state of formation of the alloy layer. In the figure, 1 is an insulating substrate, 3 is a semiconductor substrate, and 5 is S
In the i02 film, 6 is a gate electrode, 7 is a lead-out part, 8 is a source region, 9 is a drain region, 11 is a source electrode, 12 is a drain electrode, 13 is an alloy layer in the source region, and 14 is an alloy layer in the lead-out part. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 1 Figure 2

Claims (1)

[Claims] 1. An insulating substrate, a semiconductor substrate formed on the insulating substrate, a source region and a drain region provided on the surface of the semiconductor substrate and forming a pn junction with the semiconductor substrate, high impurity. A lead-out portion made of a concentrated semiconductor and connected to the drain region, and a source electrode and a drain electrode deposited on the respective surfaces of the source region and the lead-out portion, and the source region is made of a constituent material of the semiconductor substrate. A MOS type semiconductor device characterized in that a pn junction is short-circuited by an alloy layer made of a certain semiconductor and a metal that is a constituent material of an electrode. 2. The MOS type semiconductor device according to claim 1, wherein the lead-out portion is made of polycrystalline silicon with a high impurity concentration. 3. Claim 1 or claim 3, wherein the lead-out part has an extension part formed on an insulating substrate on which no semiconductor substrate is formed, and the drain electrode is attached to the extension part. MOS type semiconductor device according to item 2.