KR900007904B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR900007904B1
KR900007904B1 KR1019850000298A KR850000298A KR900007904B1 KR 900007904 B1 KR900007904 B1 KR 900007904B1 KR 1019850000298 A KR1019850000298 A KR 1019850000298A KR 850000298 A KR850000298 A KR 850000298A KR 900007904 B1 KR900007904 B1 KR 900007904B1
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oxide film
type
well
substrate
layer
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KR850006261A (en
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기요후미 오찌이
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가부시끼가이샤 도오시바
사바 쇼오이찌
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

forming at least one groove (24,25) in a substrate (21) having at least one surface well region (22,23); forming insulating film (26) over the entire surface; etching it to leave insulating film only in the groove; and burying conductive material in the groove to form a conductive layer (28a,28b) connected to the well and/or substrate, and to a power sypply. Conductire material is pref. a refractory metal, esp. Mo, or doped poly Si.

Description

상보형 반도체장치의 제조방법Manufacturing method of complementary semiconductor device

제1도 및 제2도는 종래 CMOS 트랜지스터의 단면도.1 and 2 are cross-sectional views of conventional CMOS transistors.

제3도(a) 내지 제3도(f)는 본 발명의 1실시예에 관련한 CMOS 트랜지스터의 제조공정도.3A to 3F are manufacturing process diagrams of a CMOS transistor according to one embodiment of the present invention.

제4도는 제3도(f)의 단면도.4 is a cross-sectional view of FIG. 3 (f).

제5도는 제3도(f)에 관련된 CMOS 트랜지스터의 등가회로도.5 is an equivalent circuit diagram of a CMOS transistor according to FIG. 3 (f).

제6도는 제3도(f)에 도시된 CMOS 트랜지스터의 골내부의 변형례를 설명하기 위한 단면도.FIG. 6 is a cross-sectional view for illustrating a modification example in the valley of the CMOS transistor shown in FIG. 3 (f).

제7도 내지 제9도는 본 발명의 실시예에 관한 CMOS 트랜지스터의 단면도이다.7 through 9 are cross-sectional views of a CMOS transistor according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21,45 : 실리콘 기판 22,43 : P형 웰21,45: Silicon substrate 22,43: P type well

23 : N형 웰 24,25,45,48,51.52 : 골23: N-type wells 24, 25, 45, 48, 51.52: Goal

26,26',48 : 산화막 271,272: 광차단막,26,26 ', 48: oxide film 27 1 , 27 2 : light blocking film,

28 : Mo층(저저항의 도전체) 29,30 : 게이트전극28 Mo layer (low resistance conductor) 29,30 gate electrode

33,35 : 소오스영역 34,36 : 드레인영역33,35 source region 34,36 drain region

37 : 층간절연막 38,39 : 콘택트홀37: interlayer insulating film 38,39: contact hole

40,41 : 인출배선 43,44 : 확산층40, 41: drawing wiring 43, 44: diffusion layer

46 : 고융점 금속층 49 : 불순물도우프 다결정실리콘층46: high melting point metal layer 49: impurity doped polysilicon layer

[산업상의 이용분야][Industrial use]

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 표면에 웰영역(well 領域)이 형성되어 있는 상보형 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a complementary semiconductor device in which a well region is formed on a surface thereof.

[종래의 기술 및 그 문제점][Traditional Technology and Problems]

종래, 예컨대 상보형 MOS 트랜지스터(CMOS TR)와 같은 상보형 반도체장치를 미세하게 제조하는 과정에 있어서는 웰의 분리를 기술적으로 확립시키는 것이 중요한데, 이는 CMOS가 갖추고 있는 몇몇의 결점이 거의 웰영역의 분리에 연관되기 때문이다. 예컨대 스케일링에 수반되는 P+층-P웰의 내압(또는 N+층-N웰의 내압), 다이리스터효과에 의한 랫치업 내량, 웰의 분리에 따른 칩면적의 증대와 같은 곤란한 문제가 생긴다.Conventionally, it is important to technically establish the separation of wells in the process of finely manufacturing a complementary semiconductor device such as a complementary MOS transistor (CMOS TR). Because it is associated with. For example, difficulties arise such as the internal pressure of the P + layer-P well (or the internal pressure of the N + layer-N well) accompanying scaling, the latch-up resistance due to the dielister effect, and the increase of the chip area due to separation of the wells.

종래의 상보형 CMOS 트랜지스터는 제1도에 도시한 바와 같이 제조된다. 즉, P형의 반도체기판(1)상에 P형 웰영역(2)과 N형 웰영역(3)을 형성시킨 후, 이들 웰영역(2)(3)에는 기판(1)에 도달하게 되는 골(4 ; 溝)을 형성시킨다. 이어 표면산화를 실시하고 전체면에 다결정실리콘층을 퇴적시킨 후, 이 다결정 실리콘을 전체면에 걸쳐 엣칭시켜 골(4)에만 다결정실리콘을 잔존시키다. 다음에 골(4)내의 다결정실리콘층을 산화시켜 절연산화막(5)을 형성시킨다. 이하는 통상적인 방법에 따라 P형 웰(2)과 N형 웰(3)상에 게이트절연막(8)(9)을 매개로 게이트전극(6)(7)을 형성시킨 후, 게이트전극(6)(7)을 마스크로 이용하여 P형 웰(2)과 N형 웰(3)에 각각 N-형의 소오스·드레인영역(10)(11)과 P+형의 소오스 드레인영역(12)(13)을 형성시킨다. 그 다음에는 전체면에 층간절연막(14)을 형성시키고 콘택트홀(15)을 형성시킨다.Conventional complementary CMOS transistors are fabricated as shown in FIG. That is, after forming the P type well region 2 and the N type well region 3 on the P type semiconductor substrate 1, the well regions 2 and 3 reach the substrate 1. To form a valley (4; 溝). Subsequently, the surface is oxidized and a polysilicon layer is deposited on the entire surface, and then the polycrystalline silicon is etched over the entire surface to leave polycrystalline silicon only in the valleys 4. Next, the polysilicon layer in the valley 4 is oxidized to form an insulating oxide film 5. The gate electrodes 6 and 7 are formed on the P type wells 2 and the N type wells 3 through the gate insulating films 8 and 9 according to a conventional method, and then the gate electrodes 6 are formed. (7) as a mask, an N-type source / drain region 10 (11) and a P + type source drain region 12 (for the P-type well 2 and the N-type well 3, respectively ( 13). Then, the interlayer insulating film 14 is formed on the entire surface and the contact hole 15 is formed.

이후에는 P형 웰(2)과 N형 웰(3) 각각의 소오스영역(10(12)에 대응되는 부분에다 콘택트홀(15)매개로 Vss단자(전원선)에 접속되는 인출배선(16)과 Vcc단자(전원선)에 접속되는 인출배선(17)을 형성시킴과 동시에 상기 드레인영역(11)(13)간을 접속시키는 인출배선(18)을 형성함으로써 CMOS 트랜지스터가 제조된다.Subsequently, the lead wire 16 connected to the Vss terminal (power line) through the contact hole 15 in the portion corresponding to the source region 10 (12) of each of the P-type well 2 and the N-type well 3 is connected. And a lead-out wiring 17 connected to the Vcc terminal (power supply line) and a lead-out wiring 18 for connecting the drain regions 11 and 13 to form a CMOS transistor.

상기한 제조방법에 따라 제조된 CMOS 트랜지스터에 의하면, 골(4)의 내부에 절연산화막(5)을 매립하여 P형 웰(2)과 N형 웰(3)을 분리시키기 때문에 P+형의 드레인영역(13)-P형 웰(2)(또는 N+형의 드레인영역(11)-N형 웰(3)의 내압은 종방향의 간격으로 결정되도록 되어 대폭 개선되게 된다. 또한 다이리스터효과에 있어서도 횡방향의 PNPN이 절연산화막(5)에 의해 분단되므로 랫치업내량도 대폭 개선된다. 단, 기판(1)과 웰영역(2)(3)의 전위바이어스가 충분하게 되어 있는 것이 랫치업 회피의 필수요건인 것은 물론이다. 따라서 제1도에 나타낸 트랜지스터에 따르면, 기판(1)과 웰(2)(3)의 전위바이어스는 적당한 밀도로 상면에서부터 콘택트홀(15)을 매개로 전원선으로부터 바이어스하는 방법이 필요로 된다. 그러나 종래 기술에 의하면, 예컨대 메모리장치의 메모리셀 배열의 중과 같이 매우 고밀도에서 레이 아웃(LAY OUT)되지 않으면 안되는 부분에다 상기한 바와 같이 상면으로부터 콘택트홀(15---)읕 매개로 바이어스를 행하는 것은 미세화가 되어가면 갈수록 큰 부담으로 되고, 랫치업 내량(耐量)의 향상과 원가절감의 효과를 거둘수는 없음이 더욱 현저해지게 된다.According to the CMOS transistor manufactured according to the above-described manufacturing method, since the insulating oxide film 5 is embedded in the valley 4 to separate the P-type well 2 and the N-type well 3, the drain of P + type is obtained. The internal pressure of the region 13 -P well 2 (or N + type drain region 11 -N well 3) is determined at intervals in the longitudinal direction to be greatly improved. Also, since the PNPN in the lateral direction is divided by the insulating oxide film 5, the latch up resistance can be greatly improved, however, a sufficient potential bias between the substrate 1 and the well region 2, 3 is avoided. Therefore, according to the transistor shown in Fig. 1, the potential biases of the substrate 1 and the wells 2 and 3 are separated from the power supply line via the contact hole 15 from the upper surface with a suitable density. There is a need for a biasing method, however, according to the prior art, for example, a memory cell of a memory device. As described above, biasing the contact hole from the top surface through the contact hole (15 ---) 읕 as described above becomes very burdensome as the size becomes smaller. It is even more pronounced that the improvement of dental tolerance and cost reductions cannot be achieved.

또한, 종래에는 제2도에 도시한 바와 같이, P형 웰(2)의 N+형 드레인영역(11)과 N형 웰(3)의 P+형 드레인영역(13)을 절연산화막(5)에 접하도록 형성시킨 CMOS 트랜지스터의 구조가 소개되어 있다. 이러한 구조의 트랜지스터에 의하면, 드레인영역(11)(13)이 절연산화막(5)에 접촉되어 형성되어 있기 때문에 웰영역(2)(3)의 경계부의 고유면적을 감소시킬 수 있게 됨과 더불어 드레인영역(11)(13)의 측면에 형성되는 용량치를 감소시키는 효과를 거둘 수 있다. 그러나, 제2도에 나타낸 트랜지스터에 의하며, 골(4)내부의 산화막(5)과 드레인영역(11)(또는 13)의 접촉부위에 누실전류(leakage current)가 흐르게 되는 문제가 생긴다. 이것은 저소비전력의 성능이 중요한 특성으로 되는 CMOS 트랜지스터에 있어서 치명적인 결점으로 된다.In addition, conventionally, as shown in FIG. 2, the N + type drain region 11 of the P type well 2 and the P + type drain region 13 of the N type well 3 are separated from each other by the insulating oxide film 5. The structure of a CMOS transistor formed in contact with is introduced. According to the transistor having such a structure, since the drain regions 11 and 13 are formed in contact with the insulating oxide film 5, the intrinsic area of the boundary between the well regions 2 and 3 can be reduced and the drain region can be reduced. The effect of reducing the capacitance formed on the side surfaces of (11) (13) can be achieved. However, according to the transistor shown in FIG. 2, a problem arises in that a leakage current flows through the contact portion between the oxide film 5 and the drain region 11 (or 13) in the valley 4. This is a fatal drawback for CMOS transistors where low power consumption performance is an important characteristic.

[발명의 목적][Purpose of invention]

본 발명은 상기한 점을 감안해서 발명된 것으로, 칩면적을 감소시켜 소자의 미세화를 얻을 수 있도록 하는 한편, 랫치업 내량을 향상시킬 수 있는 상보형 반도체장치의 제조방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above point, and an object thereof is to provide a method of manufacturing a complementary semiconductor device capable of reducing chip area to obtain device miniaturization and improving latchup resistance. .

[발명의 구성][Configuration of Invention]

상기 목적을 달성하기 위한 본 발명은, 상보형 반도체장치의 제조방빕에 있어서, 표면에 웰영역(22,23)을 구비하고 있는 반도체기판(21)에다 적어도 하나 이상의 골(24 ; 25)을 형성시키는 공정과, 상기 골(24 ; 25)의 내벽을 산화막(26)으로 덮는 공정, 상기 골(24 : 25)의 내벽 상부의 산화막의 일부 및 싱기 골(24) 바닥의 산화막(26)을 선택적으로 엣칭시키는 공정, 상기 골(24 ; 25)의 내벽에 잔존하는 절연막(26', 26')을 매개로 저저항성분의 도전체(28,28)을 매립시키는 공정 및, 상기 기판(21)이나 웰영역(23)에 대한 바이이스전위를 상기 도전체(28,28)에 인가하는 공정을 구비하여 이루어진 것을 특징으로 한다.According to the present invention for achieving the above object, at least one of the valleys 24 and 25 is formed in the semiconductor substrate 21 having the well regions 22 and 23 on its surface in the manufacturing method of the complementary semiconductor device. And a step of covering the inner wall of the valleys 24 and 25 with an oxide film 26, a portion of the oxide film on the upper inner wall of the valleys 24 and 25, and an oxide film 26 at the bottom of the thin bone 24. A step of embedding the low-resistance conductors 28 and 28 through the insulating layers 26 'and 26' remaining on the inner wall of the valleys 24 and 25, and the substrate 21 Or applying a bias potential for the well region 23 to the conductors 28 and 28.

(작용)(Action)

상기와 같이 구성된 본 발명은, 웰영역을 구비하고 있는 반도체기판에 적어도 하나의 골을 형성시킨 후 그 골에다 절연막을 매개하여 적당한 저저항성의 도전체를 매립시킴과 더불어, 이 도전체에다 기판이나 웰영역에 대한 바이어스전위를 인가함으로서 발생한 전자 내지는 홀을 빠르게 기판(혹은 웰영역)에서 전원선으로 빠져나가게 하여 상기한 목적을 달성하도록 되어 있다.According to the present invention configured as described above, at least one groove is formed in a semiconductor substrate having a well region, and an appropriate low resistance conductor is embedded in the valley through an insulating film. By applying a bias potential to the well region, electrons or holes generated quickly exit from the substrate (or well region) to the power supply line, thereby achieving the above object.

(실시예)(Example)

이하, 예시도면을 참조해서 본 발명에 따른 1실시예를 상세히 설명한다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

제3도(a) 내지 제3도(f)는 본 발명의 1실시예에 관한 CMOS 트랜지스터의 제조공정도이고, 제4도는 제3도(f)의 단면도로서, [I]우선, 예컨대 P형 실리콘기판(21)의 표면에 부분적으로 P형 웰(22)과 N형 웰(23)을 각각 형성시킨다. 이어 이들 웰(22)(23)의 경계부분에 기판(21)의 표면에 도달하는 골(24)(25)을 형성시킨다. 그후 산화처리를 하여 산화막(26)을 형성시키고, 이 산화막(26)의 소정위치에 광차단막(271: photo resist)을 형성시킨다(제3도(a)). 그후 반응성이온에칭법(Reactive Ion Etching, RIE)에 의해 골(24) 내벽의 산화막(26)과, 골(25)내벽의 산화막(26)과 바닥의 산화막(26)을 제외하고 선택적으로 엣칭제거를 실시한다. 또한, 상기 광차단막(271)을 제거시킨 후, 다시 광차단막(272)을 적당하게 형성시킨다(제3도(b)). 이어 광차단막(272)을 마스크로 이용해서 상기 산화막(26)을 선택적으로 제거한다. 그 결과, 한쪽의 골(24)에는 P형 웰(22)측 상부를 제외한 내벽에 산화막(26')이 잔존하게 되며, 다른 골(25)에는 내벽의 N형 웰(23)측 상부를 제외한 내벽 및 바닥에 산화막(26')이 잔존하게 된다.3 (a) to 3 (f) are manufacturing process diagrams of a CMOS transistor according to an embodiment of the present invention, and FIG. 4 is a cross sectional view of FIG. 3 (f). P-type wells 22 and N-type wells 23 are partially formed on the surface of the silicon substrate 21, respectively. Subsequently, valleys 24 and 25 reaching the surface of the substrate 21 are formed at the boundary between the wells 22 and 23. Thereafter, an oxidation process is performed to form an oxide film 26, and a photoresist film 27 1 (photo resist) is formed at a predetermined position of the oxide film 26 (FIG. 3A). Thereafter, by etching of reactive ion etching (RIE), etching is selectively removed except for the oxide film 26 on the inner wall of the bone 24, the oxide film 26 on the inner wall of the bone 25 and the oxide film 26 on the bottom. Is carried out. Further, after removing the light shielding film (27 1), thereby suitably forming a back light shielding film (27 2) (FIG. 3 (b)). Followed by using the light shielding film (27 2) as a mask, selectively removing the oxide film 26. As a result, the oxide film 26 'remains on the inner wall of the one bone 24 except for the upper portion of the P-type well 22 side, and the other valley 25 except the upper portion of the N-type well 23 side of the inner wall 25. The oxide film 26 'remains on the inner wall and the bottom.

그후, 상기 광차단막(272)을 제거한다(제3도(c)).Thereafter, the light blocking film 272 is removed (FIG. 3C).

[II] 다음에 전체면에 고융점금속인, 예컨대 몰리브덴(Mo)을 매립하여 Mo층(28)을 형성한다(제3도(d)). 여기서 Mo층(28)과 기판(21)과는 저항성으로 접촉하게 된다. 이어 상기 Mo층(28)을 RIE법에 따라 엣칭 제거시키고, 상기 골(24) (25)의 내부에 산화막(26')을 매개로 Vss단자와 Vcc단자(전원선)로 되는 Mo층(28)을 매립한다(제3도(e)). 여기서 Vss와 Vcc단자는 기판(21)과 N웰(23)의 바이어스용으로 이용된다.[II] Next, a high melting point metal, such as molybdenum (Mo), is embedded in the entire surface to form an Mo layer 28 (Fig. 3 (d)). Here, the Mo layer 28 and the substrate 21 are in ohmic contact. Subsequently, the Mo layer 28 is etched and removed according to the RIE method, and the Mo layer 28 which becomes the Vss terminal and the Vcc terminal (power line) through the oxide film 26 'inside the valleys 24 and 25. ) Is embedded (Fig. 3 (e)). The Vss and Vcc terminals are used for biasing the substrate 21 and the N well 23.

이어 P형 웰(22)과 N형 웰(23)상에 게이트절연막(31)(32)을 매개로 각각 게이트전극(29)(30)을 형성시킨다. 그후 한쪽의 게이트전극(29)을 마스크로 이용해서 P형 웰(22)의 표면에 상기한 한쪽의 골(24)내부의 Mo층(28)과 접속되는 N+형의 소오스영역(33)과 N+형의 드레인영역(34)을 각각 형성시킨 후, 다른쪽의 게이트전극(30)을 마스크로 이용해서 N형 웰(23)의 표면에 골(25)내부의 Mo층(28)과 접속되는 P+형의 소오스영역(35)와 P+형의 드레인영역(36)을 형성시킨다. 계속해서 전체면에 층간절연막(37)을 형성시킨 후, P형 웰(22)과 N형 웰(23)의 각 드레인영역(34)(36) 일부에 대응되는 부실리콘기판(42)표면의 P형 웰(43)저면으로부터 상기 P형 웰(43)표면의 P형 확산층(44)까지의 거리를 d1, P형 웰(43)의 모서리에서 P형 확산층(45)까지의 거리를 d2, N형 실리콘기판(42)의 저항을 Rsub, P형 웰(43)의 저항을 Rwell로 한 경우, d1과 d2가 크고, Rsub과 Rwell이 작은 정도로 하기 어렵다. 그러나 본 발명을 이용함으로써 항상 Rsub=Rwel

Figure kpo00002
0을 실현할 수가 있게 된다.Subsequently, gate electrodes 29 and 30 are formed on the P-type wells 22 and the N-type wells 23 through the gate insulating films 31 and 32. Thereafter, using one gate electrode 29 as a mask, an N + type source region 33 connected to the Mo layer 28 inside the one valley 24 described above on the surface of the P type well 22; After forming the N + type drain regions 34, the other gate electrode 30 is used as a mask and connected to the Mo layer 28 inside the valley 25 on the surface of the N type well 23. P + type source region 35 and P + type drain region 36 are formed. Subsequently, after forming the interlayer insulating film 37 on the entire surface, the surface of the sub-silicon substrate 42 corresponding to a part of each of the drain regions 34 and 36 of the P-type well 22 and the N-type well 23 is formed. The distance from the bottom of the P-type well 43 to the P-type diffusion layer 44 on the surface of the P-type well 43 is d 1 , and the distance from the corner of the P-type well 43 to the P-type diffusion layer 45 is d. When the resistance of the 2 , N-type silicon substrate 42 is Rsub and the resistance of the P-type well 43 is Rwell, d 1 and d 2 are large, and Rsub and Rwell are small. However, by using the present invention always Rsub = Rwel
Figure kpo00002
0 can be realized.

또한, 상기 실시예에서는 2개의 골내부에 산화막을 매개로 저저항소자의 도전체로서 Mo층을 매립시키는 경우에 관해서 설명하였지만, 본 발명은 이에 한정되지는 않는다. 예컨대, 도전체로서 Mo층 대신 기판과 동일한 도전형인 불순물을 충분히 도우핑시킨 다결정실리콘층을 사용해도 된다.In the above embodiment, the case where the Mo layer is embedded in the two bones as the conductor of the low resistance element through the oxide film is described, but the present invention is not limited thereto. For example, instead of the Mo layer, a polysilicon layer sufficiently doped with impurities of the same conductivity type as the substrate may be used as the conductor.

또한, 제6도에 도시한 바와 같이, 고융점금속층(46)을 골(47)의 내벽에 산화막(48)을 매개로 설치한 후골(47)의 내부로 불순물 도우핑다결정실리콘층(49)(혹은 SiO2등의 산화막)을 매립시켜도 된다.In addition, as shown in FIG. 6, the high-melting-point metal layer 46 is provided with an impurity doped polycrystalline silicon layer 49 inside the bone 47 after the oxide film 48 is provided on the inner wall of the bone 47. (Or an oxide film such as SiO 2 ) may be embedded.

상기 실시예에서는 웰의 경계부분에 Vcc단자와 Vss단자용의 2개의 골을 설치한 경우에 대해 설명했지만, 본 발명은 이에 한정되지 않는다. 예컨대, 제7도와 같이 기판(21) 바이어스용의 골(50)만을 설치한 구조이어도 된다. 또한, 제8도에 도시한 바와 같이, 얕은 골(51)(52)을 P형 웰(22)과 N형 웰(23)에 각각 설치하고, P형 웰(22)과 N형 웰(23)의 쌍방을 바이어스시키는 구조이어도 된다.In the above embodiment, the case where two valleys for the Vcc terminal and the Vss terminal are provided at the boundary portion of the well is described, but the present invention is not limited thereto. For example, a structure in which only the valleys 50 for biasing the substrate 21 may be provided as shown in FIG. 7. In addition, as shown in FIG. 8, shallow valleys 51 and 52 are provided in the P-type wells 22 and the N-type wells 23, respectively, and the P-type wells 22 and the N-type wells 23 are provided. May be used to bias both.

또한, 제9도에 나타낸 바와 같이 2개의 골(24)(25)을 접근시켜 양자간에 산화막(26)이 개재하도록 한 구조이어도 된다.In addition, as shown in FIG. 9, the structure in which two valleys 24 and 25 are brought close to each other and the oxide film 26 is interposed therebetween may be sufficient.

[발명의 효과][Effects of the Invention]

상기한 바와 같이 본 발명에 의하면, 칩의 면적을 감소시켜 소자의 미세화를 구현할 있고, 랫치업내량을 향상시킬 수 있게 된다.As described above, according to the present invention, it is possible to implement a miniaturization of the device by reducing the area of the chip, and to improve the latch-up tolerance.

Claims (1)

상보형 반도체장치의 제조방법에 있어서, 표면에 웰영역(22,23)을 구비하고 있는 반도체기판(21)에다 적어도 하나 이상의 골(24 ; 25)을 형성시키는 공정과, 상기 골(24 ; 25)의 내벽을 산화막(26)으로 덮는 공정, 상기 골(24 ; 25)의 내벽 상부의 산화막 일부 및 골(24) 바닥의 산화막(26)을 선택적으로 엣칭제거시키는 공정, 상기 골(24 ; 25)의 내벽에 잔존하는 산화막(26',26')을 매개로 저저항성분의 도전체(28,28)를 매립시키는 공정 및, 상기 기판(21)이나 웰영역(23)에 대한 바이어스전위를 상기 도전체(28,28)에 인가하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.A method of manufacturing a complementary semiconductor device, comprising: forming at least one valley 24 or 25 on a semiconductor substrate 21 having well regions 22 and 23 on its surface, and the valleys 24 and 25; A step of covering the inner wall of the crest with an oxide film 26, selectively etching away a part of the oxide film on the upper part of the inner wall of the troughs 24 and 25 and the oxide film 26 at the bottom of the trough 24, and the troughs 24 and 25 Embedding the low-resistance conductors 28 and 28 through the oxide films 26 'and 26' remaining on the inner wall of the < RTI ID = 0.0 >) < / RTI > and the bias potential for the substrate 21 or the well region 23. And a step of applying to the conductors (28, 28).
KR1019850000298A 1984-02-14 1985-01-18 Method of manufacturing semiconductor device KR900007904B1 (en)

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