JPH0766967B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

2. Description of the Related Art A conventional field effect (hereinafter abbreviated as MOS) semiconductor device is a semiconductor substrate after forming an isolation oxide film 21, a gate oxide film 22 and a gate electrode 23 on a semiconductor substrate 1 as shown in FIG. A source and drain region 24 is formed in. After forming an interlayer insulating film 25 on the entire surface, the interlayer insulating film on the source and drain regions is selectively removed to form a metal wiring layer 26, which is used as a source and drain connection wiring layer 26.
The connection wiring layer 26 is wired on the semiconductor substrate and is connected to another element such as another MOS type semiconductor device.

Problems to be Solved by the Invention In the above-described conventional MOS semiconductor device, since the source and drain regions are formed on the semiconductor substrate surface and the connection portions with the source and drain electrodes are formed, the semiconductor substrate surface is occupied. The large area hinders high density. Also, the source and drain connection wiring is MOS
Since the wiring is formed on the semiconductor device of the type, there is a drawback that disconnection is likely to occur at a variation portion with the gate electrode or a variation portion with another wiring.

Means for Solving the Problems In order to solve the above problems, the present invention forms a gate electrode on a semiconductor substrate and then forms an opening in the semiconductor substrate to form source and drain regions on the sidewalls of the opening. And at the bottom of the gate electrode, and forming a connection portion with the source and drain electrodes on the side wall of the opening,
A semiconductor device is formed by embedding the source and drain connection wirings in the opening of the semiconductor substrate.

Effect According to the present invention, the source and drain regions and the connection with the metal wiring are formed on the sidewalls of the opening formed in the semiconductor substrate. Therefore, unlike the conventional case, the source and drain regions and the connection are formed on the surface of the semiconductor substrate. There is no need, and the area occupied by the semiconductor device on the surface of the semiconductor substrate may be small.

Further, since the source and drain connection wirings are embedded in the openings of the semiconductor substrate, the number of wiring layers on the semiconductor substrate is reduced, and the disconnection at the intersection with the gate electrode and the short circuit between the wiring layers are reduced.

Embodiment An embodiment of the present invention will be described with reference to FIG.

The element isolation layer 2 made of an insulating film is selectively formed on the one-conductivity-type semiconductor substrate 1. Next, a gate oxide film 3 and a polycrystalline silicon film 4 and a silicon nitride film 5 to be a gate electrode are formed on the semiconductor substrate 1 (FIG. 1A). Next, after forming a predetermined pattern on the silicon nitride film 5 and the polycrystalline silicon film 4 (FIG. 1B), heat treatment is performed in a high temperature oxidizing atmosphere,
A silicon dioxide film 6 is formed on the side wall of the polycrystalline silicon film pattern (FIG. 1C). Then, the exposed gate oxide film 3 is removed by etching to form an opening 7 in the exposed semiconductor substrate (FIG. 1D). Next, after forming an insulating film 8 such as a silicon dioxide film on the entire surface, a part of the insulating film 8 on the polycrystalline silicon film 4 and on the opening portion 7, that is, directly below the gate oxide film is removed to remove the insulating film 8. The crystalline silicon film and the semiconductor substrate 9 above the opening are exposed (FIG. 1F). Next, after forming a refractory metal film 10 of dungsten, titanium or the like on the entire surface (FIG. 1G), high temperature treatment is performed. By the heat treatment, the exposed regions of the polycrystalline silicon film and the semiconductor substrate and the refractory metal film react with each other to form silicide layers 11 and 12. The exposed region 9 of the semiconductor substrate, that is, the silicide layer 12 formed on the side wall of the opening is used as a source and a drain.

Then, a part of the refractory metal film 10 is selectively removed to form source and drain electrodes, and then, on the refractory metal film 10 in the openings below the silicide layer 12 formed on the side wall of the exposed semiconductor substrate. Then, an insulator film 13 such as a silicon dioxide film is buried and formed (FIG. 1H). Thus the source consisting of the membrane 10,
A MOS transistor is obtained in which the drain electrode wiring is formed below the source and drain regions.

As described above, according to the present invention, since the source and the drain are formed by the silicide layer on the side wall of the opening of the semiconductor substrate, the area occupied on the surface of the semiconductor substrate is small, and the source and the drain having a shallow junction are formed. A drain region can be formed, and a high density semiconductor integrated circuit can be formed. In addition, since the refractory metal film which is the source and drain electrode connecting wiring is buried in the opening formed in the semiconductor substrate, the wiring layer formed on the semiconductor substrate is small, and therefore the intersection with the gate electrode and other wirings are not formed. Since there are few intersections between the two, it is possible to form a semiconductor integrated circuit with less disconnection and short circuit and high yield.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining an embodiment of the present invention, and FIG. 2 is a process sectional view for explaining a conventional example. 1 ... Semiconductor substrate, 2,8,13 ... Insulator film, 3 ... Gate oxide film, 4 ... Polycrystalline silicon film, 5 ... Silicon nitride film, 6 ...
… Silicon dioxide film, 10 …… Refractory metal film, 11,12 …… Silicide layer.

Claims (1)

[Claims] 1. A gate electrode composed of a gate oxide film and a polycrystalline silicon film is selectively formed on a semiconductor substrate of one conductivity type,
Etching the semiconductor substrate using the gate electrode as an etching mask to form an opening, and forming an insulating film on the sidewall of the opening, and then forming a side wall of the semiconductor substrate in contact with the gate electrode And a step of forming a refractory metal on the entire surface, and a step of forming a silicide layer of the polycrystalline silicon film of the gate electrode and the exposed semiconductor substrate and the refractory metal by high temperature treatment. A method of manufacturing a semiconductor device, wherein the refractory metal is selectively etched to form a refractory metal pattern connected to a silicide layer on the semiconductor substrate.