GB2106319A - Semiconductor device fabricated using self alignment technique - Google Patents
Semiconductor device fabricated using self alignment technique Download PDFInfo
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- GB2106319A GB2106319A GB08227355A GB8227355A GB2106319A GB 2106319 A GB2106319 A GB 2106319A GB 08227355 A GB08227355 A GB 08227355A GB 8227355 A GB8227355 A GB 8227355A GB 2106319 A GB2106319 A GB 2106319A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract 9
- 150000004767 nitrides Chemical class 0.000 claims description 44
- 238000009792 diffusion process Methods 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000003990 capacitor Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 38
- 239000010409 thin film Substances 0.000 claims 7
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- 238000010438 heat treatment Methods 0.000 claims 1
- 238000001465 metallisation Methods 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000007687 exposure technique Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
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- 238000010894 electron beam technology Methods 0.000 description 3
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- 239000007924 injection Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005389 semiconductor device fabrication Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
A semiconductor device has an insulative film consisting of two layers, a silicon oxide layer (3) and a silicon nitride layer (4) in at least a portion of an area on a surface of a substrate (1) on which is a polycrystalline silicon layer (9), a metallized electrode (14) being provided in a window (12) which is formed by removing at least a portion of the two-layer insulative film (3,4) around the polycrystalline silicon layer (9) by a self-alignment technique using the polycrystalline silicon layer (9) and surrounding silicon oxide film layer (10) as a mask. Thus the metallized electrode which forms a base electrode of a transistor can be located close to the polycrystalline silicon layer which forms an emitter electrode of the transistor so that the base series resistance is materially reduced and a fast operation speed transistor can be provided. <IMAGE>
Description
SPECIFICATION
Semiconductor device and method for fabricating the same
The present invention relates to a semiconductor device fabricated in a self alignment technique and a method for fabricating the same.
In the digital circuit art, there is a strong demand for fast operating speed and high packing density. High speed and high packing density require similar technologies and it is true that the speed of a device is increased as junction capacitance and diffusion capacitance decrease by the micro-miniaturization of the device.
Accordingly, the development of microminiaturization technology for device structures of bipolar transistor and MOS transistors have been widely carried out.
A technique which directly contributes to the microminiaturization of the device structure is a lithography technique in the formation of a device pattern. However, as a result of the rapid trend of miniaturization of devices, it has become difficult to form a microminiature pattern by a conventional light exposure technique. An electron beam exposure method has been proposed to take place of the light exposure technique. The electron beam exposure method permits the formation of a pattern of less than one micron in width. However, since the electron beam exposure method needs processing for each device pattern, the processing speed is very low compared with the conventional light exposure technique which processes for each semiconductor wafer.Since a device pattern formation step (photoresist step) is carried out every time prior to an etching step or a diffusion step during a semiconductor device fabrication process, the slow processing speed in the photoresist step means that the entire processing time for the semiconductor device fabrication is very long.
Another important step in the microminiaturization of the device is pattern registration between the photoresist step and the previous step. That is, in one step, a pattern is to be formed in registered relation to a pattern formed in the previous step. Since the accuracies of etching and diffusion in those steps are limited, the accuracy of the pattern registration is also limited. Accordingly, a certain margin must be left between the patterns of those steps. This margin is usually called a mask alignment margin and it needs at least one micron. While the mask alignment margin for two contiguous steps is of the order described above, the mask alignment margin of non-contiguous steps is larger because of the accumulation of the masking alignment margins.
Thus, the microminiaturization of the device has become difficult when one merely relies on the conventional light exposure technique.
Another effective method for the microminiaturization than the light exposure technique is a self-alignment technique, in which a pattern is not formed by using a mask but a pattern per se formed on a semiconductor wafer in one step is used as a mask in the next step.
Accordingly, the self-alignment technique does not need the mask and hence the mask alignment margin is not necessary. Therefore, utilizing a selfalignment method a microminiature device can be fabricated with the conventional light exposure technique.
The present invention to be described later provides a microminiature device structure and a fabrication method therefor using the selfalignment technique. Prior to the description of the present invention, the prior art technologies and the problems thereof are explained. For the sake of simplification of the description and the drawings, conductivity types of respective semiconductor layers and materials thereof are specified and the description for the structures of those semiconductor layers which are not directly related to the present invention is omitted. (The same is true in the description of the present invention.)
Fig. 1 shows a sectional view of a conventional self-alignment structure 12L device. This device is shown, for example, in IEEE Transactions on ED,
Vol. ED-27, No. 8, August 1980.In Fig. 1, numeral 1 denotes an n-type semiconductor (silicon) substrate, numeral 2 denotes a p-type semiconductor (silicon) layer, numeral 5 denotes a silicon dioxide film (hereinafter referred to as an oxide layer), numeral 9 denotes a polycrystalline silicon layer, numeral 10 denotes a silicon dioxide film layer (hereinafter referred to as an oxide film layer), numeral 11 denotes a high concentration n-type semiconductor region (diffusion layer), numeral 13 denotes a high concentration p-type semiconductor layer (diffusion layer) and numeral 14 denotes an electrode metallization (metallized electrode).
In the 12L structure shown in Fig. 1, a collector electrode is taken out of the polycrystalline silicon layer 9 and a base electrode is taken out of the metallization 14. In this structure, in order to take out the base electrode from an area very close to the collector electrode to reduce base resistance, an opening for the base terminal is formed by the self-alignment technique using the polycrystalline silicon layer 9 which is to serve as the collector terminal and the oxide film layer 10 formed thereon as a mask, and the metallized electrode 14 is formed therein. The formation of the opening by the self-alignment technique is carried out in the following steps.
The polycrystalline silicon layer is deposited on the exposed silicon layer 2 and high concentration impurities are doped into the polycrystalline silicon layer. Then the polycrystalline silicon layer is patterned to form the polycrystalline silicon layer 9 shown in Fig. 1. Thereafter, oxidation is performed so that the thick oxide film layer 10 is formed in the polycrystalline silicon layer doped with the high concentration impurities and the thin oxide film is formed in the low concentration silicon layer 2. Then, the oxide film is etched under such a condition that the thin oxide film is entirely removed while the thick oxide film is left.
In this manner, the opening for the base electrode is formed by the self-alignment technique.
In this prior art structure, the following problem is encountered in areas 100 shown in Fig. 1.
First, it is difficult to form the oxide film layer 10 of any desired thickness. That is, it is difficult to make a clear distinction between the thicknesses of the high concentration polycrystalline silicon layer and the low concentration silicon layer during the oxidization step. In the etching step after the oxidization, the oxide film layer 10 is thinned because it is also etched simultaneously with the oxide film on the silicon layer 2. As a result the possibility of shorting between the polycrystalline silicon layer 9 and the metallization electrode 14 increases.
Next, it is only the thickness of the oxide film layer 10 that defines the distance between the metallization electrode 14 and the polycrystalline silicon layer 9 or the diffusion layer 1 The thickness of the oxide film layer 10 is usually at most 1 oooA-s000A while the diffusion layer 11 extends downward as well as laterally.
(Assuming that the depth of the diffusion layer is 300 > 5000 , the lateral extension is approximately 2400-4000A.) Accordingly, the possibility of shorting between the metallization electrode 14 and the diffusion layer 1 1 is very high.
The possibility of degradation of breakdown voltage characteristic by the high concentration diffusion layers 13 and 1 1 is also high because it is not possible to set the distance between the high concentration diffusion layers 13 and 11 to a desired distance.
The prior art device thus has many problems which result in fatal defects in the integrated circuit.
It is an object of the present invention to provide a semiconductor device structure having excellent electrical characteristics and a method for fabricating the same.
In accordance with the technique of the present invention, it is possible to form a conventional bipolar transistor and an 12L device (Integrated Injection Logic) in one substrate so that an analog-digital hybrid integrated circuit can be formed at a high packing density.
In seeking to achieve the above object, a semiconductor device of the present invention is constructed as shown below. An insulative film consisting of two layers, a silicon dioxide (SiO2) film and silicon nitride (Si3N4) film, is present in at least a portion of an area between a silicon layer and a polycrystalline silicon layer a window is formed in at least a portion of the two-layer insulative film at the periphery of the polycrystalline silicon layer by the self-alignment technique using the polycrystalline silicon layer and the surrounding silicon dioxide film layer as a mask, and a metallization electrode is formed in the window.
The embodiments of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
Fig. 1 shows a sectional view of a prior art selfalignment structure 12L device,
Figs. 2a to 2f show structural sectional views for illustrating fabrication steps of an npn transistor in one embodiment of the present invention,
Figs. 3a to 3d, Figs. 4a to 4c and Figs. 5a to 5c show structural sectional views for illustrating fabrication steps of lateral npn transistors in other embodiments of the present invention,
Figs. 6a and 6b show structural sectional views for illustrating fabrication steps of Schottky diode in another embodiment of the present invention,
Fig. 7 shows a structural sectional view of a resistive device in a further embodiment of the present invention,
Figs. 8a to 8c show structural sectional views of a capacitive device in another embodiment of the present invention,
Figs. 93 to 9c shows structural sectional views of an 12L device in another embodiment of the present invention,
Fig. 1 Oa shows a structural sectional view of a
Schottky-clamped transistor in a further embodiment of the present invention, and
Fig. 1 Ob shows an equivalent circuit thereof.
Figs. 2a to 2f show a first embodiment of the present invention and it shows the structural sectional views of a semiconductor device of the present invention in the sequence of major fabrication steps. The present embodiment is directed to a vertical npn transistor. The like numerals to those shown in Fig. I denote the like or equivalent elements.
In Fig. 2a, numeral 1 denotes an n-type semiconductor (silicon) substrate, numeral 2 denotes a p-type semiconductor (silicon) layer for forming a base region of the npn transistor, numeral 3 denotes a thin (e.g. approximately 500 ) silicon dioxide film (hereinafter referred to as an oxide film), numerals 4 and 6 denote silicon nitride films (hereinafter referred to as nitride films) and numeral 5 denotes a thick (e.g.
approximately one micron) oxide film. The n-type semiconductor substrate 1 is formed on a p-type semiconductor substrate (not shown) of an integrated circuit device, and a high concentration n-type buried layer (not shown) for reducing a collector resistance and a device isolation layer (not shown) should be formed although they are omitted for the sake of simplification of the drawing and description as mentioned above. In
Fig. 2a, the nitride films 4 and 6 are selectively formed in order to use the nitride films which were used as a mask in the formation of the thick oxide film 5, in the subsequent step. When the thicknesses of the nitride films 4 and 6 are precisely controlled, the nitride films used for the selective oxidization may be removed and a new nitride film may be formed. In this case, the nitride films 4 and 6 shown in Fig. 2a are present on the entire surface.
In Fig. 2b, those portions (windows) 7 in the oxide film 3 and the nitride films 4 and 6 under which an emitter region and a collector region are to be formed are removed (formation of windows).
In Fig. 2c, after the formation of the windows, a polycrystalline silicon layer is formed on the entire surface and n-type impurities are doped into the polycrystalline silicon layer and then the polycrystalline silicon layer is patterned. Numerals 8 and 9 denote the polycrystalline silicon layers, the layer 8 being used as a collector in the subsequent step and the layer 9 being used as an emitter terminal. The pattern for the emitter terminal is larger than the emitter window 7 shown in Fig. 2b in order to prevent the underlying silicon layer from being exposed to the surface.
In Fig. 2d, after the step of Fig. 2c, the polycrystalline silicon layers 8 and 9 are oxidized.
Numeral 10 denotes oxide film layers formed by oxidizing the polycrystalline silicon layers. A first feature of the present invention resides in this step. Since the silicon layer other than the polycrystalline silicon layers in which the emitters and the collector are to be formed is covered with the nitride film 4, the oxide film does not grow in the oxidization of this step and only the polycrystalline silicon layers 8 and 9 are selectively oxidized. The oxide film layer 10 of the polycrystalline silicon layer is formed to be thicker (e.g. approximately 2000~5000 ) than the underlying oxide film 3.During the oxidization of the polycrystalline silicon, the n-type impurities doped therein diffuse from the polycrystalline silicon layer to the single crystal silicon layers (the p-type semiconductor layer 2 and the n-type semiconductor substrate 1 ) to form diffusion layers (n+ semiconductor layers) 11 (emitter and collector regions).
The deposition of the polycrystalline silicon layer after the formation of the windows in the step of Fig. 2b has been described. Alternatively, after the step of Fig. 2b, n-type semiconductor regions serving as the emitters may be formed by diffusion or ion implantation through the windows and then the polycrystalline silicon layer may be deposited in the step of Fig. 2c.
In Fig. 2e, the nitride film 4 and the oxide film 3 on a base region (the p-type semiconductor layer 2) are removed to form windows for a base terminal. This step is a second feature of the present invention. In this step, the nitride film 4 and the oxide film 3 on the base region are removed by the self-alignment technique using the polycrystalline silicon layer 9 serving as the emitter and the surrounding oxide film layer 10 as a mask. Since the oxide film 3 on the base region is sufficiently thinner than the oxide film layer 10 of the polycrystalline silicon layer, the nitride film and the oxide film on the base region are removed without substantially removing the oxide film layer 10. Thin oxide film 3 and nitride film 4 are left at a portion of a space between the polycrystalline silicon layer 9 and the base silicon layer (p-type semiconductor layer 2).The remaining oxide film and nitride film play an important role to maintain a proper spacing between the emitter window 7 and the base contact window 1 2 to prevent improper junction and shorting betwen the emitter and the base, as will be discussed later.
In Fig. 2f, high concentration boron impurities are diffused or ion-implanted through the window 12 having the nitride film and the oxide film removed therefrom to form a graft base (high concentration p-type semiconductor layer) 13.
Then, an electrode metallization layer 14 is deposited and it is patterned.
Through those steps, a vertical npn transistor (a multi-emitter transistor in the illustrated example) are formed.
In the present embodiment, as seen from Figs.
2e and 2f, no mask is needed for forming the base terminal contact openings (windows 12). The base terminal can be taken out from a point very close to the emitters and the entire surface of the transistor is covered with the metallized electrode 14.
Referring to the structure of the npn transistor of the present invention shown in Fig. 2f, the features and the advantages are discussed.
In this structure, the base terminal and the emitter terminal can be taken out by the selfalignment technique without requiring the mask alignment margin. Accordingly, the base electrode can be formed close to the emitter electrode. The base electrode is taken out from several points around the emitter region and those points are interconnected by a well-known metallized electrode. These features mean that base series resistance which is a barrier to fast operation speed of various transistors is significantly reduced. In a conventional multiemitter transistor, emitters which are far from the base terminal have high base series resistances and the operation speeds thereof are very slow.In the structure of the present invetnion, since the metallized electrode is taken out from the entire surface on the base region, all transistors of the multi-emitter transistor can operate at the same speed.
In the present structure, the high concentration p-type region for the graft base 13 can be formed by the self-alignment technique, as is done to take out the base metallized electrode. This also provides a significant effect to reduce the base resistance.
The capability of forming the base and the emitter by the self-alignment technique means that no mask registration is necessary and no mask alignment margin is necessary. Accordingly, a microminiature device can be readily fabricated.
In the present structure, since the emitter is formed by the polycrystalline silicon, the conductivity type is n for the npn transistor. As is well known, film resistance of an n-type polycrystalline silicon layer can be made significantly lower than that of a p-type.
Accordingly, in the transistor having the polycrystalline silicon layer as the emitter like the present structure, this layer can be used as a crossunder wiring. In a transistor having the polycrystalline silicon layer as the base, the resistance can not be reduced because the conductivity type of the polycrystalline layer is 9 and it is difficult to use this layer as the cross wiring. Thus, the capability of using the polycrystalline silicon layer as the cross wiring in the present invention is very significant in constructing the integrated circuit. In general, the larger the scale of the ingrated circuit is, the more rapidly the wiring area in the ingrated circuit increases so that it occupies much more area than the device area.In such a case, the advantage of the polycrystalline silicon layer of the present invention (what is more, the polycrystalline silicon layer is not formed for the purpose of wiring but it is formed simultaneously with the formation of the emitter) is particularly significant and it plays an important role in reducing the size of the integrated circuit.
As described above, the problems encountered in the prior art include improper junction and shorting between the base and the emitter. When the base and the emitter are formed by the selfalignment technique, an improper junction is caused by the contact of the base and emitter high concentration semiconductor layers.
Furthermore, when the base terminal window is too closely located to the emitter region, the base terminal metallization often shorts to the emitter due to the lateral diffusion of the emitter semiconductor layer. In accordance with the present invention, as shown in Figs. 2e and 2f, the spaced distance between the emitter and the base electrode is maintained at a proper distance by the nitride film 4 and the oxide film 3.
Accordingly, the problems encountered in the prior art self-alignment type transistor are avoided.
The features of the above process are now described.
In the present embodiment, as shown in Figs.
2a to 2f, the nitride film 4 is left on the base and it is used during the oxidization of the emitter polycrystalline silicon layer to prevent the base terminal area on the base from being oxidized.
The mask is used in patterning the emitter polycrystalline silicon layer. The pattern is formed to be slightly larger than the emitter diffusion window (window 7 in Fig. 2b). This offers a diffusion margin between the base and the emitter in the subsequent step.
Figs. 3a to 3d show steps of a second embodiment of the present invention in the sequence of the steps. It relates to a lateral pnp transistor which is to be co-existent with the npn vertical transistor shown in the first embodiment (Figs. 2a to 2f). The steps shown in Figs. 3a to 3d start from the step corresponding to the step of
Fig. 2d.
For the npn vertical transistor, the emitter window is formed in the step of Fig. 2b. In the step of Fig. 3a, the window is not formed but the polycrystalline silicon layer is patterned while the nitride film 4 and the oxide film 3 are left under the polycrystalline silicon layer and it is oxidized to form an oxide film layer 10. In this embodiment, the p-type semiconductor layer (corresponding to the p-type layer 2 in Fig. 2a) is not formed under the nitride film 4 and the oxide film 3.
In Fig. 3b, the step is identical to the graft base formation step of the npn vertical transistor. The nitride film 4 and the oxide film 3 are removed by using the polycrystalline silicon layer 9 and the oxide film layer 10 as a self-alignment mask and a high concentration p-type semiconductor layer (diffusion layer) 13 is formed.
In Fig. 3c, a metallized electrode 14 is formed.
Through those steps, the lateral pnp transistor is formed.
For the lateral pnp transistor, the polycrystalline silicon layer 9 is floated or a potential is applied thereto. When the metallized electrode 1 4a serving as the emitter of the lateral pnp transistor is connected to the polycrystalline silicon layer 9, a parasitic channel is effectively prevented. The structure therefor is shown in Fig.
3d.
In Fig. 3d, the metallized electrode 14 is connected to the polycrystalline silicon layer 9 at a point (connection point) 16. This allows the easy fabrication without increasing the device size.
Figs. 4a to 4c show steps of a third embodiment of the present invention in the sequence of the steps. Like the second embodiment, the present embodiment relates to a lateral pnp transistor.
In Fig. 4a, a p-type semiconductor layer 2 which is identical to the intrinsic base of the npn transistor is formed under the nitride film 4 and the oxide film 3. Then, a polycrystalline silicon layer 9 is formed across the p-type semiconductor layers 2 and it is oxidized to form an oxide film layer 10.
In Fig. 4b, like the graft base formation step of the npn transistor, high concentration p-type impurities are doped using the polycrystalline silicon layer 9 and the oxide film layer 10 as a self-alignment mask to form a high concentration p-type semiconductor layer 13.
In Fig. 4c, a metallized electrode 14 is finally formed.
The features of the present structure are described below.
In the present structure, the base width of the pnp transistor can be shortened. In the structure shown in Fig. 3, the base width cannot be reduced because the emitter and the collector are formed by the high concentration deep p-type semiconductor layers. In addition, the base width is restricted by the distance (I) between the emitter and collector metallized electrodes because those electrodes 14 must cover the electrode windows. On the other hand, in the structure of Fig. 4, the base width is determined by the low concentration shallow p-type semiconductor layer 2 and hence the base width can be reduced. In the present embodiment, the distance (I) between the metallized electrodes can be maintained by the polycrystalline silicon layer 9. Thus, the performance of the pnp transistor of the present invention is materially improved.
Figs. 5a to 5c show steps of a fourth embodiment of the present invention in the sequence of the steps. The present embodiment also relates to a lateral pnp transistor but it is intended to attain a better performance than the third embodiment (Fig. 4).
In Fig. 5a, a low concentration shallow p-type semiconductor layer 2 which will serve as the intrinsic base of the npn transitor is formed under the nitride film 4 and the oxide film 3. A polycrystalline silicon layer 9 is then patterned and oxidized to form an oxide film layer 10. The nitride film 4 and the oxide film 3 of an area 18 window area) are removed by using a photoresist 17 as a mask to form a window. The nitride film 4 and the oxide film 3 are removed by the selfalignment technique using the polycrystalline silicon layer 9 as a mask. Then, n-type impurities are ion-implanted or diffused after the removal of the photoresist. In this case, it is not the photoresist film but the polycrystalline silicon layer and the thick oxide film 5 that serve as the actual mask for the ion implantation or the diffusion.Therefore, precision of the alignment of the mask used is not necessary but the selfalignment technique is used.
In Fig. 5b, the nitride film 4 and the oxide film 3 not covered by the polycrystalline silicon layer 9 are removed and high concentration deep p-type semiconductor layers 13 and 13' are formed. The layers 13 and 13' may be formed simultaneously with the formation of the graft base of the npn transistor. It should be understood that the nitride film 4 and the oxide film 3 are removed by the self-alignment technique. The p-type semicondoctor layer 13 having an n-type semiconductor layer 19 formed therearound and the other p-type semiconductor layer 13' are simultaneously formed.
In Fig. 5c, a metallized electrode 14 is finally formed.
The features of the present embodiment are described below.
In the present structure, the p-type semiconductor layer 13 serves as the emitter and the p-type semiconductor layer 13' serves as the collector. Since the n-type semiconductor layer 19 and the p-type semiconductor layer 13 are of a double diffusion structure, sub-micron base width precision can be attained. For the pnp transistor, a high performance transistor having a high current amplification factor and a high operation speed is attained because the n-type semiconductor layer 19 which serves as the base layer has a concentration gradient directed from the emitter to the collector.
Figs. 6a and 6b show steps of a fifth embodiment of the present invention in the sequence of the steps. The present embodiment relates to a Schottky diode.
The step of Fig. 6a is identical to the steps of forming the emitter and the collector of the pnp transistor except that a p-type semiconductor layer 13 is formed to surround a polycrystalline silicon layer 9.
In Fig. 6b, an oxide film layer 10, the polycrystalline silicon layer 9, a nitride film 4 and an oxide film 3 are removed and a metallized electrode 14 is deposited on the entire surface.
The feature of the present embodiment is described below. In the prior art Schottky diode with a guard ring, the guard ring is formed by using a mask. Accordingly, a size of the Schottky diode is very large. In the structure of the present embodiment, since the guard ring (p-type semiconductor layer 13) is formed by the selfalignment technique, a guard ring of narrow width can be readily formed so that a Schottky diode of small size can be formed.
Fig. 7 shows a sixth embodiment of the present invention. The present embodiment relates to a resistor. Fig. 7 shows a structural sectional view of a resistor which can be formed simultaneously with the npn transistor of the present invention.
The present embodiment, a low concentration shallow p-type semiconductor layer 2 which is identical to the intrinsic base of the npn transistor is used as a resistor. The length of the resistor is determined by a polycrystalline silicon layer 9.
Windows for taking out terminals of the resistor are formed by the self-alignment technique using the polycrystalline silicon layer 9 as is done for the transistor, and high concentration p-type semiconductor layers 13 are formed therein and the terminals are taken out by metallized electrodes 14 through the same windows.
In the present embodiment, it is the p-type semiconductor layer 2 that determines the actual resistance, and a p-type semiconductor layer 13 is used to provide a low resistance ohmic contact between the metallized electrodes and the semiconductor layer 2. Since the p-type semiconductor layer 2 used as the intrinsic base forms a low concentration shallow junction, the present embodiment can provide a high resistance which has heretofore been difficult to attain in the integrated circuit.
The resistor of the present embodiment offers an advantage which has not been attainable by the prior art resistor. Most resistors in the prior art integrated circuits use different masks in the step of forming the semiconductor region serving as the resistor layer and the step of forming the windows for taking out the electrodes. As a result, the mask alignment margin for registering the masks is necessary and the semiconductor layer area must be designed to be larger than the metallized electrode take-out window. As a result, the resistance is usually deviated from the designed value by the turn-around effect of the current from the semiconductor layer around the metallized electrode take-out window.
In the present embodiment, since the electrode take-out window is formed by the self-alignment technique with the underlying semiconductor layer 13, the turn-around effect of the current at the metallized electrode end is minimized and the design of a precise resistor is allowed.
Figs. 8a to 8c show a seventh embodiment of the present invention. The present embodiment relates to a capacitor. Three structures of integrated capacitor are shown in Figs. 8a to 8c.
Fig. 8a shows a structure of a capacitor having an insulative film (a nitride film 4 and an oxide film 3) between a polycrystalline silicon layer 9 and a semiconductor layer (semiconductor substrate 1).
In accordance with the present invention, the capacitor having the insulative film can be readily formed. Since a dielectric constant of the nitride film 4 is as approximately twice as large as that of the oxide film, a large capacitance can be attained with a small area.
Fig. 8b shows a structure of a capacitor having an insulative film (a nitride film 4 and an oxide film 3) between a polycrystalline silicon layer 9 and a semiconductor layer (silicon layer 2).
The present structure has the same advantage and feature as the structure of Fig. 8a. By utilizing the semiconductor layer (silicon layer 2), the loss resistance of the capacitor at one electrode is reduced. In the structure of Fig. 8a, since the ntype semiconductor substrate 1 is used as one of the electrodes, respective capacitors must be isolated by isolation layers when a number of capacitors are needed. As a result, the size increases. In addition, the parasitic capacitance to the underlying p-type substrate (not shown) is large. In the present embodiment of Fig. 8b, such problems are avoided because the p-type semiconductor layer 2 is used as one electrode and the parasitic capacitance included is only a junction capacitance between the p-type semiconductor layer 2 and the n-type semiconductor substrate 1.Since the impurity concentration of the p-type semiconductor layer 2 is low, the parasitic capacitance is low.
Fig. 8c shows a structure of a capacitor which has an oxide film layer 10 between a polycrystalline silicon layer 9 and a metallized electrode 14 in addition to the structure shown in
Fig. 8b. With this structure, a larger capacitance is obtained for a given area.
While the nitride film 4 and the oxide film 3 are used as the insulative films on the capacitors in the above embodiments, it should be understood that the nitride film 4 of the capacitor may be removed to form a capacitor having an insulative film formed only by the thin oxide film 3.
Figs. 9a to 9c show an eighth embodiment of the present invention. The present embodiment relates to an 12L device. Three structures shown in
Figs. 9a to 9c are now explained.
By combining the npn transistor shown in the embodiment of Figs. 3 to 5, the 12L structures shown in Figs. 9a to 9c can be readily constructed.
It should be understood that the advantages of the npn transistor and the pnp transistor shown in the embodiments of Figs. 2 to 5 are directly applicable to the 12L structures of the present embodiment. In addition, the 12L structures of the present embodiment have important advantages as described below.
In the 12L structure, the npn transistor uses the upper n-type semiconductor region 11 as the collector. Such an inversely operated transistor usually has a low current amplification factor because only those electrons injected from the emitter region (substrate 1) to the base p-type region which are injected from an area immediately below the collector region 11 reach the collector to produce a collector current and almost all of the electrons injected from other areas result in a base current. As a result, in order to raise the current amplification factor of the inversely operated transistor, it is necessary to bring the ratio of areas of the collector region (11) and the base region (p-type semiconductor layers 2, 13) as close to one as possible.It is also necessary to increase the concentration of the base region other than the area immediately below the collector region to reduce the injection of the electrons to the base region.
In the present embodiment, since the base terminal is taken out by the self-alignment technique, it is possible to materially reduce the area of the base region other than the collector region. Since the high concentration p-type region is formed in the base terminal take-out area, it is possible to raise the current amplification factor of the npn transistor.
The 12L device is a non-input and multi-output logic circuit and it needs a number of collector terminals. In the prior art 12L structure having a number of collector output terminals, the effective current gain of collectors located far from the pnp transistor decreases in a large current by the effect of the base series resistance and hence the operation speed of the device is very low. In the 12L device, the high base series resistance causes extremely adverse affect to the operation margin and the operation speed.
In the 12L structure of the present embodiment, since the base terminal is taken out from a point very close to the respective collectors by the metallized electrode as shown in Fig. 9, the base series resistance is negligibly small and variation of characteristic by the collector location is avoided. This means that the operation speed of the integrated circuit can be further increased because all collectors can be operated at the same high speed whereas the operation speed of the prior art 12L structure in the integrated circuit is limited by the slowest operation speed collector.
In the 12L structure of the present embodiment, since the polycrystalline silicon layer is used to take out the collector terminals, the polycrystalline silicon layer can be used as a wiring layer when wiring to an adjacent gate is required, as opposed to the case where the polycrystalline silicon layer is used to take out the base terminal. This presents a large freedom in the design of layout including the wiring of the integrated circuit and an advantage of reducing the chip size.
Fig. 10 shows a ninth embodiment of the present invention.
The present embodiment relates to a structure of a Schottky-clamped transistor which is a combination of the npn transistor shown in Fig. 2 and the Schottky diode shown in Fig. 6.
Fig. 1 Oa shows a structural sectional view of the Schottky-clamped transistor and Fig. 1 Ob shows an equivalent circuit thereof.
As seen from the structural sectional view of
Fig. 1 Oa, the present transistor can be readily constructed by combining the transistor shown in
Fig. 2 and the Schottky diode shown in Fig. 6. In
Fig. 1 Oa, a junction 20 is a Schottky diode formed by the metallization 14 and the silicon layer. The advantages described in the embodiments of Figs.
2 and 6 are directly applicable to the present structure.
While the advantages of the present invention have been described with respect to various embodiments, it should be understood that the scope of the present invention is not restricted to the illustrated embodiments but many other modifications of the embodiments are included in the scope of the present invention.
For example it should be understood that the present invention is applicable when the conductivity type of the semiconductor layers shown in the embodiments are changed from the p-type to the n-type and vice versa. Any combination of the embodiments of the present invention is also within the scope of the present invention. While the p-type substrate and the ntype semiconductor buried layer which are conventionally used in the integrated circuit are omitted in the illustration of the embodiments of the present invention in order to clarify the gist of the present invention, it should be understood that the structure which includes the p-type substrate and the n-type semiconductor buried layer is within the scope of the present invention.
Claims (18)
1. A semiconductor device comprising:
(a) a semiconductor substrate;
(b) a first insulative layer formed on said
substrate and having a predetermined
pattern;
(c) a second insulative thin film formed on said
substrate;
(d) a third insulative thin film formed on said
second insulative thin film;
(e) a polycrystalline semiconductor layer of a
predetermined pattern formed on said third
insulative thin film;
(f) a fourth insulative thin film formed by
converting a surface of said polycrystalline
semiconductor layer by heat treatment;
(g) an opening formed in said second and third
insulative thin films by using said fourth
insulative thin film as a mask; and
(h) an electrode formed in said opening.
2. A semiconductor device comprising:
an insulative film consisting of two layers, of a silicon oxide film and a silicon nitride film, formed in a space occuping at least a portion of an area between a silicon layer and a polycrystalline silicon layer formed in a predetermined area on a surface of a substrate containing said silicon layer; and
a metallized electrode formed in a window formed by removing at least a portion of said twolayer insulative film around said polycrystalline silicon layer by a self alignment technique using said polycrystalline silicon layer and a surrounding silicon oxide film as a mask.
3. A method for fabricating a semiconductor device comprising the steps of:
(a) forming a silicon oxide film on a surface of a
substrate;
(b) forming a silicon nitride film on said silicon
oxide film;
(c) forming a window in an insulative film
consisting of two layers of said silicon nitride
film and said silicon oxide film.
(d) depositing a polycrystalline silicon layer to
cover said window and patterning said
polycrystalline silicon layer;
(e) oxidizing said polycrystalline silicon layer to
form a silicon oxide film layer surrounding
said polycrystalline silicon layer;
(f) forming a window in said two-layer
insulative film by a self-alignment technique
using said polycrystalline silicon layer and
said surrounding silicon oxide film layer as a
mask; and
(g) forming a metallized electrode in said
window.
4. In a vertical npn transistor, a structure of a semiconductor device comprising:
a base region having a low concentration ptype semiconductor region and a high concentration p-type semiconductor region;
at least one emitter region formed in said low concentration p-type semiconductor region;
a polycrystralline silicon layer formed on said emitter region to cover an emitter region opening through which an emitter terminal is taken out;
a nitride film and a thin oxide layer formed between an area of said polycrystalline silicon layer larger than said emitter region opening and said underlying base region;
said polycrystalline silicon layer being covered with an oxide film layer; and
a metallized electrode for taking out a base terminal from said high concentration p-type semiconductor layer, said metallized electrode being arranged over said dioxide film layer on said emitter electrode polycrystalline silicon layer.
5. A semiconductor device including a lateral pnp transistor capable of being formed on the same substrate in the same process as said semiconductor device according to Claim 4, said pnp lateral transistor comprising:
an oxide film and a nitride film formed on an n type semiconductor layer of a base region;
a polycrystalline silicon layer formed on said nitride film and covered with an oxide film layer having the same width;
an emitter region and a collector region formed by p-type semiconductor regions; and
a metallized electrode taken out of said p-type semiconductor region.
6. A semiconductor device according to Claim 5 wherein said p-type semiconductor regions are high concentration p-type semiconductor layers.
7. A semiconductor device according to Claim 5, wherein said p-type semiconductor regions are composite structures of low concentration p-type semiconductor layers (regions) and high concentration p-type semiconductor layers (regions), the distance between said low concentration p-type semiconductor regions being shorter than the distance between said high concentration p-type semiconductor regions and shorter than the width of said polycrystalline silicon layer.
8. A semiconductor device according to Claim 5, wherein said base region and said emitter region are formed by diffusion or ion implantation through a common window, and said emitter region is a high concentration p-type semiconductor region and said collector region includes a low concentration p-type semiconductor region and a high concentration ptype semiconductor region, said low concentration p-type collector region being located closer to the emitter than said high concentration p-type collector region.
9. A semiconductor device including a resistor device capable of being formed by the same process on the same substrate as said semiconductor device according to Claim 4, said resistor device comprising:
a resistor region consisting of a low concentration p-type semiconductor region and a high concentration p-type semiconductor region;
an oxide film and a nitride film of the same length formed on said low concentration p-type semiconductor area;
a polycrystalline silicon layer formed on said nitride film and covered with an oxide film layer having the same length as said nitride film; and
metallized electrodes taken out from the entire surface of said high concentration p-type semiconductor region.
10. A semiconductor device including a capacitor device capable of being formed in the same process on the same substrate as said semiconductor device according to Claim 4, said capacitor device comprising:
an insulative film made of a nitride film and an oxide film or the oxide film;
a first electrode made of a polycrystalline silicon layer;
a second electrode made of an n-type semiconductor region (substrate 1 ) or a low concentration p-type semiconductor region and a high concentration p-type semiconductor region, or a metallized electrode.
1 1. A semiconductor device comprising:
a guard ring made of a high concentration ptype semiconductor region; and
a diode having a Schottky junction between a metallized electrode and an n-type semiconductor region (substrate 1).
12. A semiconductor device having a combination of the semiconductor device according to Claim 4 and the semiconductor device according to Claim 11.
13. A semiconductor device having an integrated 12L structure of the semiconductor device according to Claim 4 and the semiconductor device according to any one of
Claims 5 to 8.
14. A method for fabricating the semiconductor device according to any one of
Claims 4 to 13, comprising the steps of:
forming windows in the thin oxide film and the overlying nitride film at the emitter area and the collector area of the npn transistor and depositing the polycrystalline silicon layer thereon;
depositing the polycrystalline silicon layer on the pnp transistor and the resistor without removing the oxide film and the nitride film;
patterning said polycrystalline silicon layer to cover the emitter window or the collector window or both of said npn transistor and expose the nitride film under the polycrystalline silicon layer;
oxidizing only the polycrystalline silicon layer;
removing said thin oxide film and said nitride by a self-alignment technique using the oxidized polycrystalline silicon layer as a mask;;
forming electrode take-out regions for the external base region of the npn transistor and the emitter and collector regions of the pnp transistor and the resistor by high concentration p-type semiconductor layers; and
depositing metal on said electrode take-out regions and patterning the metallized areas to take-out the base terminal of the npn transistor, the emitter and collector terminals of the pnp transistor and the terminals of the resistor by a self-alignment technique.
1 5. A method for fabricating the semiconductor device according to Claim 14 wherein said pnp transistor is fabricated by the steps of:
forming a low concentration p-type semiconductor region uniformly on an area between the emitter and the collector prior to the formation of the high concentration p-type semiconductor region;
masking the collector region such that the area to serve as the emitter is defined by the oxidized polycrystalline silicon layer by a self-alignment technique;
forming the n-type semiconductor region in the area to serve as the emitter;
removing the mask; and
forming the high concentration p-type semiconductor layers to form the collector and the emitter of the pnp transistor.
1 6. A method for fabricating a Schottky diode comprising the steps of:
forming a high concentration ptype semiconductor region in a semiconductor substrate by using an oxidized polycrystalline silicon layer formed on the semiconductor substrate as a mask;
removing said polycrystalline silicon layer and underlying a nitride film and a thin oxide film on the substrate; and
thereafter depositing metal on a surface of said semiconductor substrate.
17. A semiconductor device substantially as described herein with reference to any of Figs. 2 to 10 of the drawings.
18. A method of making a semiconductor device substantially as described herein with reference to Figs. 2 to 10 of the drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56150741A JPS5852817A (en) | 1981-09-25 | 1981-09-25 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2106319A true GB2106319A (en) | 1983-04-07 |
| GB2106319B GB2106319B (en) | 1985-07-31 |
Family
ID=15503396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08227355A Expired GB2106319B (en) | 1981-09-25 | 1982-09-24 | Semiconductor device fabricated using self alignment technique |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5852817A (en) |
| KR (1) | KR860000612B1 (en) |
| DE (1) | DE3235467A1 (en) |
| GB (1) | GB2106319B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2172744A (en) * | 1985-03-23 | 1986-09-24 | Stc Plc | Semiconductor device fabricated using self-augment technique |
| US4873199A (en) * | 1986-03-26 | 1989-10-10 | Stc Plc | Method of making bipolar integrated circuits |
| CN103021936A (en) * | 2012-12-28 | 2013-04-03 | 杭州士兰集成电路有限公司 | Bipolar circuit manufacture method |
| CN110335896A (en) * | 2019-05-09 | 2019-10-15 | 中国电子科技集团公司第二十四研究所 | A kind of production method of the polysilicon emitter structure of adjustable current gain |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6074477A (en) * | 1983-09-29 | 1985-04-26 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| EP0180363B1 (en) * | 1984-10-31 | 1994-04-13 | Texas Instruments Incorporated | Horizontal structure transistor and method of fabrication |
| JP2001217317A (en) * | 2000-02-07 | 2001-08-10 | Sony Corp | Semiconductor device and manufacturing method therefor |
| JP4259247B2 (en) * | 2003-09-17 | 2009-04-30 | 東京エレクトロン株式会社 | Deposition method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3745647A (en) * | 1970-10-07 | 1973-07-17 | Rca Corp | Fabrication of semiconductor devices |
| DE2414520A1 (en) * | 1973-07-30 | 1975-02-20 | Hitachi Ltd | Process for the production of tightly adjacent electrodes on a semiconductor substrate |
| JPS53132275A (en) * | 1977-04-25 | 1978-11-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its production |
-
1981
- 1981-09-25 JP JP56150741A patent/JPS5852817A/en active Pending
-
1982
- 1982-09-24 KR KR8204306A patent/KR860000612B1/en active
- 1982-09-24 DE DE19823235467 patent/DE3235467A1/en not_active Withdrawn
- 1982-09-24 GB GB08227355A patent/GB2106319B/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2172744A (en) * | 1985-03-23 | 1986-09-24 | Stc Plc | Semiconductor device fabricated using self-augment technique |
| GB2172744B (en) * | 1985-03-23 | 1989-07-19 | Stc Plc | Semiconductor devices |
| US4873199A (en) * | 1986-03-26 | 1989-10-10 | Stc Plc | Method of making bipolar integrated circuits |
| CN103021936A (en) * | 2012-12-28 | 2013-04-03 | 杭州士兰集成电路有限公司 | Bipolar circuit manufacture method |
| CN110335896A (en) * | 2019-05-09 | 2019-10-15 | 中国电子科技集团公司第二十四研究所 | A kind of production method of the polysilicon emitter structure of adjustable current gain |
Also Published As
| Publication number | Publication date |
|---|---|
| KR840001773A (en) | 1984-05-16 |
| KR860000612B1 (en) | 1986-05-22 |
| GB2106319B (en) | 1985-07-31 |
| DE3235467A1 (en) | 1983-04-14 |
| JPS5852817A (en) | 1983-03-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 711A | Proceeding under section 117(1) patents act 1977 | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19950924 |