DE2414520A1 - Process for the production of tightly adjacent electrodes on a semiconductor substrate - Google Patents

Description

Process for the production of closely spaced electrodes on a semiconductor substrate

The invention relates to a method for the production of two closely spaced electrodes on a semiconductor substrate, in particular those electrodes that are connected to different areas of the semiconductor substrate.

When producing circuits on semiconductor substrates, it is necessary to produce electrodes with different semiconductor areas are connected. In many cases it is desirable to have the electrodes in this way to be brought together as closely as possible without short-circuits. This enables, for example, good high-frequency characteristics or high integration densities can be achieved.

According to the state of the photo-etching process, the amount required is Electrodania minimum distance 5-10 um. this Distance is by "the limits of accuracy" in the case of

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Mask manufacture and mask transfer and the accuracy of photo-etching set.

For example, it must be used in the manufacture of bipolar transistors the distance ζwisehen of the emitter electrode and the base electrode due to the limits of the mask accuracy and the etching resolution 5-10 µm. be. the The base of such a bipolar transistor must therefore be larger, namely by about 3 to 4 times that due to the technologically achievable accuracy required.

In the same way, when producing resistors by diffusion, * a minimum distance d is required to maintain between the two contacts, which corresponds to the technological limits of 5-10 μm. In particular When producing low-ohmic resistors by diffusion processes, the width of the diffusion zone must be larger than required by the accuracy limits be formed. In this case, too, the possible integration density must be sacrificed. Simultaneously with that The problem of parasitic capacitances arises as a result of the abandonment of the integration density that can be achieved in principle.

The same considerations apply, for example, to the Manufacture of junction capacitors and junction field effect transistors by.

It is therefore an object of the invention to provide an improved method of making electrodes which are arranged with only the smallest electrode spacing from one another and are assigned to different semiconductor areas.

Another object of the invention is to increase the degree of integration of integrated switching network elements in one

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integrated circuit.

Another object of the invention is to provide a transistor with a low base resistance r 1 and a low base-collector junction capacitance C _c .

Another object of the invention is to provide one low resistance in an integrated circuit, without this element reducing the integration density will.

It is also an object of the invention to provide a junction field effect transistor with reduced parasitic capacitance and with reduced channel resistance.

After all, it's another goal of the. Invention, a junction capacitor with a high quality factor Q and low series resistance.

The invention is therefore based on the object of improving the state of the art and, in particular, a method to create adjacent electrodes, the distance from each other substantially below that by the current etching technique set distance limit of 5 - 10, im so that the integration density of integrated circuits does not need to be reduced even if when these circuits recognized difficult elements, such as low-ohmic resistors, junction capacitor en, transistors with low base-collector capacitance or junction field effect transistors.

According to the invention, a method is used to achieve this object proposed of the type mentioned at the outset, which is characterized in that the substrate surface is in one

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Covering the insulating layer makes a hole that a first electrode is created through this hole that the surface of the first electrode produced in this way is converted into an insulator that one in the insulator layer Another hole is produced, the insulating substance produced on the first electrode at least as part of a mask is used, and that a second electrode is created through this second hole.

The subject of the invention is therefore a method for the production of at least two electrodes up and down Subregions of a semiconductor substrate, these regions having at least one semiconductor region, if appropriate but also include several semiconductor regions. The surface of the semiconductor substrate is covered with an insulator layer, which at the same time acts as a protective layer. To produce the first electrode, a hole or a through-hole is produced in this insulator layer. By The first electrode is produced through this hole in the semiconductor substrate. Then the surface made this first electrode insulating; one thus preferably forms through on the surface of the first electrode chemical reaction from the electrode material an insulator layer. Then for the second electrode in the insulator layer a second hole or a second through-hole is provided on the surface of the semiconductor substrate. The insulating surface layer of the first electrode serves as a mask or at least as a part or component a mask. The second electrode then becomes in the semiconductor material through the second hole produced in this way generated. In this way it is achieved that the two electrodes produced in this way are practically immediate may be arranged adjacent, but the insulating surface of the first electrode for the insulation of both electrode areas from each other.

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According to a preferred embodiment of the invention, the electrodes are directly on both sides of a p-n junction made, which is covered with an insulator layer. This electrode arrangement is on both sides of a barrier layer can be used advantageously in the production of, for example Bipolar transistors, junction field effect transistors or Junction capacitors. One of the two electrodes is connected to one of the semiconductor regions. During their production, an insulator layer is formed on the surface of the semiconductor substrate over the p-n junction generated between the first electrode and the semiconductor surface. The surface of the first electrode is then converted according to the invention into an insulator layer. Afterward becomes the insulator layer on the semiconductor region of the other conduction type, the insulator layer on the first electrode serving as a mask. A second electrode is connected to the semiconductor region of the other conductivity type through this second hole .

According to another preferred embodiment of the invention, a low-resistance produced by "diffusion processes" is used Provide the resistor with electrodes. The first electrode is placed through a hole in the insulator layer generated through the substrate surface. The surface of this electrode turns into an electrically non-conductive one Substance converted. The insulator protective layer will then selectively removed at a second location. An opening is thereby formed, with the insulating substance made of the material of the first electrode serves as at least part of a mask. The second electrode is then formed in this opening.

The invention is described in more detail below on the basis of exemplary embodiments in conjunction with the drawings.

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wrote. Show it:

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Figures la - lh in cross section various stages in the manufacture of a transistor according to the method of the invention;

Fig. 2

in cross-section that produced according to the stages of the figures la-lh Transistor;

FIGS. 3a-3h show, in cross section, part of a semiconductor substrate in the various ways Manufacturing stages according to the method of the invention in the manufacture of a junction capacitor ;

FIGS. 4a-4j show, in cross section, a semiconductor substrate with different manufacturing stages a junction field effect transistor made by the method of the invention ;

Fig. 5

the field effect transistor produced according to the stages of FIGS. 4a 4j under supervision;

FIGS. 6a-6h show the various stages of manufacture according to the invention in cross section for “a resistor produced by a diffusion process;

Fig. 7

a transistor in cross section

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according to the state of the art and

Fig. 8 in cross section one after

"Diffusion process produced Prior Art Resistance.

example 1

In the figures la to lh, an exemplary embodiment of the method of the invention is shown in cross section on the basis of manufacturing stages described on the way to manufacture a transistor.

(a) A high-resistance η-conductive epitaxial layer 2 is applied to a heavily doped n-silicon substrate 1. According to a diffusion process that is selective per se, a p-conductive region is produced in the epitaxial layer 2, for example using boron. A silicon dioxide layer with a thickness of about 8,000 to 10,000 R serves as a mask. During the diffusion of the p-doping, a silicon dioxide layer 3 ^{1 with} a thickness of 5000 Å is formed over the p-base 4 produced in this way.

(b) An aluminum oxide layer 5 with a thickness of 3000 S is produced on the silicon dioxide layers 3 and 3 ^{1 by a cathode sputtering method known per se.}

(c) The alurainium oxide layer 5 becomes selective after one

known photo etching removed. Phosphoric acid is preferably used as the etchant. The silicon dioxide layer 3 ¹ thus exposed is selectively removed with an etchant, preferably with hydrofluoric acid. The aluminum oxide layer 5 produced serves as a mask.

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Through the opening obtained in this way or through the hole obtained in this way, an η-doping, preferably phosphorus, diffused. The emitter 6 is thereby formed.

(d) A silicon dioxide layer not shown in the figures, those involved in diffusion and the production of the emitter area is formed in the manner previously described with hydrofluoric acid etched off. It thus becomes the opening of an emitter electrode according to a flushing process known per se manufactured.

(e) Aluminum is vapor-deposited onto the structure obtained in this way to a thickness of approximately 10000 - 20,000 Å. By selective etching the emitter electrode 7 is produced. This emitter electrode 7 is designed in such a way that it has at least the p-n junction between the base and the emitter with the intervening silicon dioxide layer 3 'and the aluminum oxide layer covered.

(f) Using the emitter electrode 7 as a mask, the Aluminum oxide layer 5 is etched off using phosphoric acid.

(g) The surface of the aluminum forming the emitter electrode 7 is anodically oxidized ^{to form an aluminum oxide layer 7 1 approximately 4,000-10,000 Å thick.}

(h) The layer structure thus obtained is immersed in hydrofluoric acid. The silicon dioxide layers 3 and 3 ^β not covered by the aluminum oxide layers 5 and 7 ¹ are attacked by the etchant. As a result of this dipping, the area of the silicon dioxide layer 3 ¹ not covered by the aluminum oxide layers is completely etched away, while the silicon dioxide layer 3 becomes thinner as a result of this etching, but still remains on the substrate surface.

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surface remains as a dense layer. As a result of this etching, partial areas of the base region 4 are exposed on the surface. On the emitter side, the edge of the opening produced in this way is thus ^{delimited by the aluminum oxide layers 5 and 7 1} , while the edge of the opening on the collector side is formed by the thicker silicon dioxide layer 3.

In other words, the opening created is in the insulator layer 3 so automatically and directly limited by and to the emitter electrode 7.

Then the base electrode 8 and the collector electrode 9 generated by vapor deposition of aluminum (Fig. 2).

The distance d between the base electrode 8 and the emitter electrode 7 does not therefore need, as in the transistor according to the prior art (FIG. 7), that given by the accuracy limit and the resolution of the photo-etching process Maintain a minimum distance. According to the method of the invention, the emitter electrode and the base electrode are produced directly next to each other. This allows the base to be kept extremely small. Accordingly, both the base resistance r i and the base-collector junction capacitance C can be kept small. Above all, this can significantly improve the frequency behavior of the transistor will. In addition, due to the small area required by the transistor produced in this way, the yield is high Switching elements per substrate plate significantly increased compared to the prior art. When using the procedure of the invention for manufacturing integrated circuits can achieve a noticeable increase in the integration density will.

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Example 2

FIGS. 3a to 3h show in cross section a sequence of production stages according to the method according to the invention shown in connection with the manufacture of electrodes for a junction capacitor. With such a Capacitor becomes the junction capacitance between areas formed simultaneously with an emitter and a base exploited.

(a) A monocrystalline semiconductor substrate 11, preferably made of p-type silicon, is coated with an epitaxial, approximately 10 μm thick n-type silicon layer. By diffusing a p-doping, preferably boron, into the epitaxial layer according to a selective diffusion method known per se, a p-insulation region 13 is produced. A silicon dioxide layer 14 with a thickness of 10,000 Å serves as a mask. The p-type isolation region 13 produced in this way isolates the epitaxial island region 12 from the other regions of the epitaxial layer. A window is then introduced into the silicon dioxide layer 14, 12 of the island region is exposed through which a part of the epitaxial layer.

(b) Through this window and using the silicon dioxide layer as a mask, a diffusion process a p-region 15 is generated. At the same time, a base area is created at another point in the island area generated. During the diffusion, a new silicon dioxide layer 14 ', approximately 40000 S thick, is disfigured the surface of the p-region 15 »

(c) An opening is then made in the silicon dioxide layer 14 " which exposes a portion of the p-region 15 under the silicon dioxide layer 14 '.

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(d) Using silicon dioxide layers 14 and 14 ' An η region 16 is produced as a mask by diffusion. At the same time, at a different point on the semiconductor substrate an emitter is generated. As η-doping for production of the η region 16 is preferably used for phosphorus. During diffusion to produce the η range a further silicon dioxide layer is formed on the surface of this area educated.

(e) The structure thus obtained is immersed in hydrofluoric acid. This will etch the silicon dioxide layers. the relatively thin layer of silicon dioxide on area 16 is completely etched away. The thicker silicon dioxide layers 14 and 14 * are thinned by this etching, but remain as an intact and dense layer on the semiconductor substrate. The production described of the window on the η region 16 is thus made according to the so-called emitter washout process or immersion emitter process manufactured using the different layer thicknesses of a coherent silicon dioxide layer will.

The structure is then vapor-deposited with aluminum. The aluminum layer produced is then selectively etched, with an electrode 17 is produced, which is connected to the η region 16. The. Electrode 17 is designed in such a way that that it bridges at least part of the p-n transition between the η region 16 and the p region 15.

(f) The surface of the electrode 17 then becomes anodic an aluminum oxide layer 17 'is oxidized.

(g) The structure thus obtained is immersed in hydrofluoric acid, whereby the silicon dioxide layers 14 and 14 are etched. The thinner silicon dioxide layer 14 'thereby becomes complete

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etched away so that an opening is created that covers a part of the p-region 15 is exposed on its surface. the one edge of this opening is delimited by the aluminum oxide layer 17 ', while the other edge by the relatively thick silicon dioxide layer 14 is formed. In this way, the edge of the opening created is so to speak automatically and precisely adjusted and aligned with respect to the electrode 17.

(h) The p-region 15 is provided with an electrode 18 through the opening produced in this way, that of the electrode 17 is immediately, and in fact much closer than possible according to the state of the art, adjacent »

According to this exemplary embodiment of the invention, the series resistance of the p-layer 15 can be up to the electrode 18 are kept extremely low, whereby the quality factor Q, which is a performance indicator of the capacitor is, is significantly improved. At the same time, the parasitic capacitance is reduced. The distance between the two electrodes 17 and 18 is only determined by the very thin insulator layer 17 '. This creates over the An additional capacitance that is additive to the junction capacitance. As a result, high overall capacities can be obtained »In addition, the The area required by the capacitor produced by the method of the invention is extremely small, so that a much higher integration density can be achieved in the manufacture of integrated circuits.

> Example 3

In Figures 4a to 4j cross-sections are shown various stages of production _s the production of a junction field effect transistor according to the method of the

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Describe the invention.

(a) On an η substrate 21, an n-epitaxial layer is formed

22 generated. A silicon dioxide layer is placed on top of this layer

23 manufactured. Layer 23 is selectively removed. By A p-channel region 24 is produced through the resulting window according to a diffusion process known per se. During the diffusion, a thin silicon dioxide layer 23 'forms on the p-channel region 24.

(b) The entire area of silicon dioxide layers 23 and 23 ' is covered with an aluminum oxide layer 25 by a sputtering method.

(c) The aluminum oxide layer is used to generate the control area 25 selectively removed. For this purpose, phosphoric acid is preferably used as the etchant. Then the silicon dioxide layer 23 'also selectively removed from among the open areas. This is preferably used Hydrofluoric acid as an etchant. When the silicon dioxide layer 23 ″ is etched, the aluminum oxide layer 25 is used as a mask.

(d) Using the alumina layer 25 and of silicon dioxide layers 23 and 23 'is used as a mask the η control region 26 is generated by diffusion.

(e) When the control region 26 is formed by diffusion, a silicon dioxide layer is formed on its surface which is removed with hydrofluoric acid using the aluminum oxide layer 25 as a mask.

(f) The surface of the structure thus obtained is vapor-deposited with an aluminum layer. The aluminum layer becomes selective This is a circular ring-shaped control electrode

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27 received. This control electrode 27 is designed in such a way that it has at least the p-n transition region between the S expensive area 26 and the channel area 24 with the intermediate Silicon dioxide layer 23 'and the aluminum oxide layer 25 covered.

(g) Using the control electrode as a mask, the aluminum oxide layer 25 is etched off and completely removed. Phosphoric acid is preferably used as the etchant.

(h) Then the surface of the control electrode anodically oxidized. This forms on the entire control electrode surface an alumina layer 27 '.

(i) The structure thus obtained is then immersed in a hydrogen fluoride solution. In doing so, the silicon dioxide layers 23 and 23 'other than the alumina layers 25 and 27 'are covered, attacked. The exposed, thinner silicon dioxide layer 23 'becomes complete peeled off, whereby openings for the source electrode and for the drain electrode are formed. With this one In the etching process, the silicon dioxide layer 23 is thinned, but remains as an undamaged, dense layer consist of the semiconductor substrate.

The openings produced by this etching process are directly in accordance with the contours of the control electrode limited.

(j) The drainage electrode 23 and the source electrode 29 are then passed through the openings produced in this way connected to the duct area ο On the back of the structure a second control electrode 27 ″ is also applied.

As shown in Fig. 5 in plan view, the

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Control area 26 formed in a circular shape. The control electrode 27, the source electrode 29 and the drain electrode 28 are therefore on the annular control area 26, on the outer channel area 24 or on the inner channel area 24.

The electrodes can according to the method according to the invention That is to say, they are produced in such a way that they are directly adjacent that the channel area 24 is kept very small in terms of area can be. The series loss / ider stand and the parasitic capacitance of the channel area can thereby kept extremely low. Furthermore, due to the small space requirement of the manufactured in this way Field effect transistor, the yield of elements per substrate wafer can be increased. In the case of making such Field effect transistors in the context of integrated circuits can significantly increase the integration density that can be achieved will"

Example 4

In Figures 6a to 6h are a further embodiment of the method of the invention in cross section different manufacturing stages of the manufacture of the electrodes of a low-ohmic diffusion resistor in an integrated circuit shown.

(a) As described in Example 2, a monocrystalline Semiconductor wafer 31, preferably made of p-silicon, as Substrate used. An n epitaxial layer is produced on the substrate. By making a ρ insulation ring 33, an island region 32 is cut off from the epitaxial layer. In the silicon dioxide layer an opening is created over the island area.

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(b) Using the silicon dioxide layer 34 as Mask, a p-region 35 is produced simultaneously with a base by diffusion. During diffusion A thin silicon dioxide layer 34 'is formed on the diffusion region 35.

(c) The structure obtained is immersed in hydrofluoric acid to remove the silicon dioxide thin layer 34 '. Included the thicker silicon dioxide layer 34 is thinned, but remains intact on the semiconductor structure.

(d) Using the silicon dioxide layer 34 as a mask, diffusion simultaneously with an emitter an η region 36 is generated. During this diffusion forms A thin silicon dioxide layer 34 ″ is formed on the η region 36.

(e) To use the η region 36 as a resistance material the silicon dioxide layer 34 ″ is selectively etched off and removed to produce the first electrode the structure is vaporized with aluminum. The aluminum layer is then selectively etched away. Included the electrode 37 connected to the η region 36 is obtained. The electrode 37 is formed so that it with their edge areas on the silicon dioxide layers and 34 ".

(f) Then, on the surface of the electrode by anodic oxidation an aluminum oxide layer 37 ' manufactured.

(g) The structure thus obtained is immersed in hydrofluoric acid. The thinner silicon dioxide layer 34 ″ in the Areas that are not covered with the aluminum oxide layer 37, peeled off. The thicker silicon dioxide layer

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remains on the surface of the semiconductor substrate.

(h) The second electrode 38 is then thus obtained through this Opening through-connected to the η-area. The one produced, for example, by vapor deposition of aluminum Electrode. 38 becomes in its dimensions to the electrode 37 by this itself or by the on it applied aluminum oxide layer 37 'determined. The dimensional precision of the electrodes is thus determined by this itself, not determined by quasi external procedures. The distance between the electrodes is set automatically, so to speak. In this way, the electrodes can be brought extremely close to one another without the risk of dimensional inaccuracies Generate short circuits.

According to this method, a low resistance in integrated circuits with the smallest V / ground diffusion areas. A high integration density is no longer achieved by such elements prevented. At the same time, due to the reduced dimensions, the parasitic capacitance can also be significant to be humiliated.

The invention is not restricted to the exemplary embodiments described above. The skilled person can a multitude of variations without any inventive step make. He will be able to infer from the above description, for example, that for the implementation of the method of the invention is important that the etching means for the insulator layer on the semiconductor substrate Must not attack the insulating layer on the first electrode. For example, if the electrodes are made of conductive polycrystalline silicon are produced, so can

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the process of the invention can be carried out in the same manner as described above, using, for example, Si-N. or Al ₃ O _{3 is used} as an insulator layer for the substrate. The selection and combination of such protective or insulator layers is part of the specialist knowledge of the semiconductor specialist.

Finally, the method can also be modified in such a way that, after the emitter electrode has been produced in the process stage shown in Fig. Ie, the opening for the base electrode is produced by another process, so that the production of an insulating layer on the emitter electrode is not necessary. the Only then can the emitter electrode be provided with the insulator layer. The insulator layer will then removed for the emitter electrode, whereupon the base electrode is created.

Also, in the embodiment 4, the diffusion generated p-area 35 serve directly as resistance material without the need to form an η-area 36. The electrodes 37 and 38 are connected to the p-region 35 in the same way.

The described method, electrodes by self-controlled distance control independent of the etching technique The achievable degree of accuracy can be practically arranged as close together as desired Changed many ways and 'used for a wide variety of requirements.

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Claims (4)

24U520 Claims l) A method for producing two closely spaced electrodes on a semiconductor substrate, characterized in that a hole is made in an insulator layer covering the substrate surface, a first electrode is produced through this hole, the surface of the first electrode produced in this way is in converts an insulator by creating a further hole in the insulating layer, using the insulating substance created on the first electrode at least as part of a mask, and creating a second electrode through this second hole. 2. The method according to claim 1, characterized in that after the preparation of the first electrode makes a second hole through the first hole in the insulator layer, wherein one the first electrode is used at least as part of a mask, and only then can the surface of the oxidizes the first electrode and then produces the second electrode through the second hole. 3. The method according to any one of claims 1 or 2, characterized 5 09808/0693 24U520 characterized in that the hole for the first electrode is immediately adjacent to a p-n junction attaches that through this hole a first connected to the one line area of the transition Electrode is manufactured in such a way that it is on top of the layer of insulator below p-n junction extends away and that you then directly under the guidance of the oxide layer on the first electrode adjoining this the second hole for the second with the other line area of the p-n junction connected electrode. 4. The method according to any one of claims 1 or 2, characterized in that both holes, through which the two electrodes are formed in succession, attaches to cooperate with one and the same semiconductor region is connected. 509808/0693 Blank page