JPH0247865A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the high speed operation of an n-p-n bipolar transistor and the application to a Bi-CMOS by a method wherein a side wall is utilized when a first buried region is formed and the side wall is removed when a second buried region is formed and the distance between the first and second buried regions is made to be close to the width of the side wall. CONSTITUTION:An n-type well region 8a is formed on one of n<+>-type buried regions 8 and a p-type well region 11a is formed on a p<+>-type buried region 11. A gate oxide film 21, a gate electrode 22 and n<+>-type source and drain regions 23 are formed on the p-type well region 11a to constitute an n-type channel MOS transistor. A gate oxide film 21, a gate electrode 22 and p<+>-type source and drain regions 24 are formed on the n-type well region 24 to constitute a P-type channel MOS transistor. Further, a collector contact region 25, a base region 26 and an emitter region 27 are formed on an n-type epitaxial layer 12 to constitute an n-p-n bipolar transistor.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and in particular to a method for manufacturing a semiconductor integrated circuit device, and in particular to a method for manufacturing a Bi-CMO3 integrated circuit device in which a bipolar element and an MO3 type element are configured on the same semiconductor substrate. The present invention relates to a method for forming a high concentration region.

[Conventional technology]

Currently, in Bi-CMO3 integrated circuit devices, the general structure is to form an n-buried region and a p-buried region in parallel in a semiconductor substrate, and to have an n-well and a p-well on these buried regions, respectively. It is. When forming the n' buried region and the P' buried region, a conventional method has been used in which these buried regions are formed in one mask step in order to reduce the number of mask steps.

That is, FIGS. 3(a) to 3(f) are vertical cross-sectional views showing an example of the process in order. First, as shown in FIG. 3(a), a first silicon oxide film is formed on a p-type silicon substrate 1. After forming the silicon nitride film 2 and the first silicon nitride film 3, as shown in FIG. 3(b), the silicon nitride film 3 and the first silicon oxide film 2 in the region where the n' buried region is to be formed are removed by a mask process. Then, the n'' region 8 is selectively formed by solid phase diffusion of arsenic using the silicon oxide film 2 and the silicon nitride film 3 as masks.

Next, as shown in FIG. 3C, a second silicon oxide film 10 is formed on the n'' region 8 by selective oxidation using the silicon nitride film 3 as a mask.

Then, as shown in FIG. 3(d), after removing the silicon nitride film 3 and the first silicon oxide film 2, a p'' region 11 is selectively formed by solid phase diffusion of boron.

Next, as shown in FIG. 3(e), the second silicon oxide film 10
After removing, an n-type epitaxial layer 12 is formed by epitaxially growing n-type single crystal silicon. And the third
As shown in FIG. 1F, in the epitaxial layer 12, a P well region 11a is formed on the P' buried region 11, and an n well region 8a is formed on the n' buried region 8.

Note that here, a gate oxide film 21. is formed in the p-well region 11a. Gate electrode 22 and n° source/drain region 2
constitutes an n-channel MO3 transistor consisting of 3 transistors, n
A gate oxide film 21. is provided in the well region 8a. Gate electrode 22
and p channel M consisting of p source and drain regions 24
Form an O3I-transistor and form an n-type epitaxial layer 1
2 has a collector contact region 25. An npn bipolar transistor consisting of a base region 26° and an emitter region 27 is formed.

[Problem to be solved by the invention]

By the way, in the B i CMO3 integrated circuit device, npn
Bipolar transistor collector resistance reduction and CM
In order to prevent latch-up of O3, it is required to increase the concentration of the n' region 8 and the p'' region 11. In this case, in the conventional method described above, the opening for forming the diffusion source in the n' region 8 is Since the distance between the p'' region 11 and the opening for forming the diffusion source is as narrow as the width of the second silicon oxide film 10 which is formed under the silicon nitride film 3 during selective oxidation of silicon, (d) n″ as shown by the dashed line below.
The square region 8 and the p'' region 11 form a direct mold at the boundary region of each other.For this reason, the reverse breakdown voltage between the n'' region 8 and the p'' region 11 is likely to decrease. There is a limit to increasing the speed of npn bipolar transistors due to high concentration in region 8, and Bi-CMO which operates at high power supply voltage
A problem arises in that it is no longer suitable for application to three integrated circuits.

The present invention solves these problems, and provides a method for manufacturing a semiconductor integrated circuit device that can increase the speed of an npn bipolar transistor and form a buried region that can be applied to Bi-CMO3. It is an object.

[Means to solve the problem]

The method of manufacturing a semiconductor integrated circuit device of the present invention includes the steps of selectively forming a thick film including at least a film that is difficult to oxidize on a semiconductor substrate at a first buried region formation location, and a film made of a Max material on the entire surface. forming and etching back this to leave it as a sidewall on the side surface of the thick film; and using the thick film and sidewall as a mask, impurities are introduced into the semiconductor substrate to form a first buried region of a first conductivity type. The first layer is formed on the semiconductor substrate by a selective oxidation process in which the sidewall is removed and the remaining oxidizable film is used as a mask.
The method includes a step of forming an oxide film covering the buried region, and a step of selectively forming a second buried region of the second conductivity type in the semiconductor substrate using the oxide film as a mask.

[Effect]

The first and second buried regions formed by the above-described manufacturing method are spaced apart from each other with a dimension substantially close to the thickness of the side wall used as a mask, and are prevented from overlapping.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(i) are longitudinal sectional views showing a first embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1(a), a first silicon oxide film 2 is formed to a thickness of about 0.3 μm on a p-type silicon substrate 1 by a thermal oxidation method, and then a first silicon nitride film 2 is formed by a CVD method. The film 3 is grown to a thickness of about 0.2 μm.

Next, as shown in FIG. 1(b), after depositing a polycrystalline silicon film 5 of about 3 μm and a second silicon nitride film 6 of about 2 μm, a patterned photoresist (not shown) is used as a mask to deposit the second silicon nitride film. Nitride film 6, polycrystalline silicon 5. Then, the first silicon nitride film 3 is selectively etched. The photoresist is then removed.

Next, as shown in FIG. 1C, a third silicon nitride film 7 is formed to a thickness of about 1 μm over the entire surface by CVD, and then this third silicon nitride film 7 is etched back by anisotropic etching. As shown in FIG. 1(d), polycrystalline silicon 5. Second silicon nitride film6. and is left on the side surface of the first silicon nitride film 3 as a side wall 7A. Then, polycrystalline silicon 5° second silicon nitride film 6. The first silicon nitride film 2 exposed on the surface is etched using the side walls 7A of the first silicon nitride film 3° and the third silicon nitride film as masks, and then solid-phase diffusion of arsenic is performed. Then 1100°C-12
A buried region 8 having a sheet resistance of approximately 20Ω/hole is formed by drive-in at 00°C.

Next, as shown in Figure 1(e), approximately 0.1
After forming the mask silicon oxide film 9 with a thickness of μm, the second silicon nitride film 6 and sidewall 7A are removed by wet etching using hot phosphoric acid. Subsequently, polycrystalline silicon 5 is removed by wet etching using hydrazine.

Next, as shown in FIG. 1(f), a second silicon oxide film 10 having a thickness of about 0.8 μm is formed by selective oxidation using the first silicon nitride film 3 as a mask. After that, the first silicon nitride film 3 and the first silicon oxide film 2 are removed.

Next, as shown in FIG. 1(g), a second silicon oxide film 1 is formed.
Boron ion implantation or solid phase diffusion is performed using 0 as a mask, and then a p° buried region 11 with a maximum impurity concentration of about 10''C11-3 is selectively formed by drive-in at 1000°C to 1100°C. .

Next, as shown in FIG. 1(h), after all the silicon oxide film on the surface of the silicon substrate 1 is removed, n-type single crystal silicon with a thickness of 1 to 6 μm is epitaxially grown to form an n-type epitaxial layer 12.

Then, as shown in FIG. 1(i), an n well region 8a is formed on a part of the n+ buried region 8, and a p well region 11a is formed on the p' buried region 11. Then, a gate oxide film 21 is formed in the p-well region 11a. A gate electrode 22 and an n+ source/drain region 23 are formed to form an n-channel MO3) transistor, and a gate oxide film 21, a gate electrode 22, and a p source/drain region 24 are formed in the n-well region 8a to form a p-channel MO3I transistor. - constitute a transistor; Furthermore, a collector contact region 25. is formed in the n-type epitaxial layer 12. Base region 26° Emitter region 2
7 to form an npn bipolar transistor.

Therefore, in this manufacturing method, the n0 buried region 8 and the P9 buried region 11 that are formed have a dimension approximately equal to the thickness of the side wall 7A formed of the third silicon nitride film 7. can be formed at a distance to prevent the two from overlapping. This makes it possible to suppress a decrease in reverse breakdown voltage between both buried regions 8, 11 due to high concentration in both regions.

FIGS. 2(a) to 2(f) are longitudinal sectional views showing a second embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 2(a), a silicon oxide film 2 with a thickness of about 0.1 μm and a first silicon oxide film with a thickness of about 0.2 μm are deposited on a p-type silicon substrate 1.
After forming the silicon nitride film 3, tungsten 4a of about 0.3 μm and aluminum 4b of about 0.1 μm are deposited.

After depositing a polycrystalline silicon 5 of about 3 μm and a second silicon nitride film 6 of about 2 μm in the same manner as in the first embodiment, the second silicon nitride film 6 is deposited using a photoresist (not shown) as a mask.
Then, polycrystalline silicon 5 is selectively etched. Furthermore, aluminum 4b is removed using a dilute hydrofluoric acid solution.

After that, the photoresist was removed and about 1 μm thick was applied to the entire surface.
A third silicon nitride film 7 is deposited.

Next, as shown in FIG. 2(b), a third silicon nitride film 7 is formed.
5. Etch back the polycrystalline silicon by anisotropic etching. The second silicon nitride film 6 and the tungsten 4b are left as sidewalls 7A on the sides of the aluminum 4b, and using these as masks, the tungsten 4b is removed by wet etching or dry etching using aqua regia. After that, acceleration voltage 100KeV, dose amount IX1014
cm-' of boron ions are implanted into the p-embedded region 11.
form.

During this ion implantation, similar to etching, polycrystalline silicon 5. Second silicon nitride film6. Although the side wall 7A is used as a mask, since the tungsten 4a exists under the side wall 7A, boron ions do not reach the silicon substrate 1 under the side wall 7A (in this region). 20 buried region 11 is not formed.

Next, as shown in FIG. 2(C), the side wall 7A is removed using a hot phosphoric acid solution, and then the first silicon nitride film 2 and the second silicon nitride film 6 on the p'' region 11 are removed. Also,
The tungsten 4a is removed using aqua regia using the polycrystalline silicon 5 as a mask, and the first silicon nitride film 3 underneath is removed.
is removed with hot phosphoric acid solution.

Subsequently, as shown in FIG. 2(d), polycrystalline silicon 5 is removed using hydrazine, and aluminum 4b and tungsten 4a are removed using the aforementioned etching solution. Then, using the remaining first silicon nitride film 3 as a mask, a second silicon oxide film 10 of about 0.5 μm is formed by selective oxidation.
form.

Next, as shown in FIG. 2(e), the first silicon nitride film 3 is
Then, the first silicon oxide film 2 is removed, and arsenic is solid-phase diffused using the second silicon oxide film 10 as a mask and 1100"C
By front and rear drive-ins, an n buried region 8 having a sheet resistance of about 20 Ω/hole is selectively formed.

Thereafter, as shown in FIG. 2(f), the second silicon oxide film 10 is removed and the n-type epitaxial layer 12 is grown in the same manner as in the first embodiment.
A channel MOS transistor and an npn bipolar transistor are formed.

In this second embodiment, since tungsten 4a with a large atomic weight exists under the side wall 7A, when forming the P buried region 11 by ion implantation of boron with a small atomic weight, the side wall 7A and the tungsten 4a are completely ionized. It serves as a mask for implantation and has the advantage of reliably preventing overlap with the n+ buried region 8.

〔Effect of the invention〕

As explained above, in the present invention, the sidewall is used when forming the first buried region, and this sidewall is removed when forming the second buried region. The interval can be set close to the width dimension of the side wall, and overlapping of both embedded regions is prevented.

This suppresses a decrease in the reverse breakdown voltage between the first region and the second region due to the high concentration of the first and second buried regions, and in particular, the n buried region and the p When applied to the formation of a buried region, it is effective for increasing the speed of Bi-CMO3 integrated circuits and developing high-voltage Bi-CMO3 integrated circuits.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(i) are longitudinal sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to 2(i)
f) is a longitudinal sectional view showing the second embodiment of the present invention in the order of manufacturing steps, and FIGS. 3(a) to 3(f) are longitudinal sectional views showing the conventional manufacturing method in the order of steps. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... First silicon oxide film, 3... First silicon nitride film, 4a... Tungsten, 4b... Aluminum, 5... Polycrystalline silicon, 6 . . . second silicon nitride film, 7 . . . third silicon nitride film, 7A . . . side wall, 8 .
9... Mask silicon oxide film, 10... Second silicon oxide film, 11... P' buried region, 12... N-type epitaxial layer, 21... Gate oxide film, 22...
Gate electrode, 23...n+ source/drain region, 2
4... p" source/drain region, 25... collector contact region, 26... base region, 27...
emitter area.

Claims (1)

[Claims] 1. A step of selectively forming a thick film containing at least a film that is difficult to oxidize on the semiconductor substrate at the first buried region formation location, and forming a film made of Max material on the entire surface and etching back this. a step of leaving a sidewall on a side surface of the thick film; a step of introducing impurities into the semiconductor substrate using the thick film and the sidewall as a mask to selectively form a first buried region of a first conductivity type; and a step of selectively forming a first buried region of a first conductivity type; forming an oxide film covering the first buried region on the semiconductor substrate by selective oxidation using the remaining oxidizable film as a mask; A method of manufacturing a semiconductor integrated circuit device, comprising the step of selectively forming a second buried region of a conductive type.