JPH0666328B2 - MOS semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constituent element of a semiconductor integrated circuit, and the integrated circuit using the present invention is suitable for the field of more advanced information processing.

2. Description of the Related Art Miniaturization is an important factor for higher integration of MOS type semiconductor devices (hereinafter simply referred to as MOSIC). However, if miniaturization is performed, the source-drain distance, that is, the channel length becomes shorter and the drain breakdown voltage becomes higher. descend. To improve this, an LDD structure (Lightly-Doped Drain) provided with low-concentration source / drain regions connected to the source / drain is disclosed in JP-A-54-4.
Proposed in No. 4482.

Problems to be Solved by the Invention Although the LDD structure improves the drain breakdown voltage and the hot carrier resistance even in the submicron channel length, there is a problem that a series resistance is added due to the existence of the low concentration region. there were. As a result, although the channel length is shortened, the drain current does not increase, and thus the operating speed of the circuit does not increase.

Means for Solving the Problems The present invention has a structure in which a side wall gate is provided on an end face of a gate electrode through a tunnel oxide film and the low concentration source / drain is covered with the side wall gate.

Action The sidewall gate is electrically connected to the gate electrode by the tunnel effect. As a result, the potential change of the gate electrode causes the potential change of the side wall gate as it is, so that the low-concentration source / drain is controlled by the gate electrode. For example, in the case of n-channel, if a positive potential is applied by the gate electrode, not only many electrons are induced in the channel but also more electrons are induced in the low concentration source / drain.

EXAMPLE An example of the present invention is shown in FIGS. 1 to 3 together with a manufacturing process.

As shown in FIG. 1, a P-type region 21 serving as an inversion prevention layer and a thick oxide film 2 are formed on one main surface of a P-type silicon substrate 1 by a selective oxidation method, and a thickness of 1
A gate insulating film 3 made of a 5 nm oxide film is grown, and polycrystalline silicon containing phosphorus is deposited thereon. The polycrystalline silicon is etched using the photoresist 5 as a mask to form the gate electrode 4. At this time, the thickness of the portion 31 of the gate oxide film 3 not covered by the gate 4 is reduced by Δ. This is caused by the fact that the etching rate ratio of polycrystalline silicon to oxide film is not infinite in etching polycrystalline silicon. The film thickness of polycrystalline silicon and its etching rate are not uniform in the plane of the wafer, and for pattern formation, overetching must be performed with respect to the average etching time. Assuming that the thickness and etching unevenness are 10%, the etching rate ratio of polycrystalline silicon to oxide film is 1/10, and the thickness of polycrystalline silicon is 200 nm, the maximum value of Δ is Δmax200 (nm) × 0.1. × 0.1 = 2 nm.

Using the thick oxide film 2 and the gate 4 as a mask, phosphorus is 1 ×.
A 10 ¹³ cm ^-2 dose is implanted to form low concentration n-type regions, that is, low concentration source / drain 71 and 72.

Next, as shown in FIG. 2, after the resist 5 is removed and washed, thermal oxidation is performed so that the oxide film 31 recovers its initial thickness. At this time, a thin thermal oxide film 8 grows on the end face and the upper face of the gate 4, but the thickness thereof is about Δ2 nm.

When a second polycrystalline silicon containing phosphorus is deposited on the entire surface and anisotropic dry etching is performed so that the etching progresses perpendicularly to the substrate surface, the end face of the gate 4 is provided with a sidewall gate 9 via a thin thermal oxide film 8. Is formed. Using this as a mask, arsenic is implanted at a dose of 5 × 10 ¹⁵ cm ^-2 to form high-concentration n-type regions, that is, high-concentration source / drain 101, 102. After that, metal wiring is formed and the process is completed as shown in FIG.

Although a thin oxide film 8 is interposed between the side wall gate 9 and the gate 4, since the thickness thereof is about 2 nm, a current easily flows due to the tunnel effect. That is, the oxide film 8 is a so-called tunnel oxide film. As a result, the sidewall gate 9 is always kept at substantially the same potential as the gate 4, so that the sidewall gate 9 also has the ability to control the electrical state of the surface of the semiconductor substrate 1 like the gate 4.

The surface of the low concentration source / drain 71, 72 is an oxide film 31.
Since it is positionally aligned with the side wall gate 9 via, the carrier potential (electron) concentration is controlled by the gate potential. That is, when the gate potential becomes a positive potential, carriers are induced on the surface and the resistance of that portion decreases. As a result, a larger drain current than before flows.

When the left (101) of FIG. 3 is the source and the right (102) is the drain, when the gate potential is low and the drain potential is higher than that, the carrier concentration of the low concentration drain 72 decreases from the surface and depletes. Therefore, the effective impurity concentration of the low-concentration drain 72 with respect to the drain breakdown voltage is reduced.
1,72 should have a higher concentration. This will further reduce the additional series resistance.

EFFECTS OF THE INVENTION In the present invention, the low concentration source / drain of the LDD structure is covered by the sidewall gate, and the electrical state thereof is controlled by the gate, so that the additional series resistance is low and more drain current is increased. The effect of flowing is brought about. The circuit comprising the MOS type semiconductor device of the present invention is thereby characterized in that it operates significantly faster than the conventional type.

[Brief description of drawings]

1 to 3 are cross-sectional views of manufacturing steps of a MOS transistor according to an embodiment of the present invention. 1 ... P-type silicon substrate, 2 ... Oxide film, 3 ... Gate oxide film, 4 ... Gate, 8 ... Oxide film, 9 ... Side wall gate, 72 ... Low concentration drain, 102 ... Drain.

Claims (1)

[Claims] 1. A gate electrode provided on one main surface of one conductivity type semiconductor substrate via a gate insulating film, a tunnel oxide film covering the gate electrode, and an end face of the gate electrode via the tunnel oxide film. Provided sidewall gate, two conductivity type low concentration region connected to the source / drain on one conductivity type semiconductor substrate immediately below the sidewall gate, and two conductivity type high concentration region having the sidewall gate and the overlapping portion at the end thereof. And a source / drain diffusion layer of
Type semiconductor device.