JPH0484428A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high relative accuracy and an absolute accuracy in case a polycrystalline semiconductor layer is used for the formation of a resistance element by a method wherein parts, which are situated on the side surfaces of step parts on a semiconductor substrate, of the polycrystalline semiconductor layer are previously removed. CONSTITUTION:An anisotropic dry etching is performed to remove an oxide film on the surface of a polycrystalline silicon layer. At this time, the oxide film 109 on the side surfaces of parts, which cover gate electrodes, of the polycrystalline silicon layer is left. Subsequently, a thin film layer 110 consisting of transition metal element, such as tungsten, molybdenum or the like, or the like or a substance having a selection ratio with respect to etching with silicon oxide and polycrystalline silicon, such as tungsten, is selectively grown on the polycrystalline silicon layer. Then, after the film 109 is removed with a hydrofluoric acid, parts, which are situated on the side surfaces of the gate electrodes, of the polycrystalline silicon layer are removed using the mixed aqueous solution of a hydrofluoric acid, a nitric acid and an iodine-containing glacial acetic acid. Subsequently, after the tungsten thin film layer 109 is removed using the mixed solution of ammonia water and hydrogen peroxide water, a photoresist 111 is formed into a desired form by a photolithography technique and an anisotropic dry etching is performed using this photoresist 111 as a masking material to form a resistance element 112.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a polycrystalline semiconductor layer is formed in a desired shape on a semiconductor substrate having steps.

[Conventional technology]

In recent years, semiconductor integrated circuits have become smaller and faster, and one of the underlying technologies is polycrystalline semiconductor technology. Bipolar transistors use polycrystalline semiconductors for their emitters to form shallow junctions to increase speed, and self-alignment technology using polycrystalline semiconductor layers allows for miniaturization. It is also used for gate electrodes in MOS transistors. The polycrystalline semiconductor layer is also used as a resistance element, and is used as a resistance element with small parasitic capacitance. Due to these various uses, the polycrystalline semiconductor layers used in recent integrated circuits are mainly composed of two layers having different film thicknesses and layer resistances. For example, the first layer is used as a low-resistance gate electrode, and the second layer is used as a relatively high-resistance resistance element.

FIGS. 3(a) to 3(d) show process cross-sectional views of a conventional method for manufacturing a CMO8 type O8 circuit using two-layer polycrystalline semiconductor layers. First, as shown in FIG. 2(a), a P-type silicon substrate 201 is prepared, a P-type well region 202 and an N-type well region 203 are formed, and an isolation oxide film 204 is formed. 1 polycrystalline silicon layer 205
It grows by about 6,000 people, and impurities are diffused to lower the resistance. Next, as shown in FIG. 3(b), the polycrystalline silicon layer 205 is processed into a desired shape using a photolithography process and an anisotropic dry etching process, and the gate electrode 205 is
′ is formed. After oxidizing the gate electrode 205' surface,
Implantation energy 70KeV Dose amount 5×10”a
An N+ type source/drain region 306 is formed by ion implantation of arsenic of m-2, and a P+ type source/drain region 307 is formed by ion implantation of boron at an implantation energy of 30 KeV and a dose of 5 X I O''am-2. Next, as shown in FIG. 3(c), a second polycrystalline silicon layer 30 is formed.
After growing 8 to 1,000 to 3,000 people, a photoresist with a desired shape is formed using a photolithography process.
form 9. Furthermore, as shown in Figure 3 (cl),
Isotropic dry etching is performed using the photoresist 309 as a mask to form a resistive layer 308'. Interlayer insulation film 31
0 and after opening the contact hole, the metal wiring 31
1 to complete the element.

[Problem to be solved by the invention]

In this conventional method for manufacturing a semiconductor device using a two-layer polycrystalline semiconductor layer, isotropic dry etching is used to etch the second polycrystalline silicon layer, so side etching occurs and the shape is different from that of the photoresist. There is a drawback that the dimensions are not exactly correct, and the relative accuracy or absolute accuracy decreases when used as a resistor element, for example. On the other hand, when anisotropic dry etching is used to etch the second polycrystalline silicon layer, as shown in FIG. It has the disadvantage that it remains. Since the remaining sidewalls of polycrystalline silicon are in an electrically floating state, if they capture charges such as hot carriers, they will adversely affect transistor characteristics. Moreover, FIG. 4 shows a case where a capacitive element is constructed by a first polycrystalline silicon layer and a second polycrystalline silicon layer via a thin oxide film, and FIG. 4(a) shows a cross-sectional view.
b) shows a top view. In this case, the sidewall 404' of the second polycrystalline silicon layer remaining on the sidewall is connected to the extraction electrode of the second polycrystalline silicon layer, and this capacitive element also has a capacitive component on the side surface. The capacitance value is not determined simply by the area of the second polycrystalline silicon layer, resulting in a problem that it becomes difficult to design the capacitive element.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a polycrystalline semiconductor layer is formed in a desired shape on a semiconductor substrate having almost vertical steps, after growing the polycrystalline semiconductor layer, the surface is a step of oxidizing, and a step of using anisotropic etching to leave the oxide film on the side surface of the polycrystalline semiconductor layer covering the step and removing the other oxide film;
After selectively growing a thin film layer of a transition metal element or the like on the polycrystalline semiconductor layer and removing the remaining oxide film on the side surface of the polycrystalline semiconductor layer, isotropic etching is used to remove the polycrystalline semiconductor layer on the side surface of the stepped portion. The method includes a step of removing the crystalline semiconductor layer, and a step of etching the polycrystalline semiconductor layer into a desired shape after removing the selectively grown layer of the transition metal element or the like.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are process cross-sectional views of an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type well 102 and an N-type well 102 are formed on a P-type silicon substrate using a method similar to the conventional technique.
After forming a type well 103, an element isolation oxide film 104, a gate electrode 105, an N+ type source/drain region 106, and a P+ type source/drain region 107, a polycrystalline silicon layer 108 is grown by about 1000 to 3000 layers. The surface is oxidized to several hundred holes. Next, as shown in FIG. 1(b), anisotropic dry etching is performed to remove the oxide film on the surface. At this time, an oxide film 109 remains on the side surface of the portion where the polycrystalline silicon layer covers the gate electrode. Next, a thin film layer 110 of tungsten, such as a transition metal element such as tungsten or molybdenum, which has a good etching selectivity with silicon oxide and polycrystalline silicon, in this embodiment, is selectively grown on the polycrystalline silicon layer by about 1000 layers. do. A 5 iHz reduction method is used for selective growth of the tungsten thin film. Next, the first
After removing the oxide film 109 with hydrochloric acid, as shown in FIG. 3C, the polycrystalline silicon layer on the side surface of the gate electrode is removed using a mixed aqueous solution of hydrochloric acid, nitric acid, and iodine-containing glacial acetic acid.

Subsequently, as shown in FIG. 1(d), after removing the tungsten thin film layer 109 using a mixture of aqueous ammonia and hydrogen peroxide, a photoresist 111 is formed in a desired shape by photolithography. Using this as a mask material, anisotropic dry etching is performed to form the resistive element 112. Finally, as shown in FIG. 1(e), the interlayer insulating film 113
After forming a contact hole, the metal wiring 114 is formed to complete the device.

〔Effect of the invention〕

As explained above, the present invention uses a thin film of a transition metal element or the like as a mask material and removes the polycrystalline semiconductor layer on the side surface of the step portion on the semiconductor substrate in advance, thereby allowing selective etching of the polycrystalline semiconductor layer to remove the step portion. It becomes possible to perform anisotropic tri-etching without leaving a polycrystalline semiconductor layer on the side surface of the part. By using anisotropic etching, the shape of the polycrystalline semiconductor layer can be made to almost match the shape of the photoresist. For example, when a polycrystalline semiconductor layer is used for a resistor element, high relative and absolute accuracy can be achieved. This has the effect of making it possible to provide guarantees.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the process of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the process of the prior art, and FIGS. 3 and 4 (a) to (b) show defects in the prior art. FIG. 3 is a vertical cross-sectional view and a top view of a portion of the semiconductor integrated circuit. 101.201. ．． 301,401...(P-
type) silicon substrate, 102, 202...P type well region, 103, 203...N type well region,
104゜204.402...Element isolation oxide film, 205゜302.403...First polycrystalline silicon layer, 105゜205'...Gate electrode, 4
03'... Capacity oxidation L 106,206...
...N+ type source drain electrode, 107,207・
...P1 type source drain electrode, 108...
...Polycrystalline silicon layer, 208,404...Second polycrystalline silicon layer, 303,404'...Second polycrystalline silicon wall side, 109...Side oxidation Film, 110...Tungsten thin film, 11,209
...Photoresist, 112,208'...
...Resistance element, 113.210,402...
Interlayer insulating film, 406...Contact hole, 1
14,211,407... Wiring metal. Agent Patent Attorney Susumu Uchihara (C) Figure (d) Figure 2 Mamoru 2 Third, Photoresist (b) Figure 4

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which a polycrystalline semiconductor layer is formed in a desired shape on a semiconductor substrate having vertical steps,
After growing the polycrystalline semiconductor layer, a step of oxidizing the surface;
A process of using anisotropic etching to leave the oxide film on the side surface of the polycrystalline semiconductor layer in the part that covered the step and removing the other oxide film, and adding a thin film layer of transition metal elements etc. to the polycrystalline semiconductor layer. a step of selectively growing the polycrystalline semiconductor layer on the side surface of the step portion; and a step of removing the polycrystalline semiconductor layer on the side surface of the stepped portion using isotropic etching after removing the oxide film on the side surface of the remaining polycrystalline semiconductor layer;
A method for manufacturing a semiconductor device comprising the steps of removing the selectively grown layer of the transition metal element, etc., and then etching the polycrystalline semiconductor layer into a desired shape by anisotropic etching.