JPS5980968A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS5980968A JPS5980968A JP19277382A JP19277382A JPS5980968A JP S5980968 A JPS5980968 A JP S5980968A JP 19277382 A JP19277382 A JP 19277382A JP 19277382 A JP19277382 A JP 19277382A JP S5980968 A JPS5980968 A JP S5980968A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon
- emitter
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 238000000605 extraction Methods 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 3
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 150000004767 nitrides Chemical class 0.000 abstract description 11
- 238000002955 isolation Methods 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 241000277331 Salmonidae Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体集積回路装置、特にバイポーラ形集積
回路装置におけるペース抵抗の小さい高周波トランジス
タの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a high frequency transistor with low pace resistance in a semiconductor integrated circuit device, particularly in a bipolar integrated circuit device.
一般に、バイポーラ形集積回路装置(以下単にBIP・
ICと言う)のトランジスタはp−n接合分離1遺択酸
化技術を使った酸化膜分離、また三重拡散による方法な
どによって電気的に独立した島内に形成されるが、ここ
では酸化膜分離法によってnpn)ランジスタを形成す
る製造方法について説明する。In general, bipolar integrated circuit devices (hereinafter simply BIP
(referred to as IC) transistors are formed in electrically independent islands by oxide film separation using p-n junction isolation, single selective oxidation technology, or triple diffusion. A manufacturing method for forming a npn) transistor will be described.
第1図(a)〜第1図(e)は従来のバイポーラ形集積
回路装置の製造方法を製造工程順に示す断面図である。FIGS. 1(a) to 1(e) are cross-sectional views showing a conventional method for manufacturing a bipolar integrated circuit device in the order of manufacturing steps.
同図において、(1)は低不純物濃度のP形シリコン基
板、(2)はコレクタ埋込層となる高不純物濃度n形層
(以下単忙n+層と1う) 、(3)は低不純物濃度n
形(以下iと言う)のエピタキシャル層、(4〕はチャ
ネルカント用のp層、(5ンは下敷酸化膜、(6)は厚
い酸化膜、(7)はこの下敷酸化膜(5)上に形成した
窒化膜、(8)はイオン注入保護用の酸化膜、(9)は
外部ペース層となるp”N−、αIはレジスト膜、(1
1)は活性ベース層となるp層、(12)は一般にPS
G(ホスシリケート・ガラス膜)を用いるパッシベーシ
ョン膜、(13)および(14i if高ドースのイオ
ン注入を行なった領域、(13a)はエミツタ層、(1
4a)はコレクタ電極数シ出し層、(15a)、(15
b)および(15c)はそれぞれ開口部、(16a)
〜(16c)は一般にPt−8i、Pd−8iなどの金
属シリサイド、(17a)〜(17c)は電極配線であ
る。In the figure, (1) is a low impurity concentration P-type silicon substrate, (2) is a high impurity concentration n-type layer (hereinafter referred to as simple n+ layer) which becomes the collector buried layer, and (3) is a low impurity concentration n-type layer. concentration n
(4) is a p layer for channel cant, (5) is an underlying oxide film, (6) is a thick oxide film, and (7) is an epitaxial layer on this underlying oxide film (5). (8) is an oxide film for protecting ion implantation, (9) is p”N- which will be an external space layer, αI is a resist film, (1) is a nitride film formed on
1) is a p-layer which becomes an active base layer, and (12) is generally a PS layer.
Passivation film using G (phosphosilicate glass film), (13) and (14i if high dose ion implantation region, (13a) emitter layer, (13)
4a) is a collector electrode number projection layer, (15a), (15
b) and (15c) are openings, (16a) respectively.
- (16c) are generally metal silicides such as Pt-8i or Pd-8i, and (17a) - (17c) are electrode wirings.
次に、上記構成によるバイポーラ形集積回路装置の製造
工程について説明する。まず、第1図(a)に示すよう
に、低濃度のp形シリコン基板(1)にコレクタ埋込層
となるn−形のエピタキシャルi (3) 全成長させ
る。次に、第1図(b)に示すように、下敷酸化膜(5
)上に形成した窒化膜(7)をマスクとして選択酸化技
術によって分離帯に厚い酸化膜(6)を形成し、分離酸
化膜直下にはチャンネルカット用のp層(4)が同時に
形成される。次に第1図fc)に示すように、選択酸化
用のマスクを除去し、再度イオン注入保腫用の酸化膜(
8)を形成し、レジスト膜(図示してない)をマスクと
して外部ペース層となるp層層(9)をイオン注入法で
形成し、レジスト膜除去後、再度レジスト膜αQをマス
クとして活性ベース層となるp層(Iりをイオン注入法
によって形成する。Next, the manufacturing process of the bipolar integrated circuit device having the above configuration will be explained. First, as shown in FIG. 1(a), an n-type epitaxial layer (3) which will become a collector buried layer is completely grown on a lightly doped p-type silicon substrate (1). Next, as shown in FIG. 1(b), an underlying oxide film (5
) A thick oxide film (6) is formed on the isolation zone by selective oxidation technology using the nitride film (7) formed on the top of the isolation film as a mask, and a p-layer (4) for channel cutting is simultaneously formed directly under the isolation oxide film. . Next, as shown in Figure 1 fc), the selective oxidation mask is removed and the ion implantation mask oxide film (
8) is formed, a p-layer layer (9) which becomes an external space layer is formed by ion implantation using a resist film (not shown) as a mask, and after the resist film is removed, an active base layer is formed using the resist film αQ as a mask again. A p-layer (I layer) is formed by ion implantation.
次に、第1図(d)に示すように、パッシベーション膜
021をデポジションし、ペース、イオン注入層(9)
。Next, as shown in FIG. 1(d), a passivation film 021 is deposited, and a paste and an ion implantation layer (9) are deposited.
.
(U)のアニールとパッシベーション膜02)のmoめ
、!:をかねた熱処理をおこなったのち、パッシベーシ
ョン膜0匂に所要の開口部(15a)および(x5b)
を形成して、n形不純物の筒ドーズのイオン注入を行な
い、n+領域贈および04)を形成する。次に第1図(
e)に示すように、イオン注入層o場、 u<をアニー
ルして、エミツタ層(13a)、コレクタ電極取り出し
層(14a)を形成したのち、ペース電極取り出し用の
開口部(15c)を形成し、゛電極ぬけ防止のため、金
属シリサイド(16a) 〜(16c)を開口部(15
a) 〜(15c)にそれぞれ形成したのち、低抵抗金
属(一般K Atの使用が多い)による電極配線(17
a)〜(1’7c)をおこなう。なお、第1図(e)
K示すトランジスタの平面パターンを第2図に示す。Annealing of (U) and passivation film 02),! : After heat treatment, the required openings (15a) and (x5b) are formed in the passivation film.
04) is formed, and a cylindrical dose ion implantation of an n-type impurity is performed to form an n+ region (04). Next, Figure 1 (
As shown in e), after annealing the ion-implanted layer o and u< to form an emitter layer (13a) and a collector electrode extraction layer (14a), an opening (15c) for extracting the pace electrode is formed. However, in order to prevent the electrodes from coming off, the metal silicides (16a) to (16c) are connected to the openings (15).
After forming each of a) to (15c), electrode wiring (17
Perform steps a) to (1'7c). In addition, Fig. 1(e)
FIG. 2 shows a planar pattern of the transistor K.
しかしながら、従来の半導体集積回路装置の製造方法で
は、トランジスタの周波数特性はペース・コレクタ容量
(C,。)やペース抵抗(r、、)などに依存するので
、ペース抵抗を下げるための一層(ペース電極取り出し
領域)(9)を形成することはペース・コレクタ容量の
増大をまねく。また、ペース抵抗はエミツタ層であるに
層(13a)とペース電極開口0.ba)との距離(D
、)(第2図参照)にも依存しているが、電極配線(1
7b)および(1tC)の間隔および開口と電極の重ね
合せ分との合計の距離となって、写真製版およびエツチ
ングの向上によって電極間隔が小さくなっても重ね合わ
せ分が残るなどの欠点があった。However, in the conventional manufacturing method of semiconductor integrated circuit devices, the frequency characteristics of the transistor depend on the pace collector capacitance (C, .) and the pace resistance (r, .). Forming the electrode extraction region (9) leads to an increase in pace collector capacity. In addition, the pace resistor has a layer (13a) which is an emitter layer and a pace electrode opening 0. ba) and the distance (D
) (see Figure 2), but the electrode wiring (1
7b) and (1tC), and the total distance between the aperture and the overlapping portion of the electrodes, and even if the electrode spacing becomes smaller due to improvements in photolithography and etching, the overlapping portion remains. .
したがって、この発明の目的はエミッタ拡散とペース電
極取り出し領域がセルファライン(自己整合)されるこ
とによって、ペース抵抗の小はい島周波トランジスタを
製造することができる半導体集積回路装置の製造方法を
提供するものである。Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can manufacture an island frequency transistor with a small pace resistance by self-aligning the emitter diffusion and the pace electrode extraction region. It is something.
このような目的を達成するため、この発明は基板表面に
直接シリコン膜をデポジションし、選択酸化法によって
このシリコン膜のエミッタ拡散領域およびコレクタ電極
数シ出し領域を形成すべき部位の上の部分を除いて酸化
する工程と、この酸化膜をマスクにエミッタ拡散領域お
よびコレクタ電極取り出し領域上に形成されたシリコン
膜に高濃度不純物拡散を行なう工程と、前記基板への前
記シリコン膜から拡散によってエミツタ層を形成したの
ち、前記酸化膜を全面除去し、低温酸化を行なう工程と
、前記高濃度拡散を行なったシリコン膜表面に厚く酸化
膜を形成し、異方性エツチングを行なってこのシリコン
膜の側壁にのみ酸化膜が残るように、この低温酸化膜を
除去する工程と、金属シリサイド膜を基板およびシリコ
ン膜表面に形成したのち、バンシベニション膜ヲテポジ
ションし、次いで低抵抗金属配線す、る工程とを伽える
ものであシ、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention deposits a silicon film directly on the substrate surface, and uses a selective oxidation method to remove the portion of the silicon film above the area where the emitter diffusion region and the collector electrode extraction region are to be formed. a step of oxidizing the silicon film, using this oxide film as a mask, and diffusing a high concentration impurity into the silicon film formed on the emitter diffusion region and the collector electrode lead-out region; After forming the layer, the oxide film is completely removed and low-temperature oxidation is performed, and a thick oxide film is formed on the surface of the silicon film that has been diffused at high concentration, and anisotropic etching is performed to remove the silicon film. After removing the low-temperature oxide film and forming a metal silicide film on the substrate and silicon film surfaces so that the oxide film remains only on the side walls, the bancivention film is deposited, and then low-resistance metal wiring is formed. The process will be explained in detail below using examples.
第3図(a)〜第3図(f)はこの発明に係る半導体集
積回路装置の製造方法の一実施例を製造工程順に示す断
面図である。同図において、(財)はポリシリコン膜、
(2)は窒化膜、翰および(ハ)はそれぞれエミッタ領
域およびコレクタ電極取り出し領域の上のポリシリコン
膜、(ホ)はポリシリコン膜を酸化して形成した酸化膜
、(ハ)および(ロ)は低温酸化によって形成した酸化
膜である。FIGS. 3(a) to 3(f) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of manufacturing steps. In the figure, the foundation is a polysilicon film,
(2) is a nitride film, (c) is a polysilicon film on the emitter region and collector electrode extraction region, respectively, (e) is an oxide film formed by oxidizing the polysilicon film, (c) and (ro) are ) is an oxide film formed by low-temperature oxidation.
次に上記構成による半導体集積回路装置の製造工程につ
いて説明する。まず、従来例の第1 F (a)〜(c
)の工程とほぼ同様にして第3図(a)に示すように分
離酸化膜(6)を形成し、ペース領域(Il)をイオン
注入で形成したのち、酸化膜(3)を全面除去して、ポ
リシリコン膜c2υをデポジションする。さらに、窒化
膜(イ)をデポジションして、エミッタ領域およびコレ
クタの電極数シ出し領域を形成すべき部位上に残るよう
にパターニングする。次に、第3図(b)に示すように
、前記窒化膜(2)をマスクとして選択酸化を行々い、
エミッタ領域ポリシリコン膜(財)。Next, the manufacturing process of the semiconductor integrated circuit device having the above structure will be explained. First, the first F (a) to (c
), an isolation oxide film (6) is formed as shown in FIG. 3(a), a space region (Il) is formed by ion implantation, and the oxide film (3) is completely removed. Then, a polysilicon film c2υ is deposited. Further, a nitride film (a) is deposited and patterned so that it remains on the portion where the emitter region and collector electrode number region are to be formed. Next, as shown in FIG. 3(b), selective oxidation is performed using the nitride film (2) as a mask.
Emitter region polysilicon film.
コレクタ電極数シ出し領域ポリシリコン膜(ハ)を残し
て選択的にポリシリコン膜qυを酸化し、酸化膜に)を
形成する。ここで、窒化膜マスクとして下敷酸化膜を形
成したのち、窒化膜(イ)をデポジションして複合マス
クとして使うこともできる。さらに1次工程のイオン注
入に際して、前記下敷酸化膜を注入保護膜として使うこ
ともできる。次に、第3図(c)に示すように、エミッ
タ領域ポリシリコン膜@およびコレクタ電極数シ出し領
域ポリシリコン膜(ハ)にn形不純物を高濃度にイオン
注入する。このとき、注入領域は酸化膜に)によって決
まる。そして、酸化膜qはイオン注入マスクとして高々
3.0OOA程度でよいので、ポリシリコン膜■υが厚
い時はポリシリコン膜evを少しエツチングしたのちに
、選択酸化してポリシリコン膜シυを完全に酸化してし
まう。次に1前記ポリシリコン膜C4,Hからn形不純
物をそれぞれ拡散させて、エミツタ層(13a) 、コ
レクタ電極取り゛出し領域(14a)を形成したのち、
前記酸化膜に)を全面除去する。次に、第3図(d)
K示すように、低温酸化して酸化膜(イ)および(イ)
を形成する。このとき、よく知られているように、低温
で酸化すればn形ポリシリコン膜脅。The polysilicon film qυ is selectively oxidized, leaving the polysilicon film (c) in the area where the collector electrode is exposed, to form an oxide film (). Here, after forming an underlying oxide film as a nitride film mask, it is also possible to deposit a nitride film (a) and use it as a composite mask. Furthermore, the underlying oxide film can also be used as an implantation protective film during ion implantation in the first step. Next, as shown in FIG. 3(c), n-type impurities are ion-implanted at a high concentration into the emitter region polysilicon film @ and the collector electrode region polysilicon film (c). At this time, the implantation region is determined by the oxide film). The oxide film q can be used as an ion implantation mask at most 3.0OOA, so when the polysilicon film υ is thick, the polysilicon film ev is slightly etched and then selectively oxidized to completely remove the polysilicon film υ. It oxidizes to Next, after diffusing n-type impurities from the polysilicon films C4 and H to form an emitter layer (13a) and a collector electrode extraction region (14a),
(on the oxide film) is removed from the entire surface. Next, Figure 3(d)
As shown in K, oxide films (A) and (A) are formed by low-temperature oxidation.
form. At this time, as is well known, if oxidized at low temperatures, the n-type polysilicon film will be destroyed.
(財)の側壁上の酸化膜(ロ)は厚く、基体のp形ベー
ス領域(11)上の酸化膜(ホ)は薄く形成される。そ
の後に選択酸化に用いた窒化膜(2)を除去し、リアク
ティブ・イオン・エツチング(R工E)などの異方性エ
ツチングを施してポリシリコン膜(4)、(ハ)の側壁
の酸化膜(財)を残してp形ベース領域(1す上の酸化
膜(イ)を除去する。ここで、R工Eで酸化膜(ハ)を
残すように酸化膜エツチングをしたが、通常のエツチン
グ法でp形ベース領域(lll上の酸化膜(7)のみを
除去することも可能である。次に、第3図(e)に示す
ように、金属シリサイド(16a) 、 (16b)
、(16c)をそれぞれコレクタ電極引き出し部ポリシ
リコン膜■。The oxide film (b) on the side wall of the substrate is thick, and the oxide film (e) on the p-type base region (11) of the substrate is thin. After that, the nitride film (2) used for selective oxidation is removed, and anisotropic etching such as reactive ion etching (R-E) is performed to oxidize the sidewalls of the polysilicon films (4) and (c). The oxide film (a) on the p-type base region (1) is removed while leaving the film (material).Here, the oxide film was etched using R-E to leave the oxide film (c). It is also possible to remove only the oxide film (7) on the p-type base region (llll) by etching. Next, as shown in FIG. 3(e), metal silicides (16a) and (16b) are removed.
, (16c) are the collector electrode lead-out polysilicon films.
エミッタ領ポリシリコン膜翰およびp形ベース層(II
)の上に形成する。ここで、ポリシリコン膜に)。Emitter region polysilicon film layer and p-type base layer (II
). (here, to the polysilicon film).
鱒はその表面に金属シリサイド(16b) 、 (16
a)が500A程度の厚さに形成され、それたけポリシ
リコン膜厚が減少するので2000A程度の厚さにして
おく必安がある。また、この膜厚は段差の問題や、厚さ
方向の抵抗値の点から、できるだけ薄いことが望ましく
、上述程度の値が適当である。次に1第3図(f)に示
すように、パッシベーション膜賭を形成したのち、所要
の開口部を設けたのち、アルミニ9ム電極配線(17a
) 、 (x7b) (図示せず) 、(17c)を形
成する。第4図はこの実施例の方法によって得られるト
ランジスタの平面図である。Trout has metal silicide (16b), (16
A) is formed to a thickness of about 500A, and since the thickness of the polysilicon film decreases accordingly, it is necessary to keep the thickness at about 2000A. Further, it is desirable that this film thickness be as thin as possible from the viewpoint of the problem of the step difference and the resistance value in the thickness direction, and the above-mentioned value is suitable. Next, as shown in FIG. 3(f), after forming a passivation film and providing the required openings, an aluminum electrode wiring (17a) is formed.
), (x7b) (not shown), and (17c) are formed. FIG. 4 is a plan view of a transistor obtained by the method of this embodiment.
なお、第3図(a)の段階で選択酸化用マスクとしての
窒化膜(イ)のエミッタ領域形成部位上の部分の幅を変
えることによって、エミッタ領域(1sa)の幅を任意
の値にすることができるのけ勿論である。Note that the width of the emitter region (1sa) can be set to an arbitrary value by changing the width of the portion of the nitride film (a) serving as a mask for selective oxidation on the emitter region formation site in the step of FIG. 3(a). Of course you can.
また、以上pnp)ランジスタについて説明したがnp
n )ランジスタの製造にもこの発明は適用できる。さ
らに、素子分離については酸化膜分離法による場合を示
したが、前述のように各種分離技術が適用できる。Also, although I explained the pnp) transistor above,
n) The present invention can also be applied to the manufacture of transistors. Furthermore, although the case where an oxide film isolation method is used for element isolation has been shown, various isolation techniques can be applied as described above.
以上詳述したように、この発明の方法によれば、エミツ
タ層はその拡散形成に用いた高不純物濃度のシリコン膜
の上の金属シリサイド膜によってエミッタ電極に接続さ
れ、ベース電極はエミッタ領域から上記シリコン膜の側
壁の酸化膜の厚さだけ離れた位置まで延びる金属シリサ
イド膜に接続さス抵抗を極めて小さくすることができる
。式らに、エミッタ拡散がシリコン膜へ導入てれた不純
物を拡散芒せることによって行なうので、制御性がよく
、浅く形成することができ、また、シリコン膜の形状を
容易に小宴くできるので、エミツタ幅も従来より狭くで
きる。As detailed above, according to the method of the present invention, the emitter layer is connected to the emitter electrode by the metal silicide film on the high impurity concentration silicon film used for its diffusion formation, and the base electrode is connected from the emitter region to the emitter electrode. The resistance connected to the metal silicide film extending to a position separated by the thickness of the oxide film on the side wall of the silicon film can be made extremely small. As shown in the formula, emitter diffusion is performed by diffusing impurities introduced into the silicon film, so it has good controllability, can be formed shallowly, and the shape of the silicon film can be easily shaped. The emitter width can also be narrower than before.
第1図は従来のバイポーラ形集積回路装置の製造方法を
説明するためのその主要段階における状態を示す断面図
、第2図は第1図(elに示す従来の方法で得られたト
ランジスタの平面図、第3図はこの発明の一実施例の方
法を説明するためのその主要段階における状態を示す断
面図、第4図は第3図(f) K示すこの実施例になる
トランジスタの平面図である。
図において、(1)はシリコン基板、(3)はコレクタ
層を形成するエピタキシャル成長層、(’りはベース層
、ttzlt?<ツシベーション膜、(ユ3a) ij
エミッタ層、(laa)はコレクタ′電極取り出し領域
、(16a)〜(16c)は金属シリサイド膜、(1’
7a)〜(17c)は電極配線、シυはポリシリコン膜
、(イ)はマスク用窒化膜、啜はエミツタ層形成部位の
上のポリシリコン膜、(ロ)はコレクタ電極取り出し領
域形成部位の上のポリシリコン膜、に)は酸化膜、に)
は薄い酸化膜、@はポリシリコン脱骨、(ハ)の側壁の
厚い酸イヒ膜である。
なお、図中同一符号は同一または相当部分を示すO
代理人 葛野信−(外1名)
第1図
第1図
第3図
第3図Figure 1 is a cross-sectional view showing the state at the main stages of a conventional method for manufacturing a bipolar integrated circuit device, and Figure 2 is a plan view of a transistor obtained by the conventional method shown in Figure 1 (el). Figure 3 is a sectional view showing the state at the main stages for explaining the method of an embodiment of the present invention, and Figure 4 is a plan view of a transistor according to this embodiment shown in Figure 3(f)K. In the figure, (1) is a silicon substrate, (3) is an epitaxial growth layer forming a collector layer, (' is a base layer, ttzlt?<tsivation film, (3a) ij
Emitter layer, (laa) is collector' electrode extraction area, (16a) to (16c) are metal silicide films, (1'
7a) to (17c) are the electrode wiring, υ is the polysilicon film, (a) is the nitride film for the mask, suffix is the polysilicon film on the emitter layer formation area, and (b) is the collector electrode extraction region formation area. The upper polysilicon film, on) the oxide film, on)
(c) is a thin oxide film, @ is a polysilicon boning, and (c) is a thick oxide film on the side wall. In addition, the same reference numerals in the figures indicate the same or equivalent parts.O Agent Makoto Kuzuno (1 other person)
Claims (3)
、ジションし、エミツタ層およびコレクタ電極取り出し
領域を形成すべき部位の上を除く上記シリコン膜の部分
を選択酸化法によって酸化させる第1の工程、この第1
の工程で得られた酸化膜をマスクとして上記エミツタ層
およびコレクタ電極数シ出し領域を形成すべき部位の上
の上記シリコン膜に高濃度に不純物を拡散させる第2の
工程、上記シリコン基板へ上記シリコン膜から上記不純
物を拡散させて上記エミツタ層を形成したのち、上記酸
化膜を除去する第3の工程、上記第1の工程の選択酸化
に用いたマスクを再度マスクとして低温酸化を施して上
記シリコン膜の側壁に厚い酸化膜を、上記第3の工程に
よって露出したシリコン基板の表面に薄い酸化膜を形成
する第4の工程、上記第4の工程で用いた上記マスクを
除去した後に、上記シリコン膜の側壁にけ酸化膜を残し
て上記シリコン基板の表面の上記薄い酸化膜を除去する
第5の工程、上記第5の工程で露出した上記シリコン膜
の上面および上記シリコン基板の表面に金属シリサイド
膜を形成する第6の工程、及び全土面にパッシベーショ
ン膜をデポジション1Jc7)ち上記金属シリサイド膜
の上に所要の電極窓を開孔させ、この電極窓を介して上
記金属シリサイド膜につながる低抵抗金属配線を形成す
る第7の工程を備えたことを特徴とする半導体集積回路
装置の製造方法。(1) A first step of depositing and depositing a silicon film directly on the surface of a silicon substrate, and oxidizing the portion of the silicon film except for the area on which the emitter layer and collector electrode lead-out region are to be formed by selective oxidation; This first
A second step in which impurities are diffused at a high concentration into the silicon film above the portions where the emitter layer and the collector electrode extraction region are to be formed using the oxide film obtained in the step as a mask; After the impurity is diffused from the silicon film to form the emitter layer, a third step of removing the oxide film is performed, and low-temperature oxidation is performed using the mask used for selective oxidation in the first step again as a mask. a fourth step of forming a thick oxide film on the side walls of the silicon film and a thin oxide film on the surface of the silicon substrate exposed in the third step; after removing the mask used in the fourth step; a fifth step of removing the thin oxide film on the surface of the silicon substrate while leaving an oxide film on the sidewalls of the silicon film; and a fifth step of removing metal on the upper surface of the silicon film exposed in the fifth step and on the surface of the silicon substrate. 6th step of forming a silicide film and depositing a passivation film on the entire surface 1Jc7) A required electrode window is opened on the metal silicide film and connected to the metal silicide film through this electrode window. A method of manufacturing a semiconductor integrated circuit device, comprising a seventh step of forming a low-resistance metal wiring.
とを特徴とする特許請求の範囲第1項記載の半導体集積
回路装置の製造方法。(2) A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that a polysilicon film is used as the silicon film.
板の表面の薄い酸化膜を除去することを特徴とする特許
請求の範囲第1項または第2項記載の半導体集積回路装
置の製造方法。(3) The method for manufacturing a semiconductor integrated circuit device according to claim 1 or 2, characterized in that in the fifth step, a thin oxide film on the surface of the silicon substrate is removed by an anisotropic etching method. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19277382A JPS5980968A (en) | 1982-11-01 | 1982-11-01 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19277382A JPS5980968A (en) | 1982-11-01 | 1982-11-01 | Manufacture of semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5980968A true JPS5980968A (en) | 1984-05-10 |
JPH0136709B2 JPH0136709B2 (en) | 1989-08-02 |
Family
ID=16296781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19277382A Granted JPS5980968A (en) | 1982-11-01 | 1982-11-01 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5980968A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61147572A (en) * | 1984-12-20 | 1986-07-05 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0323698U (en) * | 1989-07-18 | 1991-03-12 |
-
1982
- 1982-11-01 JP JP19277382A patent/JPS5980968A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61147572A (en) * | 1984-12-20 | 1986-07-05 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH0136709B2 (en) | 1989-08-02 |
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