JPS61104615A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61104615A JPS61104615A JP22704584A JP22704584A JPS61104615A JP S61104615 A JPS61104615 A JP S61104615A JP 22704584 A JP22704584 A JP 22704584A JP 22704584 A JP22704584 A JP 22704584A JP S61104615 A JPS61104615 A JP S61104615A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- resist film
- resist
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000011800 void material Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 230000002093 peripheral effect Effects 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 230000004913 activation Effects 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- -1 boron ions Chemical class 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、詳しくは半導体装置の
製造工程において、レジストをマスクにして多結晶シリ
コン（ポリシリコン）を通して、また番Ｊポリシリコン
中へ不純物イオン注入を行う際に、不純物が注入されて
はならない（ドープされてはならない）領域への不純物
の拡散を防止するための方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, more specifically, in the manufacturing process of a semiconductor device, a polycrystalline silicon (polysilicon) is passed through using a resist as a mask. The present invention relates to a method for preventing impurities from diffusing into regions where impurities should not be implanted (doped) when impurity ions are implanted into silicon.
例えば第２図の断面図を参照すると、１ばシリコン基板
、２はヘース領域、３はエミッタ領域、４は絶縁膜（二
酸化シリコン１漠、５ｉｏ２１１央）、５はポリシリコ
ン膜、６はアルミニウム（八７り％極を示す。ここでポ
リシリコン１漠５が敷かれてぃなかったとすると、基板
のシリコン（Ｓｉ）がＡｎ電極６によって吸収され、そ
してｉが基板中に析出する。この析出へｌの量が多いと
八βがエミッタ領域３を突き抜けてヘース領域２に入り
込み短絡を起す原因となる。そこでポリシリコン膜５を
敷いて、基板からのＳｉの吸収と基板内への八ｅの析出
を防止するものである。For example, referring to the cross-sectional view of FIG. 2, 1 is a silicon substrate, 2 is a heath region, 3 is an emitter region, 4 is an insulating film (silicon dioxide 1, 5io211 center), 5 is a polysilicon film, 6 is aluminum ( 87% pole.Here, if polysilicon 1 and 5 were not spread, the silicon (Si) of the substrate would be absorbed by the An electrode 6, and i would precipitate into the substrate. If the amount of l is large, the 8β will penetrate the emitter region 3 and enter the heath region 2, causing a short circuit.Therefore, a polysilicon film 5 is laid to prevent the absorption of Si from the substrate and the absorption of 8e into the substrate. This prevents precipitation.
シリコン基板上に前記の如くポリシリコンを敷いた後に
当該基板に不純物をイオン注入により拡散する例を第３
図を参照して説明する。The third example shows an example in which polysilicon is spread on a silicon substrate as described above and then impurities are diffused into the substrate by ion implantation.
This will be explained with reference to the figures.
第３図（ａ）に示される如く、半導体基板１１には既に
ｐ型頭域１２が形成され、ＳｉＯ２膜１３には電極窓が
形成され、全面にポリシリコン膜１４が敷かれている。As shown in FIG. 3(a), a p-type head region 12 is already formed on the semiconductor substrate 11, an electrode window is formed on the SiO2 film 13, and a polysilicon film 14 is spread over the entire surface.
ここで、領域１５をＢ＋型に拡散するために、レジスト
膜１６を図示の如くパターニングし、レジスＩ−１１Ｗ
１６をマスクにして例えば砒素（Ａｓ” ）を図に矢
印で示す如くに注入する。図にイオン注入された領域は
砂地を付して示す。Here, in order to diffuse the region 15 into B+ type, the resist film 16 is patterned as shown in the figure, and the resist film 16 is patterned as shown in the figure.
Using 16 as a mask, for example, arsenic (As'') is implanted as shown by the arrow in the figure.The ion-implanted area is shown with a sandy background in the figure.
次いでレジストを除去し活性化と拡散のための熱処理を
行うと、第３図Ｉ：ｂ）に示される如く不純物がドーピ
ング（添加）される領域（図には（ａ）の場合の如く砂
地を付して示す）は横方向に拡がる（横方向拡散）。そ
の結果、ｐ型頭域１２とその上のポリシリコン膜とが不
必要にドーピングされ、コンタクト抵抗が大になる問題
が発生ずる。Next, the resist is removed and heat treatment is performed for activation and diffusion, and the area where impurities are doped (added) as shown in Figure 3 (I: b) (the figure shows a sandy area as in the case of (a)). ) spreads laterally (lateral diffusion). As a result, the p-type head region 12 and the polysilicon film thereon are unnecessarily doped, resulting in a problem of increased contact resistance.
半導体装置の微細化の要求に答えるため最近第３図（ｂ
）にＤで示す絶縁膜の幅は最大１０μｍ程度に抑えなけ
ればならず、このように小なる領域は前記した熱処理に
より容易に１・−ピングされる傾向にある。In order to meet the demand for miniaturization of semiconductor devices, recently
) The width of the insulating film indicated by D must be kept to a maximum of about 10 .mu.m, and such a small region tends to be easily 1.-pinged by the heat treatment described above.
本発明は、上記問題点を）Ｗ消した半導体装置の製造方
法を提供するもので、その手段は、半導体基板上に絶縁
膜を形成し、この絶縁膜に電極窓開きをなし、全面に多
結晶シリコン膜を形成する］−程、全面にレジスト膜を
形成し、このレジスト股を前記電極窓に対応してパター
ニングし、しかる後にレジスト膜をマスクに不純物をイ
オン注入する工程、前記レジスＩ〜膜をそのまま残しペ
リフェラルエツチングによりレジスト膜に接するポリシ
リコン膜をエツチングして当該ポリシリコン膜に空隙部
を形成する工程、および熱処理を行う工程を含むことを
特徴とする半導体装置の製造方法によってなされる。The present invention provides a method for manufacturing a semiconductor device that eliminates the above-mentioned problem (W), and its means include forming an insulating film on a semiconductor substrate, forming an electrode window in the insulating film, and forming a multilayer film over the entire surface. forming a crystalline silicon film] - step of forming a resist film on the entire surface, patterning the resist crotch corresponding to the electrode window, and then ion-implanting impurities using the resist film as a mask; A method for manufacturing a semiconductor device comprising: a step of etching a polysilicon film in contact with a resist film by peripheral etching, leaving the film as is, to form a void in the polysilicon film; and a step of performing heat treatment. .
上記した方法は、レジストをマスクとして、ポリシリコ
ンを通しまたはポリシリコン中へ不純物のイオン注入を
行う場合に、イオン注入後、前記レジストを利用するペ
リフェラルエツチングを行って、不純物のポリシリコン
中での横方向拡散を防止するものである。In the above method, when impurity ions are implanted through or into polysilicon using a resist as a mask, after the ion implantation, peripheral etching is performed using the resist to remove the impurities in the polysilicon. This prevents lateral diffusion.
本発明の方法を実施する工程における半導体装置要部を
断面図で示す第１図を参照して本発明実施例を説明する
。Embodiments of the present invention will be described with reference to FIG. 1, which shows a cross-sectional view of essential parts of a semiconductor device in a step of carrying out the method of the present invention.
第１図（ａ）：
ｎ型半導体基板２１上に１０００人の膜厚の絶縁膜（Ｓ
ｉＯ２膜）２２を通常の熱酸化法で形成し、次いでレジ
スＩ・膜２３を塗布形成し、このレジスト膜を図示の如
くパターニングし、このレジスト膜２３をマスクにして
、ボロン（Ｂ＋）を、６０ ＫｅＶ、ドーズｆｆ１５Ｘ
］、ｏ ｃｍ ２でイオン注入し、ｐ型不純物拡散
領域を作る。次いで、レジスト膜２３を除去し、活性化
と拡散のために、１０００℃、乾Ｎ２ガス雰囲気で５０
分熱処理をなし、ｐ型頭域２４を形成する。FIG. 1(a): An insulating film (S
iO2 film) 22 is formed by a normal thermal oxidation method, then a resist I film 23 is formed by coating, this resist film is patterned as shown in the figure, and using this resist film 23 as a mask, boron (B+) is 60 KeV, dose ff15X
], o cm 2 to form a p-type impurity diffusion region. Next, the resist film 23 is removed, and the resist film 23 is heated for 50 minutes at 1000°C in a dry N2 gas atmosphere for activation and diffusion.
A heat treatment is performed to form a p-type head region 24.
第１図（ｂ）：
５ｉＯ２１１襲２２に電極窓開きをなし、次いで全面に
ポリシリコンを１０００人の１模厚に成長し、ポリシリ
コン膜２５を形成する。FIG. 1(b): An electrode window is formed in the 5iO2 layer 22, and then polysilicon is grown on the entire surface to a thickness of 1,000 mm to form a polysilicon film 25.
第１図（Ｃ）ニ
レジストを全面に塗布して作られるレジスト膜２６を次
の不純物イオン注入のためにパターニングし、次いで、
八Ｓ＋を１００ ＫｅＶ、ドーズ量５ Ｘ １０”ｃｍ
−２のドース量で図に矢印で示す如くにイオン注入する
と、ポリシリコン中に図に砂地で示す如く不純物が打ち
込まれる。FIG. 1(C) A resist film 26 made by coating the entire surface with Ni-resist is patterned for the next impurity ion implantation, and then
8S+ at 100 KeV, dose 5 x 10”cm
When ions are implanted at a dose of -2 as shown by the arrow in the figure, impurities are implanted into the polysilicon as shown by the sandy area in the figure.
第１図（ｄ）：
イオン注入のときにマスクとして用いたレジス１−１１
Ｗ ２３はそのまま残しておいて例えば（０２→−Ｃα
す）ガスを用いるペリフェラル（周辺）工・ノチングを
行うと、ポリシリコン膜２５のレジスト膜の周辺（ペリ
フェラル）部分のみが第１図（ａ）に図示の如くエツチ
ングされ、ポリシリコン膜２５に空隙部２５ａが形成さ
れる。Figure 1(d): Resist 1-11 used as a mask during ion implantation
For example, leave W 23 as is and write (02→-Cα
) When peripheral processing and notching using gas is performed, only the peripheral (peripheral) portion of the resist film of the polysilicon film 25 is etched as shown in FIG. 1(a), leaving voids in the polysilicon film 25. A portion 25a is formed.
前記した空隙部２５ａがポリシリコン膜に形成されてい
るために、第３図（ｂｌを参照して説明したレジスｌ−
膜の除去後の熱処理において、ポリシリコン１挨内の横
方向の不純物拡散は断ち切られ、ｐ型領域の上方のポリ
シリコン膜のドーピングが防止される。Since the void portion 25a described above is formed in the polysilicon film, the resist l-
In the heat treatment after film removal, lateral impurity diffusion within the polysilicon layer 1 is cut off and doping of the polysilicon layer above the p-type region is prevented.
第１図（ｅｌに本発明の方法を用いて作ったバイポーラ
１〜ランジスタが示され、２８はヘース領域である。そ
の他の部分は同図（ａ）に示すものと同じである。図示
の例で、ｄで示す部分は１〜５μｍの幅に形成可能であ
った。FIG. 1 (el) shows bipolar transistors 1 to 1 to transistors made using the method of the present invention, and 28 is a heath region.Other parts are the same as those shown in FIG. 1(a).Example shown The portion indicated by d could be formed to have a width of 1 to 5 μm.
なお、本発明の適用範囲は例示のバイポーラ）・□ラン
シスタの場合に限定されるものでなく、その他のデバイ
スの製造にも適用可能であり、また、ポリシリコン膜そ
れ自体にイオン注入を行う場合にも適用されうるちので
ある。The scope of application of the present invention is not limited to the exemplified bipolar)/□Run transistors, but can also be applied to the manufacture of other devices. It also applies to Uruchino.
以上説明したように本発明によれば、イオン注入に用い
たレジスト膜をそのまま残しておき、ペリフェラルエツ
チングによりポリシリコン膜に空隙部を形成することに
より、ポリシリコンを通してまたはポリシリコン中へイ
オン注入を行う場合、後の熱処理においてイオン注入さ
れた不純物のポリシリコン内での横方向拡散が防止され
、従来経験されたコンタクト抵抗の増大などが発生しな
くなる効果がある。As explained above, according to the present invention, ions are implanted through or into polysilicon by leaving the resist film used for ion implantation intact and forming voids in the polysilicon film by peripheral etching. If this is done, lateral diffusion of ion-implanted impurities within the polysilicon during subsequent heat treatment is prevented, and there is an effect that increases in contact resistance, etc., which have been experienced in the past, do not occur.
第１図（ａｌ〜（ｃｊは本発明一実施例の各工程断面図
、第２図はポリシリコン膜を用いたエミッタ電極を示す
断面図、第３図はｔｊｆｌ来法によるポリシリコン膜を
通したイオン注入工程を示す図である。
図中、２１はシリコン制板、２２ば ＳｉＯ２膜、２３
はレジスト膜、２４ばｐ型領域、２５はポリシリコン膜
、２６はレジスト１漠、２７はエミッタ領域、２８ばヘ
ース領域、をそれぞれ示す。
第１図
第１図Figure 1 (al~(cj) is a cross-sectional view of each step of an embodiment of the present invention, Figure 2 is a cross-sectional view of an emitter electrode using a polysilicon film, and Figure 3 is a cross-sectional view of an emitter electrode using a polysilicon film using the tjfl conventional method. 2 is a diagram showing the ion implantation process. In the diagram, 21 is a silicon plate, 22 is a SiO2 film, and 23 is a silicon plate.
24 is a resist film, 24 is a p-type region, 25 is a polysilicon film, 26 is a resist layer, 27 is an emitter region, and 28 is a base region. Figure 1Figure 1
Claims (1)
開きをなし、全面に多結晶シリコン膜を形成する工程、
全面にレジスト膜を形成し、このレジスト膜を前記電極
窓に対応してパターニングし、しかる後にレジスト膜を
マスクに不純物をイオン注入する工程、前記レジスト膜
をそのまま残しペリフェラルエッチングによりレジスト
膜に接するポリシリコン膜をエッチングして当該ポリシ
リコン膜に空隙部を形成する工程、および熱処理を行う
工程を含むことを特徴とする半導体装置の製造方法。A step of forming an insulating film on a semiconductor substrate, forming an electrode window in this insulating film, and forming a polycrystalline silicon film on the entire surface;
A resist film is formed on the entire surface, this resist film is patterned corresponding to the electrode window, and then impurity ions are implanted using the resist film as a mask. A method for manufacturing a semiconductor device, comprising the steps of etching a silicon film to form a void in the polysilicon film, and performing heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22704584A JPS61104615A (en) | 1984-10-29 | 1984-10-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22704584A JPS61104615A (en) | 1984-10-29 | 1984-10-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61104615A true JPS61104615A (en) | 1986-05-22 |
Family
ID=16854659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22704584A Pending JPS61104615A (en) | 1984-10-29 | 1984-10-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61104615A (en) |
-
1984
- 1984-10-29 JP JP22704584A patent/JPS61104615A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6252950B2 (en) | ||
| JPS61104615A (en) | Manufacture of semiconductor device | |
| JPS624339A (en) | Semiconductor device and manufacture thereof | |
| JP2576664B2 (en) | Method for manufacturing NPN transistor | |
| JPH06163576A (en) | Manufacture of semiconductor device | |
| JPS6220711B2 (en) | ||
| JPS6129538B2 (en) | ||
| JP3311082B2 (en) | Method for manufacturing semiconductor device | |
| JPH0474463A (en) | Manufacture of semiconductor device | |
| JP2727576B2 (en) | Method for manufacturing semiconductor device | |
| JP2624365B2 (en) | Method for manufacturing semiconductor device | |
| JPH0226034A (en) | Manufacture of semiconductor device | |
| JPH0254539A (en) | Manufacture of vertical mos-fet | |
| JPH0428246A (en) | Semiconductor device and manufacture thereof | |
| JPH03222480A (en) | Semiconductor device and manufacture thereof | |
| JPH0274042A (en) | Manufacture of mis transistor | |
| JPH0230145A (en) | Manufacture of semiconductor device | |
| JPH0691097B2 (en) | Method for manufacturing semiconductor device | |
| JPH033246A (en) | Manufacture of semiconductor device | |
| JPH06120243A (en) | Manufacture of semiconductor device | |
| JPS6365671A (en) | Manufacture of semiconductor device | |
| JPH0258230A (en) | Manufacture of bipolar transistor | |
| JPH1065156A (en) | Manufacturing method for semiconductor device | |
| JPH053210A (en) | Manufacture of semiconductor device | |
| JPH0387034A (en) | Manufacture of semiconductor device |