JP2576664B2 - Method for manufacturing NPN transistor - Google Patents

Description

The present invention relates to a method for manufacturing an NPN transistor, and more particularly to a method for manufacturing an NPN transistor in which an emitter region is formed by diffusion from an impurity-doped polysilicon film.

[Conventional technology]

Conventionally, in this type of NPN transistor manufacturing method, the emitter is formed as follows. First, as shown in FIG. 3A, a polysilicon film 6 is deposited on a P-type base region 4 on the substrate surface, and an N-type impurity such as As is ion-implanted into the polysilicon film 6 using a photoresist film as a mask. Then, as shown in FIG. 3C, annealing is performed to form an N ⁺ type emitter region 8 under the polysilicon, and the polysilicon film 6 is patterned to form an emitter polysilicon 6 '.
To form an emitter composed of the N ⁺ -type emitter region 8 and the emitter polysilicon 6 ′.
After forming a contact hole 10 by etching, a reflow treatment of the interlayer insulating film is performed as shown in FIG. 3D, and a polysilicon film 11 is formed as shown in FIG. To adhere. This step is for applying a polysilicon film to a contact portion with an active region other than the emitter (not shown). Next, as shown in FIG. 3 (f), a metal film is applied and patterned to form a metal wiring such as an emitter electrode. After that, heat treatment is performed,
An alloy is formed at the contact between the emitter electrode 12 and the polycrystalline silicon.

[Problems to be solved by the invention]

In the above-described conventional method of manufacturing an NPN transistor, the effect of lowering the impurity concentration due to heat treatment such as alloying after the formation of the emitter electrode has an effect on the emitter polysilicon 6 'and on the polysilicon acting as a part of the emitter. There is a drawback that the thickness is reduced, the effective emitter width is reduced, and this causes fluctuations in the electrical characteristics of the transistor.

[Means for solving the problem]

The method of manufacturing an NPN transistor according to the present invention includes the steps of forming a polysilicon film doped with an N-type impurity on a P-type base region on a substrate surface and then performing a heat treatment to form an N ⁺ -type emitter region. The method further comprises a step of forming an interlayer insulating film having a contact hole on the polysilicon film, and then introducing an N-type impurity into the polysilicon film again through the contact hole.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (g) are sectional views shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1 (a), a P-type silicon substrate
After forming an N-type impurity region 2a in 1a, an N-type epitaxial layer 3a is formed, and a silicon oxide film having a thickness of about 60 nm is formed in a predetermined region (where a base region of an NPN transistor is formed).
5a is formed, and a P-type impurity is selectively implanted through the silicon oxide film 5a to form a P-type base region 4a. After that, the silicon oxide film 5a is etched to form an emitter contact, and the impurity-introduced polysilicon is grown to a thickness of about 200 nm to form a polysilicon film 6a.
To form

Next, as shown in FIG. 1B, the photoresist film 7a
Polysilicon film on emitter contact with mask
6a, arsenic is accelerated at an energy of 30 to 70 keV, preferably 50 k
After ion implantation of about 1.0 × 10 ¹⁶ cm ⁻² at eV to introduce an N-type impurity and remove the photoresist film 7a, a heat treatment at 1000 ° C. for about 40 minutes is performed as shown in FIG. At the same time as activating the polysilicon surface, the impurities in the polysilicon are diffused into the NPN transistor base region to form an N ⁺ -type emitter region 8a. In this case, the junction depth is about 0.1 to 0.3 μm. Thereafter, the polysilicon film is etched using the metal film as a mask to form an emitter polysilicon 6a '. Next, an interlayer insulating film 9a is formed, and after isotropic etching, anisotropic etching is performed to open contact holes.

Thereafter, as shown in FIG. 1 (d), except for the contact holes in the emitter polysilicon portion, the other portions are formed of a photoresist film 13.
After covering with arsenic at an acceleration energy of 30 to 70 keV, preferably 50 keV, about 5 × 10 ¹⁵ cm ^{−2 is} ion-implanted, an N-type impurity is introduced into the emitter polysilicon, and the photoresist film 13 is removed. As shown in FIG.
A heat treatment of about 5 minutes at 00 ° C. activates the polysilicon surface, and a high concentration N ⁺ region 14a is formed in the emitter polysilicon.
To form Thus, the N ⁺ type emitter region 8a and the high concentration
An emitter composed of the emitter polysilicon 6a 'provided with the N ⁺ type region 14a is formed.

Next, as shown in FIG.
a is grown to a thickness of about 50 nm, and then, as shown in FIG. 1 (g), a metal film for electrodes and wirings is formed thereon and patterned to form an emitter electrode 12 in the contact hole.
Form a. After that, heat treatment is performed, and the emitter electrode 12a is formed.
A process for forming an alloy of metal and polysilicon is performed. Due to the high concentration of N ⁺ regions, the emitter polysilicon 6a 'can sufficiently function as a part of the emitter even when the impurity concentration is reduced as described above.

2 (a) to 2 (d) are cross-sectional views showing the steps in order to explain the second embodiment.

After the steps described with reference to FIGS. 1A to 1C in the first embodiment, as shown in FIG. 2A, the interlayer insulating film is heat-treated at 900 ° C. to form contact holes. Smooth the etched surface. Thereafter, as shown in FIG. 2 (b), after growing a polysilicon film 11b to a thickness of about 50 nm, arsenic is accelerated by covering the other portions with a photoresist film 15 except for the contact holes in the emitter polysilicon portion. At an energy of 50keV,
After ion implantation of about 5 × 10 ¹⁵ cm ⁻² , an N-type impurity is introduced into the emitter polysilicon 6b ′, the photoresist film 15 is removed, and a heat treatment is performed at 1000 ° C. for about 5 minutes to remove the polysilicon surface. Activate to form a high concentration N ⁺ region 14b in the emitter polysilicon. Subsequent steps are the same as in the first embodiment.

Polysilicon film 11b on emitter polysilicon 6b '
Since A _s is doped to a decrease in the impurity concentration of the emitter polysilicon is even less.

〔The invention's effect〕

As described above, the present invention has a step of forming a high-concentration N ⁺ region only near the surface of the emitter polysilicon without affecting the N ⁺ type emitter region under the emitter polysilicon. In the subsequent alloying heat treatment to make contact with the emitter electrode, the impurity concentration of the emitter polysilicon is prevented from decreasing and the effective emitter width is prevented from changing, so that the electrical characteristics of the NPN transistor are prevented from changing. There is an effect that can be.

[Brief description of the drawings]

1 (a) to 1 (g) are cross-sectional views showing a process sequence for explaining a first embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are second embodiments of the present invention. 3 (a) to 3 (f) are cross-sectional views showing the order of steps for explaining a conventional example. 1, 1a, 1b: P-type silicon substrate, 2, 2a, 2b: N-type impurity region, 3, 3a, 3b: N-type epitaxial layer, 4, 4a, 4b ...
P-type base region, 5,5a, 5b ... Silicon oxide film, 6,6a, 6b
... Polysilicon film, 6 ', 6a', 6b '... Emitter polysilicon, 7,7a ... Photoresist film, 8,8a, 8b ... N ⁺
Type emitter region, 9, 9a, 9b, 9 ', 9a', 9b ... interlayer insulating film, 10 ... contact hole, 11, 11a, 11b ... polysilicon film, 12, 12a, 12b ... emitter electrode, 13 ... photoresist film, 14a, 14b ... high concentration N ⁺ region, 15 ... photoresist film.

Claims (2)

(57) [Claims] An NPN having a step of forming a polysilicon film doped with an N-type impurity on a P-type base region on a substrate surface and then performing a heat treatment to form an N ⁺ -type emitter region.
A method of manufacturing a transistor, comprising: forming an interlayer insulating film having a contact hole on the polysilicon film, and then introducing an N-type impurity into the polysilicon film again through the contact hole. Manufacturing method. 2. The NP according to claim 1, wherein the N-type impurity is arsenic.
Manufacturing method of N transistor.