JPH05243249A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To manufacture a bipolar transistor having a so-called an LGE structure and excellent characteristics without increasing at least the steps. CONSTITUTION:An opening 22 of a pattern of an emitter region is formed in an SiO2 film 21, and covered with a polycrystalline Si film 24. As is ion implanted in a low concentration in the film 24, a sidewall made of an SiO2 film 25 is formed on a step, as is again ion implanted in a high concentration. The As is diffused from the film 24 by annealing to form an n<-> type impurity region 27 for constituting an emitter region and an n<+> type impurity region 28. The film 24 becomes an emitter lead electrode, and since the sidewall is formed on the film 24, the emitter region is not damaged by an RIE for forming the sidewall.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to so-called LGE (Laterall).
y Graded Emitter) structure bipolar transistor manufacturing method.

[0002]

2. Description of the Related Art In order to prevent the current amplification factor h _{FE from} being deteriorated by the hot carrier effect due to the application of a reverse bias between the emitter and the base, a high concentration impurity region is formed on the surface of a semiconductor substrate with a low concentration impurity A bipolar transistor having an LGE structure surrounded by a region and using these impurity regions as an emitter region to relax an electric field between the emitter and the base is considered.

In order to manufacture this bipolar transistor having the LGE structure, conventionally, a low-concentration impurity region is first formed in an opening for an emitter region provided in an insulating film covering a semiconductor substrate, and then a sidewall is formed in the opening. Then, a high-concentration impurity region is formed using the insulating film and the side wall as a mask to form an emitter region (for example, SDM91-35).
p. 17-22).

[0004]

However, in order to form a side wall in the opening for the emitter region, after depositing an insulating film or the like on the entire surface, RIE is performed on the entire surface of the insulating film or the like.
I do. For this reason, the emitter region is damaged by RIE, or the emitter region is etched and the base width varies, so that the characteristics such as the current amplification factor h _FE vary. Therefore, the conventional manufacturing method described above cannot manufacture a bipolar transistor having excellent characteristics.

[0005]

According to a first aspect of the present invention, there is provided a method of manufacturing a bipolar transistor, wherein a step of forming an opening 22 having a pattern of an emitter region in an insulating film 21 covering a semiconductor substrate 14 and a first impurity are relatively performed. Covering the opening 22 with a semiconductor film 24 containing a low concentration;
Forming a side wall 25 at a step portion corresponding to the opening 22; introducing a second impurity into the semiconductor film 24 at a relatively high concentration using the side wall 25 as a mask; And diffusing the first and second impurities from the film 24 into the semiconductor substrate 14 through the opening 22 to form first and second impurity regions 27 and 28.

According to a second aspect of the present invention, there is provided a method of manufacturing a bipolar transistor, which comprises a step of forming an opening 22 having a pattern of a second impurity region 28 in an insulating film 21 covering a semiconductor substrate 14, and the semiconductor film 21 being used as a mask. The step of forming the first impurity region 27 by ion-implanting the first impurity into the base 14 in an oblique direction at a relatively low concentration, and the semiconductor film 24 containing the second impurity at a relatively high concentration. A step of covering the opening 22, and the opening 22 from the semiconductor film 24.
And the step of diffusing the second impurity into the semiconductor substrate 14 via the via to form the second impurity region 28.

[0007]

In the method of manufacturing the bipolar transistor according to the first aspect, the first impurity region 2 of the emitter region is formed by using the side wall 25 as a mask when introducing the second impurity.
Although the second impurity region 28 is formed in the semiconductor 7, the side wall 25 is formed on the semiconductor film 24 which will be the emitter extraction electrode. Therefore, the emitter region is not damaged by the etching for forming the side wall 25.

In the method of manufacturing a bipolar transistor according to a second aspect of the present invention, the first impurity region of the emitter region is implanted by obliquely implanting the first impurity so that the first impurity is buried under the edge of the insulating film 21. 27 is formed and the impurity region 28 is formed corresponding to the opening 22, the second impurity region 28 is formed in the first impurity region 27 of the emitter region.
No side wall is required to form the impurity region 28 of FIG. Therefore, the emitter region is not damaged by the etching for forming the side wall.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention applied to the manufacture of an npn bipolar transistor will be described below with reference to FIGS.
Will be described with reference to.

FIG. 1 shows the LG manufactured according to the first embodiment.
2 shows an E-structured npn bipolar transistor,
2-8 has shown 1st Example which is the manufacturing process. In the first embodiment, as shown in FIG. 2, p-type Si
First, the n ⁺ buried layer 12 is selectively formed on the surface of the substrate 11. Then, the n-type epitaxial layer 13 is
It is formed on the Si substrate 11 with a thickness of about m
A Si substrate 14 is formed by 1 and the epitaxial layer 13.

After that, a SiO ₂ film 15 is formed on the surface of the element isolation region of the epitaxial layer 13 by the LOCOS method.
Using this SiO ₂ film 15 as a mask, the epitaxial layer 1
3 is ion-implanted with BF ₂ and p is a true base region.
A type impurity region 16 is formed.

Then, BF ₂ is ion-implanted into the epitaxial layer 13 using a resist (not shown) as a mask,
A p ⁺ type impurity region 17 which is a graft base region, that is, a base electrode extraction region is formed, and Phos is formed on the epitaxial layer 13 using another resist (not shown) as a mask.
Are ion-implanted into the collector electrode extraction region n ⁺
A type impurity region 18 is formed.

After that, a SiO ₂ film 21 is deposited on the entire surface, and openings 22 of the pattern in the emitter region are formed in the impurity region 1.
6 is formed on the SiO ₂ film 21. When this npn bipolar transistor is formed in a BiCMOS integrated circuit device, a SiO ₂ film 23 as a gate oxide film is formed on the surface of the element active region of the epitaxial layer 13 as shown in the figure.

Next, as shown in FIG. 3, a polycrystalline Si film 24 having a film thickness of about 150 nm is deposited on the entire surface, and As is deposited on the polycrystalline Si film 24 at an acceleration energy of about 50 keV.
× implanted into the dose of about 10 ¹³ cm ^-2. Then, as shown in FIG. 4, SiO _{2 having} a film thickness of about 200 nm is formed.
The film 25 is deposited on the entire surface by the CVD method.

Next, RI is applied to the entire surface of the SiO ₂ film 25.
By carrying out E, as shown in FIG. 5, a side wall made of the SiO ₂ film 25 is formed in the step portion of the polycrystalline Si film 24 corresponding to the opening 22. Then, using the side wall made of the SiO ₂ film 25 as a mask, As is ion-implanted into the polycrystalline Si film 24 at an acceleration energy of about 50 keV and at a dose of about 5 × 10 ¹⁶ cm ^-2 .

As a result, the concentration of As in the polycrystalline Si film 24 becomes high except for the step portion of the polycrystalline Si film 24 corresponding to the opening 22 and the portion below the SiO ₂ film 25. After that, as shown in FIG. 6, the polycrystalline Si film 24 is processed into a pattern of the emitter extraction electrode.

Next, as shown in FIG. 7, a SiO ₂ film 26 which also serves as an interlayer insulating film and a capping film during annealing is deposited on the entire surface. Then, the polycrystalline Si is annealed for about 20 minutes in an N ₂ atmosphere at a temperature of about 900 ° C.
A from the film 24 to the epitaxial layer 13 through the opening 22
diffuse s.

However, as described above, the polycrystalline Si film 24
The concentration of As in the inside is not uniform, and in the portion of the polycrystalline Si film 24 that is in contact with the epitaxial layer 13, the concentration of the portion surrounded by the side wall made of the SiO ₂ film 25 is the concentration of the other portion. Higher than.

Therefore, as shown in FIG. 8, the n ⁻ -type impurity region 27 is contained in the impurity region 16 due to As diffused into the epitaxial layer 13 only from the portion of the polycrystalline Si film 24 having a low As concentration. Formed on the polycrystalline silicon film 2
4 diffuses laterally in the epitaxial layer 13 from the As-rich portion,
An n ⁺ type impurity region 28 surrounded by the impurity region 27 is formed in the impurity region 16.

As a result, an emitter region composed of the impurity regions 27 and 28 is formed, the impurity region 16 immediately below the impurity region 28 becomes the true base region, and the n-type epitaxial layer 13 immediately below the impurity region 28 becomes the true collector. Become an area. After that, as shown in FIG. 1, the SiO ₂ film 26,
21 and the like to form contact holes 31 to 33, and the Al electrodes 34 to 31 are used as emitter electrodes, base electrodes and collector electrodes.
36 is formed.

FIG. 9 shows LG manufactured according to the second embodiment.
2 shows an E-structured npn bipolar transistor,
10 to 13 show a second embodiment which is the manufacturing process thereof. Also in this second embodiment, as shown in FIG.
Until the opening 22 is formed in the O ₂ film 21, a process substantially similar to the process of FIG. 2 in the first embodiment described above is executed. However, the opening 22 is formed in the pattern of the n ⁺ type impurity region 28 to be formed later.

In the second embodiment, after that, the SiO ₂ film 21 is used as a mask to form Phos on the epitaxial layer 13.
Is ion-implanted with an acceleration energy of about 15 keV to a dose amount of about 7 × 10 ¹³ cm ⁻² , and an n ⁻ -type impurity region 2 is formed.
Form 7.

However, at this time, as apparent from FIG. 10, S
While rotating the i substrate 14, ion implantation is performed from an oblique direction of at least 10 ° or more, preferably about 45 ° with respect to the normal line to the surface of the i substrate 14. Therefore, the impurity region 27 has the opening 2
It is formed so as to go under the edge of the SiO ₂ film 21 from ₂ .

When this npn bipolar transistor is formed in the BiCMOS integrated circuit device as described above, the ion implantation from the oblique direction in the step of FIG. It is also performed to form.

Next, as shown in FIG. 11, a polycrystalline Si film 24 having a film thickness of about 150 nm is deposited on the entire surface, and As is 5 × 10 ¹⁶ cm in the polycrystalline Si film 24 at an acceleration energy of about 50 keV. Ion implantation is performed at a dose of about ^-2 . Then, as shown in FIG. 12, the polycrystalline Si film 24 is processed into a pattern of the emitter extraction electrode.

Next, as shown in FIG. 13, a SiO ₂ film 26 which also serves as an interlayer insulating film and a capping film during annealing is deposited on the entire surface. And N _{2 at} a temperature of about 900 ° C.
Anneal in the atmosphere for about 20 minutes to obtain polycrystalline Si
A from the film 24 to the epitaxial layer 13 through the opening 22
s is diffused to form an n ⁺ type impurity region 28 in the impurity region 16.

At this time, the impurity region 28 is formed so as to correspond to the opening 22, while the impurity region 27 is formed so as to penetrate under the edge of the SiO ₂ film 21 from the opening 22 as described above. The impurity region 28 is surrounded by the impurity region 27. After that, as shown in FIG. 9, the SiO ₂ films 26, 21
Contact holes 31 to 33 are formed in the
Al electrodes 34 to 36 as base electrodes and collector electrodes
To form.

[0028]

In the method for manufacturing a bipolar transistor according to the first aspect of the present invention, the side wall is formed on the semiconductor film which becomes the emitter extraction electrode, so that the emitter region is not damaged by the etching for forming the side wall. Therefore, LG can be used without increasing the number of processes.
It is possible to manufacture a bipolar transistor having an E structure and excellent characteristics.

In the method of manufacturing a bipolar transistor according to a second aspect of the present invention, the first impurity is ion-implanted from an oblique direction so that the side wall is not required to be formed, so that the emitter region is not damaged by the etching for forming the side wall. Since it is designed not to receive, it is possible to reduce the number of steps and manufacture a bipolar transistor having an LGE structure and excellent characteristics.

[Brief description of drawings]

FIG. 1 is an np manufactured according to a first embodiment of the present invention.
It is a sectional side view of an n bipolar transistor.

FIG. 2 is a side sectional view showing a first step of the first embodiment.

FIG. 3 is a side sectional view showing a step that follows FIG.

FIG. 4 is a side sectional view showing a step that follows FIG.

5 is a side sectional view showing a step that follows FIG.

6 is a side sectional view showing a step that follows FIG.

7 is a side sectional view showing a step that follows FIG.

8 is a side sectional view showing a step that follows FIG. 7. FIG.

FIG. 9 is an np manufactured according to a second embodiment of the present invention.
It is a sectional side view of an n bipolar transistor.

FIG. 10 is a side sectional view showing a first step of the second embodiment.

FIG. 11 is a side sectional view showing a step that follows FIG.

12 is a side sectional view showing a step that follows FIG. 11. FIG.

13 is a side sectional view showing a step that follows FIG.

[Explanation of symbols]

14 Si Substrate 21 SiO ₂ Film 22 Opening 24 Polycrystalline Si Film 25 SiO ₂ Film 27 Impurity Region 28 Impurity Region

Claims (2)

[Claims] 1. An emitter region from a first impurity region having a relatively low impurity concentration and a second impurity region having a relatively high impurity concentration surrounded by the first impurity region on the surface of a semiconductor substrate. A method of manufacturing a bipolar transistor comprising: a step of forming an opening of a pattern of the emitter region in an insulating film covering the semiconductor substrate; and the opening of the semiconductor film containing a first impurity in a relatively low concentration. A step of forming a side wall at a step portion of the semiconductor film corresponding to the opening, and a step of introducing a second impurity into the semiconductor film at a relatively high concentration using the side wall as a mask. And diffusing the first and second impurities from the semiconductor film into the semiconductor substrate through the opening to form the first and second impurities.
A method of manufacturing a bipolar transistor, the method including the step of forming an impurity region of. 2. An emitter region including a first impurity region having a relatively low impurity concentration and a second impurity region surrounded by the first impurity region on the surface of a semiconductor substrate and having a relatively high impurity concentration. A method of manufacturing a bipolar transistor comprising: a step of forming an opening of a pattern of the second impurity region in an insulating film that covers the semiconductor substrate; Ion-implanting the first impurity at a relatively low concentration to form the first impurity region, covering the opening with a semiconductor film containing a second impurity at a relatively high concentration, And a step of diffusing the second impurity from the semiconductor film to the semiconductor substrate through the opening to form the second impurity region.