JPH03224238A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To restrain the lowering of current amplification factor and cut-off frequency even in the case of a short emitter width and increase performance, by constituting a film for forming an emitter leading-out electrode as a two- layered structure, and forming an inner base and an emitter layer by ion implantation. CONSTITUTION:In an emitter forming process, a film for forming an emitter leading-out electrode is constituted as a two-layered structure. That is, a third polycrystalline silicon film 14 turning to a first emitter electrode leading-out electrode film is deposited, and arsenic is ion-implanted; a fourth polycrystalline silicon film 15 turning to a second emitter electrode leading-out film is deposited, and arsenic is ion-implanted. Then, by heat treatment, arsenic is diffused and ion-implanted boron is activated; thus preferable impurity distribution is obtained and a p-type inner base layer 16 and an n-type emitter layer 17 are formed. Thereby the impurity concentrations of the layer 16 and the layer 17 can be set the respective necessary values even when an emitter is small, so that the decrease of current amplification factor and cut-off frequency are restrained, and excellent performance independent of working precision can be obtained even when the emitter width is microminiaturized down to submicron order.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing bipolar transistors with fine emitter structures suitable for high performance bipolar integrated circuits.

(Prior Art) To increase the integration and speed of bipolar integrated circuits, it is necessary to miniaturize transistors in the horizontal and vertical directions. As one of the vertical miniaturization techniques, polycrystalline silicon emitter technology is widely used in which a polycrystalline silicon film is used as an emitter diffusion source and an emitter electrode. Furthermore, various self-alignment techniques for self-aligning the base and emitter have been considered for lateral miniaturization. These technologies have so far produced bipolar transistors with an emitter width on the order of submicrons and a new wave number of 10 GHz or more.

However, the conventional method for manufacturing bipolar transistors has the following problems. For example, when the emitter width becomes submicron, a decrease in current amplification factor and cutoff frequency is observed. This can be explained in detail in Figure 5(a).
This will be explained with reference to (c). In these figures, 2
1 is a wafer serving as an n-type collector layer, 22 is a p-type inner base layer, and 23 is a p+ pear-shaped outer base layer. 25 is a first electrode which serves as a diffusion source and base extraction electrode for the external base layer.
The polycrystalline silicon film 26 is a second polycrystalline silicon film which serves as an emitter layer diffusion source and an emitter extraction electrode, and these polycrystalline silicon films are separated by an oxide film 27. Here, the emitter layer 24 is formed by depositing a polycrystalline silicon film 26 and doping it with arsenic by ion implantation, instead of forming a diffusion layer directly on the exposed surface of the wafer as in the conventional case.
It is formed by a method of performing heat treatment to diffuse arsenic shallowly into the wafer surface. However, according to experiments conducted by the inventors, this method can reduce the emitter width to 0.8. Although a high current amplification factor and cutoff frequency can be obtained up to a certain level, when the emitter width becomes smaller than this, it has been found that these performances deteriorate significantly as shown by the broken lines in FIGS. 2 and 3. This is due to the following reasons.

When the opening for forming the emitter layer becomes small, for example, about 0.4, the emitter forms a narrow recess with respect to the film thickness ti of the second polycrystalline silicon film 26, as shown in FIG. 5(b). At the opening, the film thickness t2 is 1.5 to 2 times greater.

In this state, the second polycrystalline silicon film 26 is formed under the same conditions as when there is a sufficient emitter opening as shown in FIG. 5(a).
Even if ion implantation is performed and heat treatment is performed, the desired emitter diffusion depth cannot be obtained because the film is thick at the emitter opening. If the thickness of the pre-formed internal base layer 22 is the same as that in FIG. 5(a), the thickness as shown in FIG. 5(b)
In the case of , the effective base layer width increases as the emitter diffusion depth decreases, which causes a decrease in the current amplification factor and a decrease in the cutoff frequency. If the thickness of the second polycrystalline silicon film 26 is made thinner, as shown in FIG. 5(c), the film thickness within the narrow emitter opening will be almost constant as in the case of FIG. 5(a). It is possible to do so. However, even with this method, as shown in FIG. 5(C), the effective emitter opening width (a) relative to the emitter opening width (a) for diffusion is very small, so a desired emitter diffusion layer cannot be obtained. In other words, even if impurities are injected into the surface of the second polycrystalline silicon film 26 by ion implantation, the thick portion of the second polycrystalline silicon film 26 formed on the side wall of the opening does not function as an effective impurity diffusion source, and the original opening width a The smaller the ratio b/a of the effective opening width becomes, the smaller the effective aperture width ratio b/a becomes. Therefore, in the end, even in this case, a predetermined emitter diffusion depth cannot be obtained under the same ion implantation conditions and heat treatment conditions as when the opening width is large. in the end,
In both cases of FIGS. 5(b) and 5(c), it follows that conventional polycrystalline silicon emitter technology is unable to provide the required concentration of impurities in the emitter region.

The fact that the characteristics differ depending on the emitter width as described above is very inconvenient for bipolar integrated circuits that form multiple elements.For example, when the emitter width is O, S,
If an attempt is made to obtain the necessary emitter layer diffusion depth in an internal circuit portion made up of small elements, the emitter layer diffusion depth becomes too large for elements with a large emitter width, such as the I10 buffer region, resulting in a drop in breakdown voltage.

(Problems to be Solved by the Invention) As described above, the conventional manufacturing method of high-performance bipolar transistors has drawbacks such as performance deterioration when the emitter width is miniaturized to sub-microns. The problem was that he was unable to perform to his full potential.

An object of the present invention is to provide a method for manufacturing a bipolar transistor that solves these problems.

[Structure of the invention]

(Means for Solving the Problems) The present invention has been made in view of the above-mentioned circumstances, and the first invention is to provide a semiconductor wafer with a collector layer of a second conductivity type on an element formation region of a semiconductor wafer having a collector layer of a first conductivity type. A step of forming a base extraction electrode with a predetermined pattern doped with impurities, a step of forming an insulating film on the surface of the base extraction electrode, and a step of diffusing the impurity in the base extraction electrode into the semiconductor wafer to form a second conductivity type. forming an internal base layer of the second conductivity type in contact with the external base layer; and forming an internal base layer of the first conductivity type on the surface of the internal base layer and the insulating film around it. A step of forming a first emitter lead-out electrode film doped with impurities, a step of forming a second emitter lead-out electrode film on the first emitter lead-out electrode film, and a heat treatment are performed to form the first emitter lead-out electrode film. A first layer is formed on the surface of the internal base layer by diffusing impurities in the extraction electrode film.
The present invention provides a method for manufacturing a bipolar transistor, comprising the steps of: forming a conductive type emitter layer.

The second invention also includes a step of forming a base 9 exposed electrode film having a predetermined pattern doped with impurities of a second conductivity type on an element shadow region of a semiconductor wafer having a collector layer of a first conductivity type; forming an insulating film on the surface of the base extraction electrode; and diffusing impurities in the base extraction electrode into the semiconductor wafer to form an external base layer of a second conductivity type.

forming a first emitter extraction electrode film doped with a second conductivity type impurity and a first conductivity type impurity on the semiconductor wafer surface where the internal base layer is to be formed and the insulating film around the semiconductor wafer surface; and heat treatment. forming an internal base layer of a second conductivity type and an emitter layer of a first conductivity type on the semiconductor wafer by diffusing impurities in the first emitter extraction electrode; The present invention provides a method for manufacturing a bipolar transistor, comprising the steps of: forming a second emitter extraction electrode film;

(Function) The present invention can be said to be an improvement on polycrystalline silicon emitter technology. That is, the film forming the emitter extraction electrode has a two-layer structure, and the internal base and emitter layer are formed by ion-implanting impurities into the first emitter extraction electrode, which preferably has a thin film thickness.
For example, if the emitter aperture is 0.8. Even when the impurity concentration is as small as below, the impurity concentration of the internal base and emitter layers can be easily maintained at the required value. The second emitter extraction electrode film prevents the effect of reaction with the metal emitter electrode formed on the thin first emitter extraction electrode film only, and also prevents holes injected from the base into the emitter. It functions to prevent the current amplification factor from decreasing due to recombination in the metal emitter electrode region. As a result, a high-performance bipolar transistor with no reduction in current amplification factor or cut-off frequency can be obtained even with a short emitter width.

Furthermore, according to the present invention, in addition to improving the emitter formation process, complete self-alignment of the external base, internal base, and emitter is possible, achieving dimensional accuracy with extremely little variation and improving the performance of bipolar transistors. can be achieved.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1J are cross-sectional views showing the manufacturing process of a bipolar transistor according to an embodiment. As shown in FIG. 1(a), first, an n-type collector buried layer 2 is formed on a p-type Si substrate 1, and an n-type epitaxial layer 3, which will become a collector layer, is formed thereon. The n-type epitaxial layer 3 is
For example, by using a vapor phase growth method, the impurity concentration I
It is formed as an n-type layer.

Next, grooves are formed in the element isolation region of this wafer, and grooves are also formed in the isolation region between the base, emitter region, and collector/contact region, and selective oxidation is performed to form grooves with element isolation oxide. A film 4 and an oxide film 5 for isolation between electrodes are formed. Note that the collector contact region is not shown.

A silicon oxide film 6 having a thickness of approximately 200 layers is formed by thermal oxidation on the entire surface of the wafer from which the elements have been separated. Next, a silicon nitride film 7 was deposited as an oxidation-resistant insulating film at a film thickness of 1000 nm.
A CVD oxide film is further deposited as a first mask material film to a thickness of about 5,000 layers. This CVD oxide film is patterned by photolithography, and oxide film patterns 81 to 8.
(Figure 1(a)).

At this time, reactive ion etching is used for patterning, so that the thick oxide film 8 has substantially vertical walls.

Next, a first layer of polycrystalline silicon [9] is deposited as a first conductor film. The thickness of this first polycrystalline silicon film 9 is 3.
Approximately 500 people lost their skin. Next, a photoresist was applied as a second mask material film over the entire surface, and after flattening the surface,
02 By etching back in a plasma atmosphere,
The surface of first layer polycrystalline silicon film 9 on oxide film 8 is exposed. That is, as shown in FIG. 1(b), a state is formed in which the photoresist pattern 10 is embedded in the recessed portion of the first layer polycrystalline silicon film 9.

Next, RIE is performed using the photoresist pattern 10 as a mask.
The first polycrystalline silicon film 9 is etched by etching. Oxide film patterns 81-8. After the oxide film patterns 81 to 83 are exposed, together with the photoresist pattern 10, these oxide film patterns 81 to 83 are used as a mask. In this way, the photoresist 10
until the first polycrystalline silicon film 9 remains only under the first polycrystalline silicon film 9.
Etching of the layered polycrystalline silicon film 9 is continued. Furthermore, the exposed nitride film 7 is also removed by etching. Although directional anisotropic etching can be used for these etchings, it is preferable to use RIE in which no overhang is formed. After the nitride film 7 is etched to expose the oxide film 6, this oxide film is removed by etching using an NH, F solution to expose the wafer surface. In this way, the first opening A for forming the external base region is formed (FIG. 1(C)). Incidentally, oxide film etching to expose the wafer surface can also be performed by RIE. Since a sufficient etching selectivity can be achieved between the oxide film and the epitaxial layer, it is possible to prevent damage to the wafer.

Next, as shown in FIG. 1(d), the photoresist pattern 10 is removed. Subsequently, a second polycrystalline silicon film 11 is deposited by about 6,000 layers as a second conductor film, and then this polycrystalline silicon film 11 is etched back. As a result, as shown in FIG. 1(e), the opening A of the second polycrystalline silicon film 11 is filled with the surface of the oxide film 8 exposed. Moreover, these first and second polycrystalline silicon films 9,
The surface of 11 should be flat. The thickness of the second layer polycrystalline silicon film 11 should be at least half the width of the first opening A.6 However, in order to obtain practical flatness,
The film thickness should be 1.5 times the width of the opening A.

Next, ion implantation is performed in the state shown in FIG. 1(e).

Second polycrystalline silicon film 11 is doped with boron.

Not only the second polycrystalline silicon film 11 but also the first polycrystalline silicon film 9 may be doped with boron at the same time. Boron ion implantation conditions are, for example, an acceleration voltage of 50 keV,
The dose amount is I XIO”/aJ.

Next, as shown in FIG. 1(f), by selectively removing the CVD oxide film 81 in the emitter formation region by photolithography, a second opening B for forming an internal base region is formed.
form. Next, by performing thermal oxidation using the exposed nitride film 7 as a mask, the first
Then, an oxide film 13 is formed on the surfaces of the second polycrystalline silicon films 9 and 11.

Thermal oxidation conditions are wet oxidation at 800 to 900°C,
1000~30 on the surface and sides of the polycrystalline silicon film
An oxide film 13 of 0.00 people is formed. As a result, the second polycrystalline silicon! The contact width between 11111 and the wafer is 2,000 to 3,000 people. Through this thermal oxidation step, boron in the polycrystalline silicon [11] is diffused into the wafer, forming a p-type external base layer 12. At this time, if necessary, in addition to the thermal oxidation process, heat treatment is performed in an inert gas atmosphere such as N2 gas to control the diffusion depth and concentration of the p-type external base layer 12.

Thereafter, the nitride film 7 within the second opening B is removed by plasma etching, and the oxide film 6 underneath it is further removed using an NH, F solution, thereby exposing the wafer surface of the second opening B. On the wafer surface exposed through the second opening B, a thin oxide film of about 250 layers is again formed by thermal oxidation. Then, the acceleration voltage is 15 keV, the dose is 5
Boron ions are implanted under the condition of X 1013/d.

Subsequently, the oxide film in the second opening B is removed to expose the wafer surface of the emitter region, and an emitter diffusion source/emitter extraction electrode film is formed in two steps. First, as shown in FIG. 1(h), a third polycrystalline silicon film 14 of about 200 layers is deposited, which will become the first emitter 9 lead electrode film (fourth conductor film), and arsenic ion implantation. The ion implantation conditions were an acceleration voltage of 10 to 30 keV, and a dose of IX.
10"/aJ to I x 10"#d. The accelerating voltage is adjusted so that the position where the concentration of arsenic implanted at this time is maximum is within the third polycrystalline silicon film 14 or near the interface between this and the wafer. Subsequently, a fourth polycrystalline silicon film 15 having a thickness of about 2,000 layers is deposited to become the second emitter electrode lead III (fourth conductor film). This fourth polycrystalline silicon film 15 is also coated with arsenic at an acceleration voltage of 60 ksV and a dose of 1 xlO14/a.
d ~I Deposition may also be performed.

Next, heat treatment was performed at 850°C to 1000°C to obtain the result shown in Figure 1 (
As shown in i), by diffusing arsenic and activating the previously ion-implanted boron and obtaining a preferable impurity distribution, the p-type internal base layer 16 and the n-type emitter layer 17 are formed.
form. At this time, heat treatment.

Short-time annealing for several seconds using halogen lamp irradiation, etc.
Preferably, rapid thermal annealing is performed. Emitter electrodes are made of third and fourth polycrystalline silicon films 1
4 and 15, but the arsenic ion-implanted into the third polycrystalline silicon film 14 mainly forms the emitter layer 1.
The arsenic becomes a diffusion source for forming the emitter electrode 7 and is ion-implanted into the fourth polycrystalline silicon film 15, and the arsenic is mainly used to lower the resistance of the emitter electrode.

After this, as shown in FIG. 1(j), the emitter extraction electrode is patterned, a hole for the base contact is made on the first and second polycrystalline silicon films 9 and 11, and a hole is formed between the emitter and the base. AQ of electrodes 18.19 and collector
The process is completed by forming electrodes (not shown).

According to this embodiment, the thickness of the third polycrystalline silicon film 14 is set to be thin so as to ensure a sufficient arsenic concentration to form an emitter. Furthermore, since the arsenic ions do not directly strike the silicon surface exposed within the second opening B, an emitter layer free from crystal defects due to ion implantation can be formed. Since the concentration of arsenic contained in the third polycrystalline silicon film 11114 is high, the adverse effects of the natural oxide film present at the interface between the third polycrystalline silicon film 14 and the substrate are also suppressed. The fourth polycrystalline silicon film 15 prevents a reaction between the third polycrystalline silicon film 14 and the AQ electrode, and also prevents holes injected from the base to the emitter from recombining in the Aft electrode region. As such, the film thickness is set to be large, and the arsenic in the fourth polycrystalline silicon film does not directly affect the formation of the emitter layer. Therefore, when forming the emitter layer, the impurity diffusion depth and concentration of the emitter layer can be made constant regardless of the size of the opening, and even an extremely shallow and minute emitter layer can be formed with good controllability.

Further, as a modification of this embodiment, it is possible to form a base and emitter diffusion source electrode film and an emitter extraction electrode film in two steps on the exposed wafer surface of the emitter region. That is, as shown in FIG. 1(h), about 200 layers of third polycrystalline silicon 14, which will become the electrode films (fourth conductor films) of the base and emitter diffusion sources, are deposited, and then boron and Arsenic ions are implanted respectively. The ion implantation conditions are an acceleration voltage of 10 to 30 kaV, and a dose of I x 1.
0"/3 to I x 10"/a11. At this time, the position where the concentration of the implanted boron and arsenic is maximum is located within this third polycrystalline silicon film 14 or near the interface between the third polycrystalline silicon film 14 and the wafer. Adjust the acceleration voltage so that the Alternatively, the concentration of boron and arsenic is maximized near the interface between the third polycrystalline silicon film 14 and the wafer.

At this time, the position where the arsenic concentration is maximum is generally located shallower than the position where the boron concentration is maximum, but by adjusting the temperature and time of the subsequent diffusion heat treatment, the arsenic concentration can be reduced. The position where the concentration of boron is maximum can also be located deeper than the position where the concentration of boron is maximum. Also,
It is also effective to locate the position where the boron concentration is maximum deeper than the interface between the third polycrystalline silicon film 14 and the wafer. Further, a third polycrystalline silicon film 14 is formed.
After depositing a fourth polycrystalline silicon film 15 of about 2,000 layers on top, arsenic is again applied at an accelerating voltage of 60 keV.
, dose amount I x 10"/3 ~ I x 10"/cn
Ion implantation is performed under the following conditions. The introduction of impurities into the fourth polycrystalline silicon film 15 does not necessarily need to be performed by ion implantation, and the film may be deposited, for example, in a gas atmosphere containing impurities.

Next, heat treatment is performed at about 850 to 1000°C to activate the previously implanted boron and arsenic and obtain a preferable impurity distribution to form the p-type internal base region 16 and the n-type internal base region 16. An emitter region 17 is formed. At this time, in order to prevent defects due to redistribution of impurities forming the p-type internal base region 16 and the n-type emitter region 17, short-time annealing (rapid thermal annealing) for several seconds by halogen lamp irradiation, etc. is performed at 850°C.
It is preferable to carry out the reaction at a temperature of about 1000°C. The emitter electrode is composed of third and fourth polycrystalline silicon films 14 and 15, and the boron and arsenic ions implanted into the third polycrystalline silicon film 14 are used in the p-type internal base region 16, respectively.
Arsenic, which serves as an impurity source for forming the n-type emitter region 17 and is ion-implanted into the fourth polycrystalline silicon film, is mainly used to lower the resistance of the polycrystalline silicon of the emitter electrode.

Thereafter, as shown in FIG. 1(j), the emitter extraction electrode is patterned to form the first and second polycrystalline silicon films 9.
, 11 for a base contact, and the emitter, base l electrodes 18 and 19, and collector AQ electrodes (not shown) are formed to complete the process.

According to this embodiment, the thickness of the third polycrystalline silicon film 14 is set to be thin so that sufficient impurity concentration to form an internal base and emitter can be ensured by ion implantation. Further, since the boron and arsenic ions do not directly strike the wafer surface exposed within the second opening B, an internal base and emitter layer without crystal defects due to ion implantation can be formed. Furthermore, a third polycrystalline silicon film 1
Since 4 is set thin, the ion-implanted boron and arsenic can suppress the adverse effects of the natural oxide film present at the interface between the third polycrystalline silicon film 14 and the wafer. In addition, the thickness of the fourth polycrystalline silicon film 15 is set such that the reaction between the third polycrystalline silicon film 14 and the AQ electrode is prevented, and the holes injected from the base to the emitter are
The film thickness is set to be thick to prevent recombination in the i-electrode region, and arsenic in the fourth polycrystalline silicon film 15 does not directly affect the formation of the emitter layer. Therefore, when forming the internal base and emitter regions, since the third polycrystalline silicon film 14 acts as a diffusion source, the impurity diffusion depth and concentration of the internal base and emitter regions can be approximately controlled regardless of the size of the opening. It is possible to form an internal base layer and an emitter layer of extremely shallow and minute dimensions with good controllability.

Further, in the above embodiment, the fourth polycrystalline silicon film 15 was deposited on the third polycrystalline silicon film 14 into which boron and arsenic were ion-implanted, and then heat treatment was performed to form the internal base and emitter layers. As another embodiment, heat treatment may be performed to form the internal base and emitter layers before depositing the fourth polycrystalline silicon film 15. As another example, when forming the internal base and emitter layer, the third polycrystalline silicon film 14 is ion-implanted with boron or arsenic and then subjected to heat treatment to form the internal base or emitter layer. , if the internal base layer is formed first, arsenic ions are implanted,
If the emitter layer is formed first, boron ions are implanted and heat treated.

It is also possible to form an emitter layer and an internal base layer, respectively.

The solid lines in FIGS. 2 and 3 represent the relationship between the emitter opening width, current amplification factor, and cutoff frequency of the bipolar transistor according to this embodiment. As is clear from Figure 0, which is the result, according to this embodiment, the emitter aperture width is 0.
．． Excellent device characteristics with no decrease in current amplification factor or cutoff frequency can be obtained up to 8- or less. In this way, since a transistor with stable characteristics can be obtained regardless of the size of the emitter aperture, especially when multiple transistors with different emitter widths are integrated into a bipolar integrated circuit,
This makes it possible to exhibit stable performance.

Further, according to this embodiment, an external base layer is formed around the CVD oxide film 81 patterned on the emitter region of the device, and this CVD oxide film 8i
An internal base layer and an emitter layer are sequentially formed in the region.

In other words, these element diffusion layers are completely self-aligned. In this respect, stable characteristics unprecedented in the prior art can be obtained. In particular, since the first opening for forming the external base layer is formed with a width equivalent to the thickness of the first layer polycrystalline silicon film 9, it has excellent controllability. The width of the external base layer can be easily changed by changing the thickness of the film.

In the above embodiment, boron ions are implanted into the second polycrystalline silicon film 11.
1 was used as a diffusion source to form an external base layer 12. However, it is not always necessary to use such an in-phase diffusion source. For example, by directly implanting boron ions into the wafer in the state shown in FIG. 1(c), the external base layer can be formed in the heat treatment process for forming the oxide film 11. This allows the impurity concentration to be higher and is preferable for lowering the resistance of the external base layer.

In the above embodiment, the internal base region is formed using a nitride film 7.
Then, the oxide film 6 is removed by etching, and a thin thermal oxide film is formed again.

However, it may be formed by ion implantation at the stage where the nitride film 7 or the oxide film 6 is removed.

The present invention is applicable to SSTs other than the self-alignment techniques described in the embodiments.
It can also be applied to self-alignment techniques represented by . Furthermore, in order to control the distance between the external base region and the emitter region, there is a method of arranging a spacer made of another polycrystalline silicon film, and the present invention can also be applied to this method.

In the above embodiment, there is a step of thermally oxidizing the surface of the polycrystalline silicon film that will become the base lead electrode. This thermal oxidation reduces the film thickness of the base lead-out electrode, lowers the impurity concentration, and increases the resistance value of the base electrode. Furthermore, if a thick oxide film is formed on the surface of the polycrystalline silicon film that will serve as the base lead-out electrode, the external base layer formed by diffusion from the polycrystalline silicon film will deviate from the optimum conditions, adversely affecting the high frequency characteristics of the element. Next, an embodiment will be described in which such an increase in the resistance of the base electrode and its influence on high frequency characteristics are prevented.

FIGS. 4(a) to 4(g) show the manufacturing process of this example.

As in the previous embodiment, first, as shown in FIG. 4(a),
forming an n-type collector buried layer 2 on a p-type Si substrate 1;
On top of this, impurity concentration 1×10”/cI becomes the collector layer.
An n-type epitaxial layer 3 of f is formed.

Next, trenches are formed in the element isolation region of this wafer, and trenches are also formed in the isolation region between the base, emitter region, and collector/contact region, and selective oxidation is performed to form an isolation oxide film in this trench. form 5. On the entire surface of the device-separated wafer, a silicon oxide film 6 with a thickness of about 200 layers is deposited by thermal oxidation, followed by a silicon nitride film 7 with a thickness of about 1000 layers as an oxidation-resistant insulating film, and then as a first mask material film. A CVD oxide film is deposited to a thickness of approximately 5,000 layers.

This CVD oxide film is patterned by photolithography,
Oxide film patterns 8□-83 are left on the planned internal base region and the element isolation region.

Next, a first layer polycrystalline silicon film 9 is deposited as a first conductor film. The thickness of this first polycrystalline silicon film 9 is 3.
500 people, rice yield is 8. Subsequently, a photoresist is applied to the entire surface as a second mask material film, and after flattening the surface,
0□By etch-packing in a plasma atmosphere,
The surface of first layer polycrystalline silicon film 9 on oxide film 8 is exposed. That is, as shown in FIG. 4(b), a state is formed in which the photoresist pattern 10 is embedded in the recessed portion of the first layer polycrystalline silicon film 9.

Next, RIE is performed using the photoresist pattern 10 as a mask.
The first polycrystalline silicon film 9 is etched by etching. Oxide film patterns 81-8. After the oxide film patterns 81 to 8. are exposed, the photoresist pattern 10 and the oxide film patterns 81 to 8. is also used as a mask. thus.

Etching of the first polycrystalline silicon film 9 is continued until the first polycrystalline silicon film 9 remains only under the photoresist 10. Furthermore, the exposed nitride film 7 is also removed by etching. Although directional anisotropic etching can be used for these etchings, it is preferable to use RIE in which no overhang is formed. When the nitride film 7 is etched and the oxide film 6 is exposed, this oxide film is
) The wafer surface is exposed by etching using a 14F solution. In this way, the first opening A for forming the external base region is formed (FIG. 4(C)), and the steps up to this point are the same as in the previous embodiment.

Thereafter, as shown in FIG. 4(d), a silicon oxide film 31 is deposited by about 3000 people by CVD, and then a silicon nitride film 32 is deposited by about 1500 people by CVD. Next, a photoresist is patterned on the emitter formation region, and the nitride film 32, oxide film 32, and oxide film 31 are etched using the reactive ion etching method. At this time, the area of the oxide film 8□ on the emitter formation region is provided with a margin for mask alignment, and about 3,000 portions outside the region of the oxide film 81 are removed. Then, about 2000 silicon nitride films 33 are deposited on the entire surface and reactive ion etching is performed to form a nitride film only on the side walls of the patterned oxide film 31 and nitride film 32, as shown in FIG. 4 (8). Leaving 33. Thereafter, the oxide film 8□ on the emitter formation region is removed by etching using a buffered hydrofluoric acid solution to open an opening B for forming an internal base. And nitride film 7, 32°3
3 as a mask, an oxide film 34 of approximately 1000 layers is formed on the end face of the second polycrystalline silicon film 11 exposed in the opening B, as shown in FIG. 4(f).

During this thermal oxidation process, the second polycrystalline silicon film 11 is
boron is diffused to form a p-type external base layer 12.

Thereafter, the nitride film 7 exposed in the opening B is removed by etching. At this time, the nitride film 32 on the base extraction electrode region is also removed. If isotropic etching is used at this time, the nitride film 33 on the upper side wall of the opening B will be removed and the second polycrystalline silicon film 11 will be exposed.

In order to prevent this, it is necessary, for example, to make the oxide film 31 sufficiently thick so that the nitride film 33 in this portion becomes sufficiently thick. In this embodiment, reactive ion etching was used for etching the nitride film.

Next, as shown in FIG. 4(g), the oxide film 6 of the opening B is
After removing by etching with a buffered hydrofluoric acid solution, boron ions are implanted to form a p-type internal base layer 16. Furthermore, a third polycrystalline silicon film 35 is deposited, arsenic ions are implanted into this film, and heat treatment is performed to diffuse the arsenic into the wafer to form an n-type emitter layer 17. At this time, as in the previous embodiment, it is desirable to perform the film formation of the third polycrystalline silicon film 35 and the ion implantation in two stages.After that, the AQ electrodes are arranged in the same way as on the actual flow side. and complete it.

According to this embodiment, it is possible to prevent the surface of the base extraction electrode from being oxidized, thereby preventing the base extraction electrode from increasing in resistance.

〔Effect of the invention〕

As described above, according to the present invention, 0.8. When manufacturing bipolar transistors with fine emitters such as those shown below, by improving the emitter formation process, we can suppress the decline in the current amplification factor hFE and the switching frequency, and obtain excellent performance that is independent of variations in processing accuracy. be able to. In particular, if the present invention is applied to a bipolar integrated circuit, transistors having different emitter widths, such as an internal circuit and an I10 buffer, can be formed with stable performance, and a highly reliable integrated circuit can be obtained.

Further, according to the present invention, the external base, internal base, and emitter can be formed with complete self-alignment, and a high-performance bipolar transistor with a fine structure can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to (j) are cross-sectional views showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention, and FIGS. 2 and 3 are views showing the characteristics of the bipolar transistor in comparison with a conventional example. , FIGS. 4(a) to 4(g) are cross-sectional views showing the manufacturing process of a bipolar transistor of another embodiment, and FIGS. 5(a) to (c) are diagrams for explaining the problems of the prior art. . 1... P type Si substrate 2... N medium collector buried layer 3... N type epitaxial layer (collector layer) 4.5... Isolation oxide film 6... Oxide film 7.
...Nitride film 8...CVD oxide film (first mask material film) 9...
First layer polycrystalline silicon film (first conductor film) 10... Photoresist (second mask material film) 11... Second layer polycrystalline silicon film (second conductor film) 12... P-type external base region 13... Thermal oxide film 14... Third polycrystalline silicon film (third conductor film, first emitter extraction electrode film) 15... Third polycrystalline silicon film ( 16...p-type internal base layer 31...silicon oxide film 33...silicon nitride film 35...third polycrystalline silicon film A. ...First opening 17...N-type emitter layer 32...Silicon nitride film 34...Thermal oxide film B...Second opening

Claims (2)

[Claims] (1) A step of forming a base extraction electrode with a predetermined pattern doped with impurities of a second conductivity type on the element formation region of a semiconductor wafer having a collector layer of the first conductivity type, and an insulating film on the surface of the base extraction electrode. forming an external base layer of a second conductivity type by diffusing impurities in the base extraction electrode into the semiconductor wafer; and forming an internal base layer of a second conductivity type in contact with the external base layer. forming a first emitter extraction electrode film doped with a first conductivity type impurity on the surface of this internal base layer and the insulating film around it; forming a second emitter extraction electrode film on the film; and performing heat treatment to diffuse impurities in the first emitter extraction electrode film to form an emitter layer of a first conductivity type on the surface of the internal base layer. A method for manufacturing a bipolar transistor, comprising the steps of: (2) A step of forming a base lead-out electrode in a predetermined pattern doped with a second conductivity type impurity on the element formation region of a semiconductor wafer having a collector layer of the first conductivity type; and an insulating film on the surface of the base lead-out electrode. forming an external base layer of a second conductivity type by diffusing impurities in the base extraction electrode into the semiconductor wafer; forming a first emitter extraction electrode film doped with a second conductivity type impurity and a first conductivity type impurity on the insulating film; and performing heat treatment to diffuse the impurities of the first emitter extraction electrode. forming an internal base layer of a second conductivity type and an emitter layer of a first conductivity type on a semiconductor wafer; and forming a second emitter extraction electrode film on the first emitter extraction electrode film. A method for manufacturing a bipolar transistor characterized by the following.