JPH04277631A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To facilitate manufacture and to improve high frequency characteristics with an external base region close to an emitter region without the need of a high-degree self-alignment positioning by forming a base insular region in an epitaxial region and an emitter region in its center. CONSTITUTION:This semiconductor device is provided with a conductivity-I base insular region formed in a conductivity-II epitaxial region 3 and having a high impurity concentration in the periphery 11, a conductivity-II high-doped emitter region formed in the center of the insular region, and a conductivity-II high-doped collector region 16. Further provided are an insulating film 5 windowed over the above-mentioned base, emitter, and collector regions, polysilicon 6 spread over the periphery 11 of the base insular region, an insulating film 12 spread over polysilicon side face on the emitter region side, an insulating nitride film 7 spread over the polysilicon 6, and a second polysilicon 15 spread over the insulating film 7 including the top of the emitter region 14 over the collector region 16.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in semiconductor devices and methods of manufacturing the same.

0002

[Prior Art] In order to achieve higher frequencies in ICs, it is necessary to make the component transistors smaller and shallower, and in order to improve the alignment accuracy of emitters, bases, etc., various self-alignment ( self-alignment) has been proposed. There are also some self-aligns,
As an example, the PSA (pol
y-Si Self-Aligned Process
5 and 6 show the cross-sectional structure of the product during manufacturing and after completion.

In FIG. 5, each region is formed on the base region, emitter region, and collector region by ion implantation through a polysilicon film, and the separation of the base, emitter, and collector polysilicon films is , isolation is performed by oxidizing a silicon nitride film as a mask. This example is characterized in that contacts and electrodes in each region can be formed in a self-aligned manner, and the positional relationship between the external base region and the emitter region is determined by a silicon nitride film mask.

[0004] Another example is SST (Super Self-Alig) announced by Nippon Telegraph and Telephone Corporation.
ned Processes Technology). FIGS. 7 and 8 show cross-sectional structures during and after manufacturing. This method has been proposed as a manufacturing method for ultra-high frequency transistors, and is characterized by the fact that the width of the emitter can be extremely miniaturized by using the first and second polysilicon films. In its manufacture, after forming an external base through a first polysilicon film, the surface is oxidized, only the emitter region is removed, and a second polysilicon film is formed. After this, an emitter region is formed via the second polysilicon film, and although the process is quite complicated, it is characterized by the ability to form fine transistors.

[0005]

[Problems to be Solved by the Invention] In the PSA method shown in FIGS. 5 and 6, the relative positional relationship between the external base region and the emitter region does not change depending on the alignment position of the silicon nitride film;
The area of each region may change. For example, if it shifts to the right, the emitter area will become smaller. Furthermore, in order to achieve higher frequencies, it is necessary to minimize the base resistance, but the distance between the external base and the emitter region is determined by the mask dimensions of the silicon nitride film and the amount of horizontal expansion caused by oxidation. An expensive high-precision aligner (step projection exposure device) such as a stepper is required, and an inexpensive proximity type exposure device has the disadvantage that the pattern becomes large. On the other hand, in the SST method shown in FIGS. 7 and 8, the process is very complicated, and several steps are required to form the sidewalls of the first silicon film for forming the external base region, resulting in low yield and manufacturing costs. However, there is a problem in that it is difficult to adopt it inside an IC.

[0006]

OBJECTS OF THE INVENTION The present invention can be used as a component for increasing the frequency of an IC. An object of the present invention is to provide a semiconductor device whose characteristics can be improved and a method for manufacturing the same.

[0007]

[Means for Solving the Problems] A semiconductor device according to the present invention includes an epitaxial region of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and an epitaxial region of a second conductivity type formed in the epitaxial region and having a high impurity concentration in a surrounding portion. a base island-like region of one conductivity type; a high-concentration impurity emitter region of a second conductivity type formed in the center of the base island-like region; and a second conductivity type formed on the side of the base island-like region in the epitaxial region. a high concentration impurity collector region formed on the substrate;
a first insulating film having windows formed on at least the base, emitter, and collector regions; a first polysilicon formed on a peripheral portion of the base island region; and an emitter region of the first polysilicon. an insulating film formed on the side surface, a nitride insulating film formed on the first polysilicon, and a second polysilicon film formed on the nitride insulating film including on the emitter region and on the collector region. The gist is that it includes silicon.

The method for manufacturing a semiconductor device according to the present invention also includes a step of forming a second conductivity type epitaxial layer on a first conductivity type silicon substrate and forming an insulating film on the surface, and a first step of forming a base and an emitter. A window is opened in the insulating film of the part and the second part forming the collector, a first polysilicon is deposited on the entire surface, and silicon nitride is deposited thereon, and a second part forming the emitter of the first part is formed. removing the first polysilicon and silicon nitride around the portion including the portion No. 3 and the second portion, and covering a predetermined position of the first portion and the second portion with a resist;
A process of implanting boron into the first polysilicon and diffusing impurities into the substrate, covering the first part except the third part with a resist, implanting boron, and then activating the polysilicon after removing the resist. activating and spreading the base, anisotropically removing the oxide film on the third portion and on the second portion, and removing the oxide film on the first portion and the second portion. The gist of the method is to include the steps of forming a second polysilicon layer above, implanting phosphorus into the entire surface, and then diffusing it into the substrate.

[0009]

[Operation] In the semiconductor device having the above structure, the external base region and the emitter region can be uniquely determined by self-alignment. The polysilicon on the base and emitter can be used as an extraction electrode, and there is no need to miniaturize the metal electrode. Furthermore, leaving the nitride insulating film on the base has a passivation (protection) effect on the base.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view of a semiconductor device showing one embodiment of the present invention, and FIGS. 2, 3 and 4 are manufacturing process diagrams thereof. In the figure, 1 is a P-type substrate, 2 is a heavily doped N-type buried region, 3 is an N-type epitaxial layer, 4 is a heavily doped P-type isolation region, 5 is an oxide film, and 6 is a first polysilicon (polycrystalline silicon). silicon), 7 is a silicon nitride film (Si3
N4), 8 is the photoresist, 9 is the emitter region, 10 is the collector extraction location, 11 is the external base region, 12 is the oxide film formed after the external base diffusion, 13 is the active base region, and 14 is the Emitter region, 15
is the second polysilicon, 16 is the collector extraction high concentration N type diffusion region, 17 is the oxide film on the second polysilicon,
18 is a metal (Al) electrode.

The manufacturing process shown in FIGS. 2 to 4 will be explained below. A heavily doped N-type buried region is formed in a P-type silicon substrate 1 serving as an IC substrate, and after growing an N-type epitaxial layer in step 3, an oxide film 5 is formed to form element isolation regions 4 in each IC. Although the isolation region 4 is a general diffusion, it is not limited to this, and may be, for example, bidirectional diffusion isolation from the silicon epitaxial layer surface and from the substrate.
Insulating film separation or trench separation may also be used.

After forming the IC substrate in the above steps, windows are opened in the oxide film 5 at the positions that will become the base, emitter, and collector regions of the transistor, and then the first polysilicon 6 and silicon nitride 7 are sequentially coated on the entire surface. Then, the portion 9 that will become the emitter region, the portion 10 that will become the collector region, and further regions that are unnecessary for the device configuration within the IC are removed. This removal means may be wet etching or dry etching using a resist mask. Further, the first polysilicon may be etched by just etching or roof etching (because it will be removed by oxidation in the next step). In this case, for example, the first polysilicon film thickness is 5000 Å, and the silicon nitride film thickness is 2000 Å.
It is Å. Further, the oxide film 5 has a thickness of 2000 Å or more to block boron during element isolation.

Next, in order to form the external base region 11, the portion 9 which will become the emitter region and the portion 10 which will become the collector region are covered with resist. At this time, since the diffusion of boron in the first polysilicon 6 is extremely fast, the mask alignment may be rough, as long as it covers the areas 9 and 10 where the substrate is visible in FIG. , the pattern is made such that it overlaps the silicon nitride 7. In this state, boron for forming an external base is implanted into the first polysilicon by ion implantation. for example,
Dose amount 1×1515/cm2 at acceleration voltage 120KeV
It is. FIG. 2 shows the manufacturing process up to this point.

Thereafter, the resist is removed by a conventional method, and the first polysilicon 6 is diffused into the silicon substrate in an oxidizing atmosphere. For example, heat treatment temperature 105
When carried out for 120 minutes at 0°C, the surface concentration is approximately 1 x 1019/
cm3, and the depth is around 1.1 μm. At this time, the surface of the first polysilicon is covered with a silicon nitride film, but since the polysilicon is exposed on the sidewall that will become the emitter region, it is oxidized and an oxide film 1 with a thickness of about 1000 Å to 2000 Å is formed.
2 are also formed in the lateral direction. Next, in order to form the active base region 13, areas other than the base region are covered with resist, and boron ions are similarly implanted. For example, acceleration voltage 60Ke
V and the dose amount is 5×10 13 /cm 2 . FIG. 3 shows the manufacturing process up to this point.

Next, the resist is removed, and ions in the active base region 13 are activated and diffused. For example, heat the oxide film 12 at 900 to 1000°C for 30 minutes at a location 9 that will become the emitter region and a location 10 that will become the collector region.
, 12' are removed by dry etching. Since the etching is dry, there is anisotropy, and the oxide film 12 on the sidewall of the first polysilicon remains unetched. Thereafter, second polysilicon 15 is deposited, the emitter region and collector region are patterned, and phosphorus ions are implanted into the entire surface and diffused into the silicon substrate by a prescribed heat treatment to form a transistor. The polysilicon film thickness at this time is, for example, 4000 Å, the phosphorus acceleration voltage is 80 KeV, and the dose is 5 x 1015/cm2.
It is. Further, the heat treatment temperature is 1000° C. for about 40 minutes in an oxidizing and inert atmosphere. FIG. 4 shows the manufacturing process up to this point.

[0016] After this, in order to take out the electrodes in each area,
A window is opened on each polysilicon lead electrode, a metal electrode is provided, and the transistor is completed. Figure 1 is a diagram of its completion. However, in Figure 1, passivation (
protection) is not shown. Also, if there is a need for two-layer wiring etc. for the IC, additional processes will be added after this.
Only the manufacturing method of the transistor structure is shown here.

[0017]

[Effects of the Invention] According to the present invention, in particular, the following effects can be obtained. (1) The external base and emitter regions can be uniquely determined by self-alignment. (2) Self-alignment allows the external base region and emitter region to approach each other without requiring a high degree of alignment, thereby improving high frequency characteristics. (3) It is easy to manufacture and can be used as a component of an IC. (4) The polysilicon on the base and emitter can be used as an extraction electrode, and there is no need to miniaturize the metal electrode. (5) Leaving the silicon nitride film on the base has a passivation (protection) effect on the base, improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a semiconductor device in the middle of a manufacturing process.

FIG. 3 is a sectional view showing the next step.

FIG. 4 is a sectional view showing the next step.

FIG. 5 is a cross-sectional view showing the middle of a manufacturing process in a conventional semiconductor device manufacturing method PSA.

FIG. 6 is a cross-sectional view of the completed semiconductor device.

FIG. 7 is a cross-sectional view showing the middle of a manufacturing process in a conventional semiconductor device manufacturing method SST.

FIG. 8 is a cross-sectional view of the completed semiconductor device.

[Explanation of symbols]

1 P-type silicon substrate 2 High concentration N-type buried region 3 N-type epitaxial layer 4 Isolation region 5 Oxide film 6 First polysilicon 7 Silicon nitride film 8 Resist 9 Emitter region 10 Collector region 11 External base Region 12 Oxide film 13 formed after extrinsic base diffusion
Active base region 14 Emitter region 15 Second polysilicon 16 Collector extraction high concentration N-type diffusion region 17
Oxide film 18 on second polysilicon Metal electrode

Claims (2)

[Claims] 1. A second conductivity type epitaxial region formed in a first conductivity type semiconductor substrate, a first conductivity type base island region formed in the epitaxial region and having a high impurity concentration in a surrounding portion, and the base a second conductivity type high concentration impurity emitter region formed in the center of the island region; a second conductivity type high concentration impurity collector region formed on the sides of the base island region within the epitaxial region; a first insulating film having a window formed on at least the base, emitter, and collector regions; a first polysilicon formed on a peripheral portion of the base island region; and the first polysilicon. an insulating film formed on the side surface of the emitter region, a nitride insulating film formed on the first polysilicon, and a first insulating film formed on the nitride insulating film including on the emitter region and on the collector region. 2. A semiconductor device comprising: 2 polysilicon. 2. A step of forming a second conductivity type epitaxial layer on a first conductivity type silicon substrate and forming an insulating film on the surface, and a step of forming a base, a first part forming an emitter, and a second part forming a collector. A window is opened in the insulating film of the portion, a first polysilicon is deposited on the entire surface, and silicon nitride is deposited thereon, and a third portion forming an emitter of the first portion and the second portion are formed. removing the first polysilicon and silicon nitride around the first polysilicon, covering a predetermined position of the first part and the second part with a resist, implanting boron into the first polysilicon, and removing the first polysilicon and silicon nitride from the substrate. a step of performing impurity diffusion into the first part, a step of covering the first part except the third part with a resist, implanting boron, and then performing activation and extension diffusion of the active base after removing the resist; a step of anisotropically removing an oxide film on the third portion and the second portion; and forming a second polysilicon layer over the first portion and the second portion; After injecting phosphorus,
A method for manufacturing a semiconductor, comprising the step of diffusing into the substrate.