JPS62194672A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To narrow a space between a base electrode and an emitter, to scale down the size of a transistor and to improve high-frequency operation and performance by forming a shallow base layer by an silicide layer and using the same silicide layer as a base leading-out electrode. CONSTITUTION:A first high melting-point metallic silicide 601, such as MoSi, TiSi, etc. is shaped extending over the upper section of a first oxide film 102 from the whole surface of a base region through photoetching, and a p-type impurity such as boron is implanted into the silicide as the base region by a photo-mask 301. The photo-mask 301 is removed, and B is diffused through heat treatment to form a base layer 61. A second oxide film 402 is deposited on the whole surface. The base layer is shallowed, and a section between base- emitter electrodes is shortened, thus scaling down the size of a transistor both in the vertical direction and the transverse direction, then improving high-frequency operation and performance.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a bipolar semiconductor integrated circuit bag. lt (hereinafter referred to as BIP・I
The present invention relates to a method for forming a transistor in the method (referred to as C).

[Conventional technology]

Generally, the transistor in BIP-IC is pnn
Junction separation Oxide film separation using 5-selective oxidation technology.

Alternatively, they are formed in electrically independent islands by a method using triple diffusion. Here, a method for forming an npn transistor using an oxide film separation method will be described.

Of course, when using the above-mentioned various separation methods other than this, it can also be applied to pnp transistors.

FIGS. 2(a) to 2(e) are cross-sectional views showing the state of the conventional manufacturing method at the stage of use. The conventional method will be briefly explained below with reference to this figure. p-type (p
After selectively forming a highly impurity-concentrated n-type (n+ type) WJ2 to serve as a collector buried layer on a silicon substrate l, an n-type epitaxial layer 3 is grown on top of them (see Fig. a)) Next, selective oxidation is performed using the nitride film 201 formed on the underlying oxide film 101 as a mask to form a thick isolation oxide film 102;
At the same time, a p-type layer 4 for channel cutting is formed under 02 (FIG. 2)). Next, the nitride film 201 used as a mask for the selective oxidation described above is removed together with the underlying oxide film 101, and the oxide film 103 for protecting ion implantation is replaced.
is formed, and using a photoresist film (the photoresist film at this stage is not shown) as a mask, the P4 type layer 5 that will become the external base layer is removed, and the photoresist film is removed, and a photoresist film 301 is formed again. is formed, and using this as a mask, a p-type layer 6 which will become an active base layer is formed by ion implantation (FIG. 2(C)). Subsequently, the photoresist film 301 is removed, a pansivation film 401 generally made of phosphosilicate glass (PSG) is deposited, and the base ion-implanted layer 5.6 is annealed and the PSG film is deposited.
After the film 401 is subjected to a heat treatment that also serves as a heat treatment to form an intermediate external base layer 51 and an active base layer 61, the required openings 70 and 80 are formed in the PSG film 401, and then the PSG film 401 is heated by ion implantation. An n-type layer 7 to serve as an emitter layer and an n-type layer 8 to serve as a collector electrode extraction layer are formed (FIG. 2(d)). After that, each ion implantation layer is annealed to complete the external base layer 52 and the active base layer 62, and the emitter layer 71 and the collector electrode extraction layer 8 are formed, and then an opening 50 for extracting the base electrode is formed. Metal silicide (platinum silicide (Pt-3t), palladium silicide (Pt-3t), palladium silicide (Pt-3t),
d-3i) etc.] After forming the film 501, base electrode wiring 9. is formed using a low resistance metal such as aluminum (A1). Emitter electrode wiring vA10 and collector electrode wiring 1
1 (Fig. 2(e)).

FIG. 3 is a plan pattern diagram of a transistor manufactured by this conventional method. By the way, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these to improve the frequency characteristics. In the above structure, the p-type external base layer 52 is provided to reduce the base resistance, but this has the disadvantage of increasing the base-collector capacitance. Also, to
The abrasive resist is the emitter layer 71 and the base electrode extraction hole 50.
In the conventional method, the distance between the base electrode wiring 9 and the emitter electrode wiring 10 and the arrangement of each electrode 4
This is the total distance of the protrusion from each of the openings 50 and 70 of FA9.10, and even if the precision of photoetching is improved and the electrode wiring spacing is reduced, the protrusion will inevitably remain.

[Problem that the invention seeks to solve]

Generally, in order to improve transistor performance, it is necessary to reduce the transistor size so as to reduce parasitic capacitance and parasitic resistance. Conventional transistor structures have been hindered from shrinking in size by the need for photoetching margins. In addition, the reduction in the vertical direction was zero because the base layer was formed by ion implantation through the oxide film.
．． It was not possible to make the depth shallower than about 3 μm, which was a limit for high frequency operation.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to obtain a transistor that can improve high frequency operation and performance.

[Means for solving problems]

In the semiconductor device according to the present invention, after forming the collector layer, a shallow base layer is formed by diffusing P-type impurities injected into high-melting point metal silicide, and this silicide layer is further used to lead out the base electrode. It is.

[Effect]

Conventionally, it has been widely practiced to form a shallow emitter layer by diffusing n-type impurities from polysilicon.
Since a transistor with a thin base width is formed, it is difficult to obtain a sufficient hFE. In this invention,
The base layer can be made shallow, and the distance between the emitter and base electrodes can be reduced using self-alignment, and the transistor can be reduced using the same level of lithography technology.
A transistor with all can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(1) are process diagrams showing one embodiment of the present invention, in which 1 is a P-type semiconductor silicon substrate, 2 is a P-type semiconductor silicon substrate;
3 is an n-type buried collector layer, 3 is an n-type epitaxial growth layer, 4 is a channel cut layer for isolation between elements, 9 is a collector lead metal wiring, 10 is an emitter lead metal wiring, 11 is a base lead metal wiring, 22 102 is a collector extraction layer, 102 is a thick oxide film, 301 is a base mask photoresist, 401 is a passivation film, 50 is a base contact opening, 61 is a base layer,
62 is the base diffusion layer after the base heat treatment, 70 is the opening of the emitter contact, 71 is the emitter diffusion layer, 80 is the opening of the collector contact, 81 is the n-type layer after the emitter heat treatment, 110 is the base and collector drawer Interlayer oxide film, 601 is the first high melting point metal silicide for the base extraction electrode, 402 is the second oxide film, 403 is the third oxide film left on the side wall, 75 is the emitter diffusion hole, and 85 is the collector opening. Hole 550 is polysilicon for emitter diffusion,
501 is a second silicide layer.

Next, the manufacturing method will be explained.

As shown in FIG. 1 (al), in the same manner as the process shown in FIG. 2 (a) of the conventional method, an n-type deep buried collector layer 2 is formed on a low concentration P-type silicon substrate 1, and a thin n-type epitaxial layer is formed. Forms N3. After etching the epitaxial growth layer only in the element isolation region in the same manner as in FIG. 102. A shallow and thick oxide film 110 is formed between the base region and the collector extraction layer region (
1st step). Next, after removing the nitride film and oxide film (not shown), an n-type impurity is introduced into the collector extraction layer region by ion implantation or diffusion using a photomask, and is diffused to form the collector extraction layer 22 (second process). Next, as shown in Figure 1 (bl), Mo5
First oxidation II! As shown in FIG. 1 (C1), a P-type impurity such as boron is implanted into the silicide corresponding to the base region using a photomask 301.
3rd step). This boron implantation may be performed before etching the first high melting point metal silicide 601 shown in FIG. 1(d).
After removing the photomaster 301, B is diffused by heat treatment to form the base layer 61 (third step). Thereafter, a second oxide film 402 is deposited over the entire surface (fourth step). Next, as shown in FIG. 1 (81), the second oxide film 402 and silicide film 601 in the emitter region (emitter diffusion hole) 75 and collector extraction region (collector opening) 85 are etched (fifth As shown in FIG. 1(f), by forming the third acid film on the entire surface and performing anisotropic etching, the third film is formed only on the side wall of the opening. An oxide film 403 is left (sixth step).After this, as shown in FIG. The emitter layer 71 and the n-type layer 81 to the collector are formed by diffusion (seventh step).At this time, the diffusion base layer 62 is also formed.Then, the polysilicon is formed by leaving a region 550 as an emitter lead-out. and remove it by photo etching (
8th step). Next, as shown in FIG. 1(h), a highly reactive metal is deposited on the entire surface and the emitter electrode lead portion and collector electrode portion are silicided by a silicide reaction (ninth step). After that, as shown in Figure 1 (1), passivation is performed on the entire surface with an oxide film, etc.
Contact holes 50, 70, 80 are opened by photoetching for the base on the silicide of the base electrode, for the emitter on the silicide for taking out the emitter electrode, and for the collector on the collector extraction layer.Finally, as shown in FIG.
), the transistor is completed by wiring metal such as Al (10th step).

In this way, in this example, the base layer is shallow and the distance between the base and emitter electrodes is reduced to about several thousand layers, so the transistor size can be reduced both vertically and horizontally, which improves high frequency operation and performance. Improved.

In the above example, when forming an emitter, an n-type impurity was diffused from polysilicon, and then a second silicide film was formed to form an emitter extraction layer. An emitter layer may be formed by diffusion, and then an emitter extraction layer may be formed only by photoetching, and in this case, the silicidation step can be omitted.

〔Effect of the invention〕

As described above, according to the present invention, a shallow base layer is formed using a silicide layer, and the same silicide layer is used as a base extraction electrode, so that the distance between the base electrode and the emitter is narrowed, and the transistor size can be increased vertically. It can be reduced in both lateral directions, thus improving high frequency operation and performance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view and a plan view of a transistor at each process step according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a transistor at each process step according to a conventional manufacturing method, and FIG. FIG. In the figure, numeral 1 is a P-type semiconductor silicon substrate, 2 is an n-type buried collector layer, 3 is an n-type epitaxial growth layer, and 4 is a p-type semiconductor silicon substrate.
is a Chanel cut layer for isolation between elements, 9 is a collector lead metal wiring, 10 is an emitter lead metal wiring,
Reference numeral 11 indicates metal wiring for base extraction, 22 indicates collector extension layer, 102 indicates thick oxide film, 401 indicates passivation film, 61 indicates base diffusion layer, 71 indicates emitter diffusion layer, 1
10 is an oxide film between the base and the collector extraction layer, 601
402 is the second oxide film, and 403 is the third metal silicide left on the side wall.
75 is an emitter diffusion hole, 550 is polysilicon for emitter diffusion, and 501 is a second silicide layer. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Ken Hayase - Amendment to Figure 1 Figure 2 Procedures (Voluntary) March 72, 1988

Claims (4)

[Claims] (1) In a bipolar semiconductor device, a buried collector layer, an epitaxial growth layer, and a collector extraction layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type, and a thick first oxide film for isolation between elements. , an oxide film thinner than the first oxide film between the base region and the collector extraction region; a first high melting point metal silicide layer formed from above the base region to the first oxide film; A base layer of a first conductivity type diffused from a melting point metal silicide layer, a second oxide film covering the metal silicide layer, and an emitter layer of a second conductivity type formed of polysilicon from an opening in an emitter region. a second silicide layer formed by siliciding the surface of the emitter extraction polysilicon and collector extraction layer; a base formed on the first and second silicide layers;
A semiconductor device characterized by comprising contact holes for collector and emitter wiring. (2) In a method for manufacturing a bipolar semiconductor device, after forming a buried collector layer and an epitaxial growth layer of a second conductivity type on a semiconductor substrate of a first conductivity type, a thick first oxide film is formed for isolation between elements. a first step of forming an oxide film thinner than the first oxide film between the base region and the collector lead-out region; a second step of forming a collector lead-out layer of a second conductivity type in the collector lead-out region; a third step of forming a base layer of a first conductivity type by forming a high melting point metal silicide layer of 1 and diffusing an impurity of a first conductivity type implanted into the layer; a fourth step of forming an oxide film, a fifth step of opening holes in the second oxide film in the portions that will become the emitter region and the collection extraction region, and further opening the silicide layer directly under the emitter region, the entire surface. After forming the third oxide film, the sixth step is to leave the third oxide film only on the side walls of the opening using anisotropic etching. a seventh step of forming an emitter layer by introducing and diffusing conductive type impurities; an eighth step of removing the polysilicon or high melting point metal silicide layer except for the emitter extraction region; The ninth step is to form a second silicide layer by depositing a strong metal and causing a silicidation reaction. After depositing a passivation film, contact holes are opened on the silicide for leading out each of the base, emitter, and collector. A method for manufacturing a semiconductor device, comprising a tenth step of forming holes and wiring. (3) The third step of forming the base layer includes depositing a first high melting point metal silicide layer on the entire surface, implanting conductive type impurities into the entire surface, and selectively removing the silicide layer. 2. The semiconductor device according to claim 2, further comprising the steps of: forming a base lead-out electrode portion from above the base region to above the oxide film; and then forming a base layer by diffusion. Production method. (4) The third step is a step of depositing and forming a high melting point metal silicide layer from above the base region to above the first oxide film, and introducing impurities of a first conductivity type into the metal silicide layer. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming a base layer of the first conductivity type by diffusion.