JPH0428246A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the breakdown strengths of junctions between the second conductivity type high-concentration impurity regions of a MOS transistor and low- concentration first conductivity type impurity regions by a method wherein the low- concentration first conductivity type impurity regions are respectively formed between the second conductivity type high-concentration impurity regions and the first conductivity type high-concentration channel stop region of the MOS transistor. CONSTITUTION:Arsenic ions 19 are ion-implanted in the surface of a silicon substrate 1 in the direction perpendicular to the substrate surface using a gate electrode 3 with a sidewall oxide film 17 formed thereon and a field oxide film 7 as masks and thereafter, an activation treatment is conducted. Thereby, high-concentration n<+> impurity regions 5a are formed and an LDD structure consisting of source and drain regions is completed. Low-concentration P<-> impurity regions 15 are respectively formed between a channel stop layer 8 and the regions 5a at the end parts of the film 7. When a reverse voltage is applied to junctions between these regions 15 and the regions 5a, the spread of depletion layers which are formed at the junction regions is increased, an electric field which is applied to the junction surfaces is relaxed and the breakdown strengths of the junctions can be improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a fine structure of an element isolation film formed on the surface of a semiconductor substrate, a structure capable of improving element isolation characteristics, and a method for manufacturing the same. It is.

[Prior Art] FIG. 6 is a cross-sectional structural diagram schematically showing a cross-sectional structure of a semiconductor device, for example, a semiconductor storage device such as a memory.

Referring to FIG. 6, there is a MOS on the surface of p-type silicon substrate 1.
) An element formation region L2 in which a transistor 2 is formed and an element/isolation region L1 in which a field oxide film 7 is formed are formed.

The MOS transistor 2 includes a gate electrode 3 formed on the surface of a p-type silicon substrate 1 with a gate insulating film 4 interposed therebetween. The upper surface and side surfaces of gate electrode 3 are covered with upper oxide film 18 and sidewall oxide film 17. Furthermore, a pair of source/drain regions 5a and 5b are formed on the surface of the silicon substrate 1.

The source/drain region is a so-called L D consisting of a high concentration n+ impurity region 5a and a low concentration n− impurity region 5b.
It has a D (Lightly Doped Drain) structure.

A thick field oxide film 7 is formed in the element isolation region. The field oxide film 7 is a so-called LOC
OS (Local Oxidation of' 5
iljcon) method. A channel stop layer 8 made of a p-type impurity region having a higher concentration than the substrate 1 is formed on the lower surface of the field oxide film 7 . The purpose of this channel stop layer 8 is to increase the substrate concentration in the region below the field oxide film 7, thereby preventing the formation of an inversion layer in this region and improving the element isolation ability.

FIG. 6 also shows an electrode layer 6 passing over the field oxide film 7, for example.

Next, a method for manufacturing the semiconductor device shown in FIG. 6 will be described with reference to FIGS. 7A to 7G.

First, referring to FIG. 7A, underlying oxide film 14, nitride film 9, and resist 10 are sequentially formed on the surface of p-type silicon substrate 1. Next, the resist 10 and the nitride film 9 are patterned using a lithography method and an etching method,
A predetermined opening is formed.

Next, referring to FIG. 7B, p-type impurity ions such as boron] 2 are implanted into the surface of the silicon substrate 1 using the patterned resist 10 and nitride film 9 as masks.

Further, referring to FIG. 7C, the silicon substrate 1 is subjected to steam oxidation to form a field oxide film 7 having a thickness of about several thousand amps. At this time, boron ions 12 are simultaneously diffused into the substrate to form a channel stop layer 8.

Furthermore, referring to FIG. 7D, nitride film 9 and underlying oxide film 14 are removed. Then, thermal oxidation treatment is performed to form a gate oxide film 4 on the surface of the silicon substrate 1 again to a thickness of several tens of tens of pounds.
form. Furthermore, CVD (chemi) is applied on the surface.
Several thousand polycrystalline silicon layers 3 are formed using the cal vapor deposition method, and an oxide film 18 is formed on the surface thereof.

Furthermore, referring to FIG. 7E, after applying resist 10 on the surface of oxide film 18, this is patterned, and further, using patterned resist 10 as a mask, oxide film 18 and polycrystalline silicon layer 3 are Pattern into a shape. As a result, the gate electrode 3 or the electrode layer 6
is formed.

Thereafter, referring to FIG. 7F, a first n-type impurity ion 19 is implanted into the silicon substrate 1 using the gate electrode 3 as a mask to form a low concentration n impurity region 5b.

Further, referring to FIG. 7G, after forming a sidewall oxide film 17 on the sidewall of the gate electrode 3, a second n-type impurity 2 is applied to the surface of the silicon substrate 1 using the sidewall oxide film 17 as a mask.
A high concentration n+ impurity region 5a is formed by implanting 0 ions. Through the above steps, the semiconductor device shown in FIG. 6 is manufactured.

[Problems to be Solved by the Invention] However, the conventional element isolation structure as described above has the following problems.

First, the field oxide film 7 formed by the conventional LOCO3 method has a problem in that regions called so-called bird's beaks are formed at both ends thereof. That is, in FIG. 6, when the bird's beak region is formed, the width of the element isolation region increases, reducing the area of the element forming region L2, and hindering miniaturization of the element structure.

Another problem is that a junction region is formed in which the heavily doped channel stop layer 8 formed under the field oxide film 7 and the heavily doped n+ impurity region 5a of the MOS transistor 2 are in direct contact with each other. It was difficult to maintain a high junction breakdown voltage.

Therefore, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a field oxide film that can reduce the bird's beak area and to improve the junction breakdown voltage at the edge of the field oxide film. An object of the present invention is to provide a semiconductor device having an isolation structure that can be obtained and a method for manufacturing the same.

[Means for Solving the Problems] A semiconductor device according to claim 1 is a semiconductor device of a first conductivity type, which has an element formation region in which a semiconductor element is formed on a main surface, and an element isolation region surrounding this element formation region. a semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate located in the element formation region via a gate insulating layer, and a pair of gate electrodes formed at a predetermined distance in the semiconductor substrate on both sides of the gate electrode. A second conductivity type high concentration impurity region, a pair of second conductivity type low concentration impurity regions connected to the second conductivity type high concentration impurity region and formed in the semiconductor substrate region directly under the gate electrode, and a pair of second conductivity type low concentration impurity regions located in the element isolation region. an element isolation insulating film formed on the surface of a semiconductor substrate, a channel stop region of a first conductivity type formed in the semiconductor substrate in contact with a lower surface of the element isolation insulator, and a channel stop region and a high concentration second conductivity type. and a first conductivity type low concentration impurity region formed in contact with the impurity region.

The invention according to claim 2 provides an LDD structure MOS in a region surrounded by an element isolation film on the main surface of a first conductivity type semiconductor substrate.
A method of manufacturing a semiconductor device including a transistor includes the following steps.

First, an oxidation-resistant film and a resist are formed on the main surface of a semiconductor substrate, and patterned into a predetermined shape. Next, impurity ions of the first conductivity type are ion-implanted into the semiconductor substrate using the patterned resist and the oxidation-resistant film as masks. Furthermore, a thermal oxidation treatment is performed to form an element isolation film on the surface of the semiconductor substrate not covered with the oxidation-resistant film, and at the same time, a channel stop layer of the first conductivity type is formed on the lower surface thereof. Furthermore, after exposing the surface region of the semiconductor substrate located in the element formation region surrounded by the element isolation film, a gate insulating film and a gate electrode are formed on the surface of the semiconductor substrate in the element formation region. Then, using the gate electrode as a mask, a second conductivity type impurity is ion-implanted obliquely to the main surface of the semiconductor substrate, and a first impurity at a relatively low concentration is implanted into the semiconductor substrate near the side end surface of the gate electrode. A first conductivity type low concentration impurity region adjacent to the channel stop layer is formed in the semiconductor substrate near the end face of the element isolation film. After forming an insulating layer on at least the sidewalls of the gate electrode, impurities of the second conductivity type are ion-implanted almost perpendicularly to the main surface of the semiconductor substrate using the gate electrode with the sidewall insulating layer formed as a mask. The invention according to claim 3 is a method for manufacturing an element isolation oxide film, characterized by a relatively highly concentrated second impurity region in contact with the first conductivity type low concentration impurity region, and the following: It has a process of

First, an oxidation-resistant film and a mask layer are formed on the main surface of a semiconductor substrate, and an opening of a predetermined shape is formed by selectively removing the oxidation-resistant film and mask layer located in a region that is to become an element isolation region. form a section. Next, using the mask layer as an ion implantation mask, ions are implanted obliquely to the main surface of the semiconductor substrate within the opening while rotating the semiconductor substrate, thereby forming an amorphous region at the center of the opening of the semiconductor substrate. Further, thermal oxidation treatment is performed to form a field oxide film on the surface of the semiconductor substrate within the opening of the oxidation-resistant film.

[Function] In the invention according to claim 1, a low concentration first conductivity type impurity region is provided between the second conductivity type high concentration impurity region of the MOS transistor and the first conductivity type high concentration channel stop region. p formed in this region by forming
By relaxing the concentration distribution of the n-junction and expanding the formation region of the depletion layer, the junction breakdown voltage can be improved.

Further, in the manufacturing method according to claim 2, the above-mentioned first
The conductivity type low concentration impurity region is the LDD of the MOS transistor.
It is formed using an ion implantation process to form a low concentration impurity region of the structure.

Therefore, there is no need to add a new manufacturing process.

Further, in the invention according to claim 3, only the central region of the substrate surface located within the opening region of the mask layer is made amorphous using the oblique ion implantation method. Then, when the amorphous silicon layer is thermally oxidized, accelerated oxidation is performed, and a thicker oxide film is formed in a shorter time than in other single crystal regions. Therefore, the field oxide film can be formed to a predetermined thickness until the bird's beak extends in the plane direction of the substrate. As a result, a fine device isolation oxide film with a reduced bird's beak region can be manufactured.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional structural diagram of a semiconductor device showing an embodiment of the invention according to claim 3. Referring to FIG. 1, a MOS transistor 2 and a field oxide film 7 for element isolation are shown on the surface of a p-type silicon substrate 1. MOS) transistor 2 has a source transistor consisting of a pair of n+ impurity regions.
It has a gate electrode 3 formed on the surface of the silicon substrate 1 located between the drain region 5.5 and the source/drain region 5.5 with a gate insulating film 4 interposed therebetween. adjacent M
A field oxide film 7 is formed between OS transistors 2.2. This field oxide film 7 has a shorter bird's beak region and a thicker film thickness t than the conventional field oxide film 7 shown in FIG. Therefore, when the film thickness is set to be the same as that of the conventional field oxide film 7, the width L1 of the field oxide film 7 can be formed smaller than that of the conventional field oxide film. An electrode layer 6 is disposed on the upper surface of the field oxide film 7, and a channel stop layer 8 made of a higher concentration p+ impurity region of the same conductivity type as the substrate is formed on the lower surface of the field oxide film 7. There is.

Next, a method for manufacturing the field oxide film shown in FIG. 1 will be explained using FIGS. 2A to 2C. Second
FIGS. A to 2C are manufacturing process cross-sectional views sequentially showing a method for manufacturing the field oxide film 7 shown in FIG.

First, referring to FIG. 2A, an underlying oxide film 14 with a thickness of 300 to 500 and a thickness of 5
00 to 1000 nitride films are sequentially formed. Furthermore, a resist is applied to the surface of the nitride film 9 to a thickness of 5000 to 1000.
Apply approximately 000 μm. Then, the resist 10 is patterned into a predetermined shape using a lithography method and an etching method, and the patterned resist 1
Using 0 as a mask, the nitride film 9 is selectively etched away. As a result, an opening 11 is formed.

The width of this opening 11 defines the isolation width of field oxide film 7.

Next, referring to FIG. 2B, using the resist pattern 10 as a mask, boron (B) ions 12 are implanted into the surface of the silicon substrate 1 using an oblique rotational ion implantation method. That is, boron ions 12 are implanted obliquely into the main surface of silicon substrate 1 while rotating silicon substrate 1 .

As a result, a high concentration impurity implantation region 13a is formed in the center of the surface of the silicon substrate 1 exposed within the opening 11 of the resist 10, and a low concentration impurity implantation region 13b is formed around it.

By this ion implantation step of the boron ions 12, an amorphous region in which the silicon substrate 1 is made amorphous is formed in the high concentration impurity implantation region 13a. Further, in the low concentration impurity implanted region 13b, the degree of amorphization is low and the boron ion concentration is low. Furthermore, this boron ion 1
When ion-implanting 2, the dose is 2X10"'am
An amorphous region can be formed under conditions of about -2.

This boron ion implantation simultaneously achieves two purposes.

The first is to implant an impurity (boron) to form a channel stop layer, and the other is to form an amorphous region near the center of the opening in the silicon substrate 1.

Thereafter, as shown in FIG. 2C, after removing the resist 10, steam oxidation is performed at a temperature of 800° C. for about 30 minutes to form a field oxide film on the surface of the silicon substrate 1 exposed in the opening 11 formed in the nitride film 9. form 7. by the way,
It is known that the oxidation rate of silicon is faster in an amorphous region than in a crystalline region. For this reason, the oxidation rate of the amorphous region 13a of the silicon substrate 1, which has been made amorphous by boron ion implantation, is faster than that of the impurity implanted region 13b around the amorphous region 13a. Therefore, the time required to reach a predetermined oxide film thickness is shortened compared to the conventional method. For this reason, the time required to form a bird's beak that progresses in the planar direction of the silicon substrate 1 is suppressed compared to the conventional method. As a result, the bird's beak becomes smaller. Furthermore, boron ions are also diffused into the substrate due to this oxidation treatment, but boron ions are implanted at a high concentration in the center of the opening and at a low concentration at the periphery, so the boron diffusion region is narrower than in the past. therefore,
Channel stop layer 8 formed by boron diffusion
is formed under the field oxide film 7, and the amount of protrusion toward the element forming region is suppressed.

Note that the ion implantation process shown in FIG. 2B can achieve the same effect by the following ion implantation process. That is, first, silicon (Si), argon (A), and oxygen (o
2) After forming an amorphous region by implanting ions, a p-type impurity such as boron may be implanted as a channel stop layer. In addition, when the substrate is an n-type silicon substrate, n-type impurities such as phosphorus (P) are added.
Alternatively, the amorphous region may be formed by oblique ion implantation using arsenic (A) or arsenic (A). The dose required to make a silicon substrate amorphous with these impurity ions is, for example, 6X1014 am-2 for silicon.
In the case of phosphorus, it is 1 x 1015 cm-2, and in the case of arsenic, it is about 3 x 1014c+T+-2.

Next, embodiments of the invention according to claims 1 and 2 will be described. FIG. 3 is a plan structural diagram of the semiconductor device according to the embodiment, and FIG. 4 is a cross-sectional structural diagram taken along the cutting line IV-IV in FIG. 3. The features of this embodiment are the heavily doped n+ impurity region 5a and the heavily doped channel stop layer 8 of the MOS transistor having an LDD structure.
This is because a low concentration p- impurity region 15 is formed between the two.

This p- impurity region 15 has the effect of increasing the spread of a depletion layer formed in the junction region when a reverse voltage is applied to the junction with the n+ impurity region 5a compared to the conventional one. This reduces the electric field applied to the junction surface and improves the junction breakdown voltage.

Next, a method for manufacturing the semiconductor device shown in FIG. 4 will be described. FIGS. 5A to 5D are cross-sectional views of the manufacturing process.

First, referring to FIG. 5A, on the surface of p-type silicon substrate 1, field oxide film 7, channel stop layer 8, and gate electrode 3 or electrode layer 6 patterned into a predetermined shape are manufactured by LOCO8 method.

Next, referring to FIG. 5B, phosphorus ions 16 are obliquely implanted using gate electrode 3 and field oxide film 7 as masks to form low concentration n- impurity region 5b on the surface of silicon substrate 1. This n impurity region 5b is formed so that a portion thereof sinks into the channel region of the MOS transistor. Furthermore, on the field oxide film 7 side, by this ion implantation, a low concentration (1016 to 10110 l8") of p
- Impurity region 15 is formed.

Furthermore, referring to FIG. 5C, after an oxide film is deposited on the entire surface of the silicon substrate 1, this oxide film is selectively removed by anisotropic etching. By this etching step, a sidewall oxide film 17 is formed on the sidewall of the gate electrode 3 or electrode layer 6.

Furthermore, referring to FIG. 5D, arsenic ions 19 are implanted into the surface of the silicon substrate 1 in a direction substantially perpendicular to the substrate surface using the gate electrode 3 and field oxide film 7 on which the sidewall oxide film 17 is formed as a mask. , and then performs activation processing. As a result, a highly concentrated n+ impurity region 5a is formed, and the LDD structure of the source/drain region is completed. Through the above steps, a low concentration p-type layer is formed between the channel stop layer 8 and the high concentration n+ impurity region 5a of the LDD MOS transistor at the end of the field oxide film 7.
- Impurity region 15 is formed.

In this way, in the above method, p- impurity region 1
5 can be formed simultaneously using the ion implantation process of the low concentration impurity region 5b of the MOS transistor. Therefore, there is no need for an increase in manufacturing steps.

Note that this second embodiment can be applied subsequent to the step of forming the field oxide film 7 manufactured according to the first embodiment. In this case, the field oxide film 7, which can reduce the isolation width, the channel stop layer 8, and the MOS
) It is possible to realize a semiconductor device having a structure in which the junction breakdown voltage between the source and drain regions of the transistor is improved.

In the above embodiment, an example in which oblique rotational ion implantation is performed before forming the sidewall oxide film 17 of the gate electrode 3 has been described.
You may do this after forming 7.

Similarly, although an example using the p-type silicon substrate 1 has been described in the above embodiment, the same method can be applied to the n-type silicon substrate 1 as well.

[Effects of the Invention] Thus, in the invention according to claim 1, the low concentration impurity layer is formed between the channel stop layer formed under the element isolation oxide film and the source/drain region of the transistor. , the junction breakdown voltage between the two can be improved. Further, in the invention according to claim 2, the low concentration impurity region is simultaneously formed using an oblique rotational ion implantation process for forming the low concentration impurity region forming the LDD structure of the transistor. , can be manufactured without adding a new manufacturing process.

Further, in the invention according to claim 3, only the central part of the substrate surface that is to become the element isolation region is made amorphous using an oblique rotational ion implantation method, and then thermal oxidation treatment is performed to form an isolation oxide film. With this configuration, the time required to form the isolation oxide film is shortened by accelerated oxidation through amorphization, and it becomes possible to suppress the formation of bird's beaks and manufacture an element isolation film with a fine structure.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional structural diagram of a semiconductor device according to an embodiment according to claim 3. 2A, 2B, and 2C are cross-sectional views of the manufacturing process of the semiconductor device shown in FIG. 1. 3 is a plan view of a semiconductor device according to an embodiment of the invention according to claims 1 and 2, and FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. be. Figures 5A, 5B, 5C and 5D are
FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device shown in the figure. FIG. 6 is a cross-sectional structural diagram of a conventional semiconductor device. 7th
Figure A, Figure 7B, Figure 7C, Figure 7D, Figure 7E, Figure 7
FIG. F and FIG. 7G are cross-sectional views of the manufacturing process of the semiconductor device shown in FIG. 6. In the figure, 1 is a p-type silicon substrate, 2 is a MOS transistor, 3 is a gate electrode, 5 is a source/drain region,
5a is an n+ impurity region of the source/drain region 5, 5b is an n- impurity region of the source/drain region 5, 7 is a field oxide film, 8 is a channel stop layer, 9 is a nitride film, 10 is a resist, and 12 is a p-type impurity region. type impurity ion, 13a
13b represents a high concentration impurity implantation region, 13b represents a low concentration impurity implantation region, and 15 represents a p- impurity region. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A semiconductor substrate of a first conductivity type having an element formation region in which a semiconductor element is formed on the main surface and an element isolation region surrounding the element formation region, and the semiconductor substrate located in the element formation region. a gate electrode formed on the surface with a gate insulating layer interposed therebetween; a sidewall oxide film covering sidewalls of the gate electrode; and a pair formed at a predetermined distance in the semiconductor substrate on both sides of the gate electrode. a second conductivity type high concentration impurity region; a pair of second conductivity type low concentration impurity regions continuous with the second conductivity type high concentration impurity region and formed in the semiconductor substrate region directly under the gate electrode; an element isolation insulating film formed on the surface of the semiconductor substrate located in an isolation region; a channel stop region of a first conductivity type formed in the semiconductor substrate in contact with a lower surface of the element isolation insulating film; and the channel A semiconductor device comprising: a first conductivity type low concentration impurity region formed in contact between a stop region and the second conductivity type high concentration impurity region. (2) A method for manufacturing a semiconductor device comprising an LDD structure MOS transistor in a region surrounded by an element isolation film on the main surface of a first conductivity type semiconductor substrate, the method comprising: a step of forming an oxidation-resistant film and a resist and patterning it into a predetermined shape; and a step of ion-implanting impurities of a first conductivity type into the semiconductor substrate using the patterned resist and the oxidation-resistant film as masks. , forming an element isolation film on the surface of the semiconductor substrate not covered with the oxidation-resistant film by performing thermal oxidation treatment, and simultaneously forming a channel stop layer of the first conductivity type continuous to the lower surface thereof; forming a gate insulating film and a gate electrode on the surface of the semiconductor substrate in the element formation region after exposing a surface region of the semiconductor substrate located in an element formation region surrounded by an element isolation film; A second conductivity type impurity is ion-implanted obliquely to the main surface of the semiconductor substrate using as a mask, and a relatively low concentration first impurity is implanted into the semiconductor substrate near the side end surface of the gate electrode. and forming a low concentration impurity region of a first conductivity type adjacent to the channel stop layer in the semiconductor substrate near an end surface of the element isolation film, and insulating at least a sidewall of the gate electrode. forming a second layer substantially perpendicularly to the main surface of the semiconductor substrate using the gate electrode on which the sidewall insulating layer is formed as a mask;
ion-implanting a conductivity type impurity to form a relatively high concentration second impurity region in contact with the low concentration first impurity region and the first conductivity type low concentration impurity region. Method of manufacturing the device. (3) Forming an oxidation-resistant film and a mask layer on the main surface of a semiconductor substrate, and selectively removing the oxidation-resistant film and the mask layer located in a region to be an inter-element isolation region to obtain a predetermined area. forming an opening in the shape of the semiconductor substrate; using the mask layer as an ion implantation mask, while rotating the semiconductor substrate, ions are implanted in the opening in a diagonal direction with respect to the main surface of the semiconductor substrate; forming an amorphous region in the central portion of the opening; and performing thermal oxidation to form a field oxide film on the main surface of the semiconductor substrate within the opening of the oxidation-resistant film. A method for manufacturing an element isolation oxide film.