JP2007258302A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that enables to form field oxide films having different bird's beak lengths on the surface of the same silicon substrate by using heat treatment for forming the field oxide film once, and a semiconductor device. <P>SOLUTION: In a first step (S1001) of manufacturing the semiconductor device, a silicon nitride film 30 is formed on an element region on the surface of a single-crystal silicon wafer 10 (strictly speaking, across a buffer oxide film 20). In a second step (S1002), oxidation-accelerating ions are implanted into a prescribed position in an element isolation region on the surface of the single-crystal silicon wafer 10 (in the case of this embodiment, a high breakdown-voltage element isolation region). In a third step (S1003), thermal oxidation processing is applied to the single-crystal silicon wafer 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

2. Description of the Related Art Conventionally, a LOCOS (Local Oxidation of Silicon) method is known as a method for electrically separating (insulating) elements formed on the surface of a silicon substrate such as a single crystal silicon wafer among semiconductor device manufacturing methods. ing.
The LOCOS method selectively oxidizes a predetermined region on the surface of a single crystal silicon wafer, so that an element region (a region in which a device is formed on the surface of the silicon substrate) among the surfaces of the silicon substrate. This is a method of forming an element isolation region (a region where electrical isolation (insulation) between element regions is performed).

Hereinafter, a conventional LOCOS method (hereinafter referred to as “conventional LOCOS method”) will be described with reference to FIGS. 42 and 43.
As shown in FIG. 42, the conventional LOCOS method generally includes a buffer oxide film formation step (S10100), a silicon nitride film formation step (S10200), a photolithography step (S10300), an etching step (S10400), and a photoresist removal. The process (S10500), the field oxide film formation process (S10600), and the final removal process (S10700) are performed in this order.

As shown in FIG. 43, the buffer oxide film forming step (S10100) is a step of forming a buffer oxide film 120 having a thickness of about several tens of nm to 100 nm on the surface of the single crystal silicon wafer 110. The buffer oxide film 120 is a film made of SiO ₂ for the purpose of relaxing and protecting the stress on the surface of the single crystal silicon wafer 110. The buffer oxide film 120 is usually formed by heating the single crystal silicon wafer 110 using a heating furnace or the like.

  The silicon nitride film forming step (S10200) is a step of forming a silicon nitride film 130 having a thickness of about 100 nm to 300 nm on the buffer oxide film 120. The silicon nitride film 130 is a film made of silicon nitride (SiN) and prevents oxidation of the surface of the single crystal silicon wafer 110 in a field oxide film forming process (S1600) which is a subsequent process. The silicon nitride film 130 is formed by CVD (Chemical Vapor Deposition) or the like.

  The photolithography process (S10300) is a process including a photoresist coating process (S10310) and a patterning process (S10320).

  The photoresist coating process (S10310) is a process of coating the photoresist 140 on the silicon nitride film. The photoresist 140 is usually a liquid or pasty photosensitive resin to which a solvent is added in order to give a certain degree of fluidity. By holding (pre-baking) the single crystal silicon wafer 110 coated with the photoresist 140 at a predetermined temperature for a predetermined time, the solvent contained in the photoresist 140 is removed and the fluidity is suppressed.

  The patterning step (S10320) is further divided into an exposure step (S10321) and a development step (S10322).

The exposure step (S10321) is a step of irradiating light of a predetermined wavelength with the surface of the photoresist 140 covered with a mask 150 having a predetermined shape.
The mask 150 is provided with openings 150 a, 150 a... Such as holes, grooves, notches, and the like. Of the photoresist 140 applied to the single crystal silicon wafer 110, the mask 150 is not covered with the mask 150 and is not covered with the mask 150. Only the photosensitive portion 141 (the portion corresponding to the openings 150a, 150a...) Irradiated with the light of the wavelength is altered, and the mask portion 142 that is covered with the mask 150 and not irradiated with the light of the predetermined wavelength is altered. do not do.

The developing step (S10322) is a step of forming a pattern of the photoresist 140 corresponding to the shape of the mask 150 on the silicon nitride film 130 by removing only the photosensitive portion 141 from the photoresist 140.
In the developing step (S10322), the photosensitive portion 141 is removed using a developer. Since the developer has a property of dissolving only the photosensitive portion 141 that has been altered by being irradiated with light of a predetermined wavelength, the developer is sprayed onto the photoresist 140 or the single crystal silicon wafer 110 coated with the photoresist 140. Is immersed in the developing solution, only the photosensitive portion 141 is removed, and a portion of the silicon nitride film 130 corresponding to the photosensitive portion 141 is exposed.
Thereafter, by holding (post-baking) the single crystal silicon wafer 110 at a predetermined temperature for a predetermined time, moisture and solvent are removed from the remaining photoresist 140, that is, the mask portion 142, and the mask portion 142 and the silicon nitride film are removed. Adhesion with 130 is enhanced.

The etching step (S10400) is a step of selectively removing the silicon nitride film 130 in a portion corresponding to the element isolation region, that is, a portion corresponding to the photosensitive portion 141.
In the etching step (S10400), there are methods such as dry etching (etching performed in the gas phase), wet etching (etching performed in the liquid phase), electric field etching (etching performed by energizing in the liquid phase), and the like. Used. At this time, the portion of the silicon nitride film 130 corresponding to the mask portion 142 is not removed because it is not in contact with the etching atmosphere (or etching solution). On the other hand, the portion of the silicon nitride film 130 corresponding to the photosensitive portion 141 is exposed by removing the photosensitive portion 141, so that it comes into contact with the etching atmosphere (or etching solution) and is removed by decomposition.

The photoresist removal step (S10500) is a step of removing the photoresist 140, that is, the mask portion 142 remaining on the surface of the single crystal silicon wafer 110 when the etching step (S10400) is completed.
In the photoresist removal step (S10500), the photoresist 140 (mask portion 142) is usually decomposed and removed by oxidization using oxygen plasma (ashing). In some cases, the photoresist 140 (mask portion 142) may be decomposed and removed using a chemical such as a remover.

In the field oxide film forming step (S10600), the surface of the single crystal silicon wafer 110 corresponding to the portion from which the silicon nitride film 130 has been removed in the etching step (S10400) is oxidized to form the field oxide film 160 in the portion. It is a process to do.
In the field oxide film forming step (S10600), the single crystal silicon wafer 110 is usually heated at a predetermined temperature for a predetermined time using a heating furnace.
As a result, a portion of the surface of the single crystal silicon wafer 110 from which the silicon nitride film 130 has been removed is oxidized to contact the atmosphere in the heating furnace, and a field oxide film 160 made of thick SiO ₂ is formed on the portion. Although formed, the portion where the silicon nitride film 130 remains is not oxidized because it does not contact the atmosphere in the heating furnace.

The final removal step (S10700) is a step of removing the remaining silicon nitride film 130 and buffer oxide film 120 formed on the surface of the single crystal silicon wafer 110.
In the final removal step (S10700), as in the etching step (S10400), dry etching (etching performed in the gas phase), wet etching (etching performed in the liquid phase), electric field etching (energization in the liquid phase) The silicon nitride film 130 and the buffer oxide film 120 are removed using a method such as etching.

  As described above, the conventional LOCOS method forms an element isolation region composed of the field oxide film 160 at a desired position on the surface of the single crystal silicon wafer 110, and electrically isolates the element regions across the element isolation region ( Insulation).

As shown in FIG. 43, bird's beak portions 160a and 160a are formed at the side ends of the field oxide film 160 in the conventional LOCOS method.
Bird's beak portions 160a and 160a are formed in the field oxide film formation step (S10600) from the end of silicon nitride film 130 to the boundary portion between silicon nitride film 130 and single crystal silicon wafer 110 (strictly speaking, buffer oxide film 120 and It is formed by oxygen entering and diffusing along the portion of the single crystal silicon wafer 110 facing the buffer oxide film 120, and extends along the surface direction of the buffer oxide film 120. The shape is just like a bird cage.

The bird's beak portions 160a and 160a are formed so as to protrude toward the mask portion 142 side from the end portion of the pattern of the photoresist 140 formed in the photolithography step (S10300) (that is, the end portion of the mask portion 142). The width of the oxide film 160 (the length from the tip of one bird's beak 160a to the tip of the other bird's beak 160a) is larger than the width of the opening 150a formed in the mask 150.
Therefore, there is a problem that a substantial distance between element regions formed on the surface of the single crystal silicon wafer 110 is increased, which becomes an obstacle to integration of elements in a semiconductor device.

  Therefore, a method for reducing the protrusion amount of the bird's beak portion of the field oxide film, that is, the bird's beak length (more precisely, the length from the end of the photoresist pattern to the tip of the bird's beak) has been studied.

Hereinafter, the conventional polybuffer LOCOS method will be described with reference to FIGS. 44 and 45. FIG.
As shown in FIG. 44, the conventional polybuffer LOCOS method generally includes a buffer oxide film forming step (S20100), a polysilicon film forming step (S20150), a silicon nitride film forming step (S20200), and a photolithography step (S20300). ), Etching step (S20400), photoresist removal step (S20500), field oxide film formation step (S20600), and final removal step (S20700).

  The conventional polybuffer LOCOS method is shown in FIGS. 42 and 43 in that a polysilicon film forming step (S20150) is provided between the buffer oxide film forming step (S20100) and the silicon nitride film forming step (S20200). Different from the conventional LOCOS method.

As shown in FIG. 45, the polysilicon film forming step (S20150) is a step of forming a polysilicon film 170 having a thickness of about 150 nm on the buffer oxide film 120.
The polysilicon film 170 is a film made of polycrystalline silicon, and is formed by CVD or the like.
The polysilicon film 170 is less affected by thermal distortion (such as formation of crystal defects) on the single crystal silicon wafer 110 than the silicon nitride film 130 and contributes to prevention of oxidation of the surface of the single crystal silicon wafer 110.

  The silicon nitride film forming step (S20200) is a step of forming a silicon nitride film 130 having a thickness of about 100 nm to 300 nm on the polysilicon film 170.

  As described above, in the conventional polybuffer LOCOS method, by forming the polysilicon film 170 between the buffer oxide film 120 and the silicon nitride film 130, the field oxide film 161 grows in the plane direction of the bird's beak portions 161a and 161a. As compared with the conventional LOCOS method shown in FIG. 43, the bird's beak length Lb of the bird's beak portions 161a and 161a can be shortened (Lb <La).

Hereinafter, the conventional R-LOCOS method will be described with reference to FIGS.
Conventional R-LOCOS methods generally include a buffer oxide film formation step (S30100), a silicon nitride film formation step (S30200), a photolithography step (S30300), an etching step (S30400), and a photoresist removal step (S30500). The field oxide film forming step (S30600) and the final removal step (S30700) are performed in this order.

  In the conventional R-LOCOS method, in the etching step (S30400), not only the silicon nitride film 130 but also the buffer oxide film 120 and the single crystal silicon wafer 110 are removed from the surface to a predetermined depth by etching, and the single crystal silicon wafer is removed. This is different from the conventional LOCOS method shown in FIGS. 42 and 43 in that the recess 110a is formed on the surface of 110. FIG.

As described above, the conventional R-LOCOS method oxidizes the portion corresponding to the recessed portion 110a formed on the surface of the single crystal silicon wafer 110 in the field oxide film forming step (S30600), thereby obtaining FIG. 42 and FIG. Compared to the conventional LOCOS method shown, it is possible to form a field oxide film 162 having a shape deeply buried inside the single crystal silicon wafer 110.
As a result, the amount of protrusion to the surface of the single crystal silicon wafer 110 is suppressed to improve the flatness of the surface of the single crystal silicon wafer 110, and the growth of the bird's beak portions 162a and 162a in the surface direction is suppressed and the bird's beak portions 162a. The bird's beak length Lc of 162a can be made shorter than the conventional polybuffer LOCOS method shown in FIGS. 44 and 45 (Lc <Lb). Note that improving the flatness of the surface of the single crystal silicon wafer 110 facilitates subsequent element formation in the element region, and thus enables miniaturization of elements and thus integration of elements.

  Thus, the smaller the bird's beak length of the field oxide film that forms the element isolation region, the smaller the width in the surface direction of the field oxide film, thereby facilitating device integration.

On the other hand, in recent years, the demand for semiconductor devices that handle large voltages has increased due to the spread of electric vehicles, and in the case of obtaining a large breakdown voltage (maximum voltage that can be insulated), the field oxide film that forms the element isolation region A larger bird's beak length is advantageous.
In the case of such a semiconductor device, (1) a region of an element that handles a large voltage on the surface of the same silicon substrate, and (2) an element for controlling these elements, which requires a large voltage. However, the optimization (compacting) of the semiconductor device is demanded by forming both the element regions where integration is required.

  A method has been proposed in which field oxide films having different bird's beak lengths are formed on the surface of the same silicon substrate to form element isolation regions having different breakdown voltages. For example, it is as described in Patent Document 1 and Patent Document 2.

The methods described in Patent Document 1 and Patent Document 2 both use two heat treatments (heating by a heating furnace or the like) to form field oxide films having different bird's beak lengths. This is because when the heat treatment temperature, the heat treatment time, and the heat treatment atmosphere, which are the heat treatment conditions, are determined, the bird's beak length is usually determined almost uniquely.
In the method described in Patent Document 1, a field oxide film having a bird's beak length smaller than that of the conventional LOCOS method is first formed on the surface of the silicon substrate based on the conventional polybuffer LOCOS method, and then the bird's beak length is determined based on the conventional LOCOS method. By forming a long field oxide film, field oxide films having different bird's beak lengths are formed on the surface of the same silicon substrate.
In the method described in Patent Document 2, first, a field oxide film is formed on the surface of a silicon substrate based on the conventional polybuffer LOCOS method, and then on the surface of the silicon substrate and the surface of the field oxide film. The thickness of the end portion (bird's beak portion) of the previously formed field oxide film is formed by heating the silicon nitride film formed by removing the portion of the silicon nitride film corresponding to the end portion of the field oxide film by etching. To grow.
Japanese Patent No. 2689004 Japanese Patent No. 3230184

However, the semiconductor device manufacturing methods described in Patent Document 1 and Patent Document 2 have the following problems because two heat treatments (heating by a heating furnace) are used for forming a field oxide film.
(1) The energy cost for manufacturing a semiconductor device is large.
(2) Since heating and cooling are repeated, the time required for production becomes long and productivity is not good.
(3) Since heat treatment using a heating furnace or the like is generally difficult to control the temperature distribution in the furnace uniformly, the yield decreases when the number of silicon substrates processed simultaneously in the same heating furnace increases. Cheap.

  In the method of manufacturing a semiconductor device described in Patent Document 2, a part of an antioxidant film (silicon nitride film) that protrudes (bulges) on the surface of the silicon substrate and is formed on a non-planar field oxide film. Must be removed by etching. In order to achieve this, the photoresist pattern is accurately applied to the uneven portion of the antioxidant film under the condition that the depth of focus margin is small or a high overlay accuracy is required in the exposure operation. It must be formed and is difficult to work.

  In view of the above circumstances, the present invention is a semiconductor device capable of forming field oxide films having different bird's beak lengths on the surface of the same silicon substrate using only one heat treatment for forming the field oxide film. Manufacturing method and semiconductor device are provided.

  The problem to be solved by the present invention is as described above. Next, means for solving the problem will be described.

That is, in claim 1,
A first step of forming an antioxidant film on the element region on the surface of the silicon substrate;
A second step of implanting oxidation promoting ions at a predetermined position of the element isolation region on the surface of the silicon substrate;
Applying a thermal oxidation process to the silicon substrate, and forming a field oxide film in an element isolation region on the surface of the silicon substrate;
It comprises.

In claim 2,
The second step includes
A photolithography process for ion implantation for forming a pattern of a photoresist for ion implantation having a shape covering the portion of the element isolation region excluding the predetermined position and the antioxidant film;
An ion implantation step of implanting oxidation promoting ions at a predetermined position of the element isolation region;
It comprises.

In claim 3,
In the second step, the oxidation promoting ions are implanted at an angle inclined with respect to the surface of the silicon substrate.

In claim 4,
The oxidation promoting ions include oxygen ions.

In claim 5,
The oxidation promoting ions include boron ions.

In claim 6,
The first step includes
A buffer oxide film forming step of forming a buffer oxide film on the surface of the silicon substrate;
An antioxidant film forming step of forming the antioxidant film on the buffer oxide film;
A photolithography step of forming a photoresist pattern in a shape covering the element region on the antioxidant film;
An etching step of removing a portion of the antioxidant film corresponding to the element isolation region;
A photoresist removal step of removing the photoresist from the silicon substrate;
It comprises.

In claim 7,
In the etching step, a portion of the antioxidant film corresponding to the element isolation region and a silicon substrate having a predetermined depth thereunder are removed.

In claim 8,
The first step includes
A buffer oxide film forming step of forming a buffer oxide film on the surface of the silicon substrate;
A polybuffer silicon film forming step of forming a polybuffer silicon film on the buffer oxide film;
An antioxidant film forming step of forming the antioxidant film on the polybuffer silicon film;
A photolithography step of forming a photoresist pattern in a shape covering the element region on the antioxidant film;
An etching step of removing a portion of the antioxidant film corresponding to the element isolation region;
A photoresist removal step of removing the photoresist from the silicon substrate;
It comprises.

In claim 9,
A first step of forming an antioxidant film on the element region on the surface of the silicon substrate;
A second step of implanting oxidation promoting ions at a predetermined position of the element isolation region on the surface of the silicon substrate;
Applying a thermal oxidation process to the silicon substrate, and forming a field oxide film in an element isolation region on the surface of the silicon substrate;
It is manufactured through.

  As effects of the present invention, the following effects can be obtained.

  According to the first aspect, it is possible to form field oxide films having different bird's beak lengths on the surface of the same silicon substrate by one thermal oxidation treatment.

  According to the second aspect of the present invention, it is possible to reliably implant oxidation promoting ions only at predetermined positions in the element isolation region, and to easily and reliably form field oxide films having different bird's beak lengths on the surface of the silicon substrate. Is possible.

  According to the third aspect of the present invention, it is possible to promote the growth of the bird's beak portion of the field oxide film formed in the element isolation region in the surface direction of the silicon substrate.

  According to the fourth aspect of the present invention, it is possible to promote the growth of the bird's beak portion of the field oxide film formed at a predetermined position in the element isolation region in the surface direction of the silicon substrate.

  According to the fifth aspect of the present invention, it is possible to promote the growth of the bird's beak portion of the field oxide film formed at a predetermined position in the element isolation region in the surface direction of the silicon substrate.

  According to the sixth aspect, it is possible to easily form field oxide films having different bird's beak lengths.

  According to the seventh aspect, it is possible to easily form field oxide films having different bird's beak lengths.

  According to the eighth aspect, it is possible to easily form field oxide films having different bird's beak lengths.

  According to the ninth aspect, it is possible to form field oxide films having different bird's beak lengths on the surface of the same silicon substrate by one thermal oxidation treatment.

A first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS.
The “semiconductor device” according to the present invention includes (a) a semiconductor element itself or (b) a device including one or more semiconductor elements.
Specific examples of the “device including one or a plurality of semiconductor elements” include a lateral power MOS (for example, LDMOS), an IGBT (Insulated (or Inverted) Gate Bipolar Transistor), a BT (Bipolar Transistor) module, and a GTO thyristor (Gate). (Turn Off Thyristor) and the like, in which semiconductor elements such as IGBTs, diodes, and CMOSs are mounted on an insulating substrate made of phenol resin or the like to form a predetermined circuit.

  As shown in FIG. 1, the first embodiment of the method for manufacturing a semiconductor device according to the present invention includes a first step (S1001), a second step (S1002), and a third step (S1003).

Hereinafter, the first step (S1001) will be described with reference to FIGS.
As shown in FIG. 1, the first step (S1001) includes a buffer oxide film formation step (S1010), a silicon nitride film formation step (S1020), a photolithography step (S1030), an etching step (S1040), and a photoresist removal step ( S1050).

  As shown in FIG. 2, the buffer oxide film forming step (S <b> 1010) is a step of forming the buffer oxide film 20 on the surface of the silicon single crystal wafer 10.

  The silicon single crystal wafer 10 is an embodiment of the “silicon substrate” according to the present invention. For example, single crystal silicon produced by a pulling method such as the Czochralski method (CZ method) or the FZ method (floating zone method). The ingot was sliced and cut into a substantially disk shape.

The silicon substrate according to the present invention is not limited to the silicon single crystal wafer 10 as in the present embodiment, and may be one obtained by cutting polycrystalline silicon into a plate shape.
The silicon substrate according to the present invention may be either P-type or N-type.

The “element region” according to the present invention refers to a region where a semiconductor element is formed on the surface (usually a wide plate surface) of the silicon substrate, and the “element isolation region” refers to a field oxide film on the surface of the silicon substrate. Refers to the area to be formed. Accordingly, a portion of the surface of the silicon substrate excluding the element isolation region can be defined as an element region.
Further, among the element isolation regions, a region where high breakdown voltage is important because it is adjacent to an element region where a semiconductor element that handles a large voltage is formed is a high breakdown voltage element isolation region, and adjacent element regions where breakdown voltage is not so important A region where the degree of integration is important is defined as a high-density element isolation region.
In this embodiment, of the two element isolation regions in FIG. 2, the left element isolation region is the high breakdown voltage element isolation region, and the right element isolation region is the high density element isolation region.

The buffer oxide film 20 is an embodiment of the “buffer oxide film” according to the present invention, and is a film made of silicon dioxide (SiO ₂ ).

In the buffer oxide film forming step (S1010), the silicon single crystal wafer 10 is accommodated in a heating furnace and heated at a predetermined temperature for a predetermined time. As a result, oxygen in the atmosphere in the heating furnace and silicon on the surface of the silicon single crystal wafer 10 are combined, and a buffer oxide film 20 of about 50 nm to 100 nm is formed on the surface of the silicon single crystal wafer 10.
The buffer oxide film is used to alleviate the distortion generated in the silicon substrate and the antioxidant film. The magnitude of the distortion depends on the size (diameter) of the silicon substrate and heat treatment conditions (described later in the field oxide film formation step). It varies depending on the heat treatment temperature, heat treatment time, atmosphere in the heating furnace) and the like. Therefore, the thickness of the buffer oxide film may be appropriately selected according to these conditions, and is not limited to this embodiment.

  When the buffer oxide film forming step (S1010) is completed, the process proceeds to the silicon nitride film forming step (S1020).

  As shown in FIG. 3, the silicon nitride film forming step (S1020) is a step of forming a silicon nitride film 30 on the buffer oxide film 20.

The silicon nitride film 30 is an embodiment of the “antioxidation film” according to the present invention, and is a film made of silicon nitride (SiN). The silicon nitride film 30 is a film formed to prevent oxidation (progress) of the surface of the silicon single crystal wafer 10 in a field oxide film formation step (S1090) described later.
In the silicon nitride film formation step (S1020), a silicon nitride film 30 of about 200 nm is formed on the buffer oxide film 20 by CVD (Chemical Vapor Deposition).

The “antioxidation film” according to the present invention is not limited to the silicon nitride film 30 as in this embodiment, and may be a film made of another material as long as the oxidation (progress) of the surface of the silicon substrate can be prevented. .
Further, the thickness of the antioxidant film according to the present invention is appropriately determined according to the material constituting the antioxidant film, the heat treatment conditions (heat treatment temperature, heat treatment time, atmosphere in the heating furnace) in the field oxide film forming step described later, and the like. Since it is selected, it is not limited to this embodiment.
The method of forming the antioxidant film according to the present invention is not limited to CVD as in this embodiment, and other methods may be used.

  When the silicon nitride film forming step (S1020) is completed, the process proceeds to the photolithography step (S1030).

  As shown in FIG. 1, the photolithography process (S1030) includes a photoresist coating process (S1031) and a patterning process (S1032).

  As shown in FIG. 4, the photoresist coating process (S <b> 1031) is a process of coating a photoresist 40 on the silicon nitride film 30.

  The photoresist 40 is usually a liquid or pasty photosensitive resin to which a solvent is added in order to give a certain degree of fluidity. The photoresist 40 is altered when irradiated with light of a predetermined wavelength. The unmodified photoresist 40 cannot be dissolved by the developer, but the altered photoresist 40 can be dissolved by the developer.

  In the photoresist coating process (S1031), a photoresist 40 is coated on the silicon nitride film 30. Next, the silicon single crystal wafer 10 in which the photoresist 40 is applied on the silicon nitride film 30 is accommodated in a heating furnace or the like and held at a predetermined temperature for a predetermined time (pre-baking). The solvent contained in the photoresist 40 is removed by pre-baking, and the fluidity of the photoresist 40 is suppressed.

  The method of applying the photoresist on the antioxidant film is as follows: (1) A predetermined amount of the photoresist is dropped on the antioxidant film, and the silicon substrate is rotated to rotate the photoresist on the antioxidant film by centrifugal force. (2) A method of uniformly stretching the photoresist on the antioxidant film using a tool such as a roller or a squeegee, etc., depending on the material of the photoresist and the size and shape of the silicon substrate Are appropriately selected.

  When the photoresist coating process (S1031) is completed, the process proceeds to the patterning process (S1032).

As shown in FIG. 1, the patterning step (S1032) includes an exposure step (S1033) and a development step (S1034).
As shown in FIG. 5, the exposure step (S1033) is a step of irradiating light of a predetermined wavelength with the surface of the photoresist 40 covered with a mask 50 of a predetermined shape.
The mask 50 is made of a material capable of blocking light of a predetermined wavelength, and the light of predetermined wavelength irradiated on the mask 50 is blocked and does not reach the opposite side of the mask 50. However, the mask 50 is provided with openings 50 a, 50 a... Such as holes, grooves, notches, etc., and light of a predetermined wavelength is transmitted to the opposite side of the mask 50 from the openings 50 a, 50 a. To reach.
The shape of the openings 50a, 50a,... Of the mask 50 is substantially the same as the shape of the element isolation region when the mask 50 is placed on the photoresist 40, as viewed from the method of irradiating light of a predetermined wavelength. is there.
When light having a predetermined wavelength is irradiated in a state where the mask 50 is disposed on the photoresist 40 (a state where the photoresist 40 is covered with the mask 50), only a portion of the photoresist 40 corresponding to the element isolation region is predetermined. The light corresponding to the element region is irradiated, and the light corresponding to the element region is not irradiated with the light having the predetermined wavelength.
As a result, in the photoresist 40 applied to the single crystal silicon wafer 10, the portion corresponding to the element isolation region is altered to form the photosensitive portion 41, and the portion corresponding to the element region is not altered, and the mask portion 42 is not altered. Form.

  When the exposure process (S1033) is completed, the process proceeds to the development process (S1034).

  As shown in FIG. 6, in the developing step (S1034), only the photosensitive portion 41 of the photoresist 40 is removed, thereby forming a pattern of the photoresist 40 corresponding to the shape of the mask 50, that is, the shape of the element region. It is.

In the developing step (S1034), a developer is sprayed onto the photoresist 40. As a result, only the photosensitive portion 41 of the photoresist 40 is dissolved and the mask portion 42 remains, so that a pattern of the photoresist 40 corresponding to the shape of the mask 50 is formed.
In this embodiment, the developer is sprayed onto the photoresist 40, but other methods may be used as long as only the photosensitive portion 41 can be removed. Examples of other methods include a method of immersing the single crystal silicon wafer 10 coated with the photoresist 40 in a developer.

  When the development process (S1034) is completed, the patterning process (S1032) is completed. When the patterning step (S1032) ends, the photolithography step (S1030) ends. When the photolithography process (S1030) is completed, the process proceeds to the etching process (S1040).

  As described above, the photolithography step (S1030) is a step of forming a pattern (mask portion 42) of the photoresist 40 having a shape covering the element region on the silicon nitride film 30.

  As shown in FIG. 7, the etching step (S1040) is a step of removing the portion of the silicon nitride film 30 corresponding to the element isolation region.

In the etching step (S1040), when RIE (Reactive Ion Etching) is applied to the single crystal silicon wafer 10 on which the pattern of the photoresist 40 corresponding to the shape of the mask 50 is formed, the mask portion of the silicon nitride film 30 is masked. The silicon nitride film 30 corresponding to 42 (portion corresponding to the element region) is not removed because it does not contact the etchant, and the remaining portion, that is, the exposed portion of the photosensitive portion 41 is removed (corresponding to the element isolation region). The silicon nitride film 30 in contact with the etchant is decomposed and removed. An etchant used for RIE includes a mixed gas of CHF ₃ and CF ₄ .

  When the etching process (S1040) is completed, the process proceeds to a photoresist removing process (S1050).

As shown in FIG. 8, the photoresist removing step (S1050) is a step of removing the photoresist 40 (mask portion 42) from the single crystal silicon wafer 10.
In the photoresist removal step (S1050), the photoresist 40 (mask portion 42) remaining on the single crystal silicon wafer 10 is oxidized and decomposed and removed by oxygen plasma.
In the present embodiment, the remaining photoresist 40 (mask portion 42) is removed from the single crystal silicon wafer 10 using oxygen plasma. However, the photoresist removal process according to the present invention is not limited to this, The photoresist may be removed from the silicon substrate by other methods such as using a predetermined chemical (such as a remover).

  When the photoresist removal step (S1050) is finished, the first step (S1001) is finished. When the first step (S1001) is completed, the process proceeds to the second step (S1002).

  As described above, the first step (S1001) is a step of forming the silicon nitride film 30 on the element region on the surface of the silicon single crystal wafer 10.

Hereinafter, the second step (S1002) will be described with reference to FIG. 1 and FIG. 9 to FIG.
As shown in FIG. 1, the second step (S1002) includes an ion implantation photolithography step (S1060), an ion implantation step (S1070), and an ion implantation photoresist removal step (S1080).
The ion implantation photolithography process (S1060) includes an ion implantation photoresist coating process (S1061) and an ion implantation patterning process (S1062).

As shown in FIG. 9, in the ion implantation photoresist coating step (S1061), the ion implantation photoresist 45 is coated on the silicon single crystal wafer 10 in which the silicon nitride film 30 is formed on the portion corresponding to the element region. It is a process.
The ion implantation photoresist 45 is a photosensitive resin similar to the photoresist 40.

  In the ion implantation photoresist coating process (S1061), the ion implantation photoresist 45 is formed on the silicon nitride film 30 and on the portion where the silicon nitride film 30 is removed in the etching process (S1040) (the portion corresponding to the element isolation region). Is applied. Next, the silicon single crystal wafer 10 is accommodated in a heating furnace or the like and held at a predetermined temperature for a predetermined time (pre-baking). The solvent contained in the ion implantation photoresist 45 is removed by pre-baking, and the fluidity of the ion implantation photoresist 45 is suppressed.

  When the photoresist coating process for ion implantation (S1061) is completed, the process proceeds to a patterning process for ion implantation (S1062).

As shown in FIG. 1, the ion implantation patterning step (S1062) includes an ion implantation exposure step (S1063) and an ion implantation development step (S1064).
As shown in FIG. 10, the ion implantation exposure step (S1063) is a step of irradiating light of a predetermined wavelength with the surface of the ion implantation photoresist 45 covered with a mask 51 of a predetermined shape.
The mask 51 is made of a material capable of blocking light of a predetermined wavelength, and the light of predetermined wavelength irradiated to the mask 51 is blocked and does not reach the opposite side of the mask 51. However, the mask 51 is provided with openings 51 a, 51 a, etc. such as holes, grooves, notches, etc., and light of a predetermined wavelength is transmitted to the opposite side of the mask 51 from the openings 51 a, 51 a,. To reach.
The shape of the openings 51a, 51a,... Of the mask 51 is such that, when the mask 51 is placed on the ion implantation photoresist 45, in the element isolation region, as viewed from the light irradiation method of a predetermined wavelength. It is substantially the same as the shape of the high voltage element isolation region.
When light having a predetermined wavelength is irradiated in a state where the mask 51 is disposed on the ion implantation photoresist 45 (in a state where the ion implantation photoresist 45 is covered with the mask 51), the highest in the ion implantation photoresist 45. Only a portion corresponding to the withstand voltage element isolation region is irradiated with light having a predetermined wavelength, and a portion corresponding to the element region and the high density element isolation region is not irradiated with light having a predetermined wavelength.
As a result, in the photoresist 45 for ion implantation applied to the single crystal silicon wafer 10, the portion corresponding to the high breakdown voltage element isolation region is altered to form the photosensitive portion 46, thereby forming the element region and the high density element isolation region. The mask portion 47 is formed without changing the corresponding portion.

  When the ion implantation exposure step (S1063) is completed, the process proceeds to an ion implantation development step (S1064).

  As shown in FIG. 11, in the ion implantation development step (S1064), by removing only the photosensitive portion 46 from the ion implantation photoresist 45, the shape of the mask 51, that is, the device region and the high-density device isolation region are matched. This is a step of forming a pattern of the ion implantation photoresist 45 corresponding to the shape.

In the ion implantation development step (S1064), a developer is sprayed onto the ion implantation photoresist 45. As a result, only the photosensitive portion 46 of the ion implantation photoresist 45 is dissolved and the mask portion 47 remains, whereby a pattern of the ion implantation photoresist 45 corresponding to the shape of the mask 51 is formed.
In this embodiment, the developer is sprayed onto the ion implantation photoresist 45, but other methods may be used as long as only the photosensitive portion 46 can be removed. As an example of another method, there is a method of immersing the single crystal silicon wafer 10 coated with the ion implantation photoresist 45 in a developer.

  When the ion implantation development process (S1064) is completed, the ion implantation patterning process (S1062) is completed. When the ion implantation patterning step (S1062) is completed, the ion implantation photolithography step (S1030) is terminated. When the ion implantation photolithography process (S1060) is completed, the process proceeds to the ion implantation process (S1070).

  As described above, the ion implantation photolithography step (S1060) is for ion implantation having a shape covering the portion of the element isolation region excluding the high breakdown voltage element region (that is, the high density element isolation region) and the silicon nitride film 30. This is a step of forming a pattern (mask portion 47) of the photoresist 45.

  As shown in FIG. 12, the ion implantation step (S1070) is a step of implanting oxidation promoting ions into the high breakdown voltage element isolation region (“predetermined position of the element isolation region” in this embodiment).

  “Oxidation promoting ions” according to the present invention refers to ions that can promote the formation of a field oxide film formed in a field oxide film forming step, which will be described in detail later. Specifically, oxygen ions, boron ions, etc. Can be mentioned.

Among the oxidation promoting ions, oxygen ions contribute to the promotion of the formation of the field oxide film by themselves being used as elements (raw materials) constituting the field oxide film.
Among the oxidation-promoting ions, boron ions are not elements that constitute field oxide films themselves, but are empirically known to promote the oxidation of silicon substrates by being implanted into the silicon substrate. It is.
The oxidation promoting ions according to the present invention are not limited to oxygen ions and boron ions as in this embodiment. Other ions may be used as long as they can promote the formation of the field oxide film by being implanted into the silicon substrate. good.
Moreover, it is good also as a structure which inject | pours one type of oxidation promotion ion, and it is good also as a structure which injects in the state which mixed multiple types of oxidation promotion ion, and also as a structure which injects several types of oxidation promotion ion one by one in order good.

  In the ion implantation step (S1070), oxidation promoting ions are implanted into the single crystal silicon wafer 10 accommodated in the ion implantation apparatus. In addition, although the ion implantation apparatus of a present Example is an exclusive article, it is also possible to use a commercially available ion implantation apparatus. As a specific method of ion implantation, an existing method such as ion shower or plasma doping can be used.

  At this time, since the silicon nitride film 30 is removed and the photosensitive portion 46 of the ion implantation photoresist 45 is also removed from the high voltage element isolation region of the single crystal silicon wafer 10, the buffer silicon film 20 is exposed to the outside. In this state, the oxidation promoting ions penetrate the buffer silicon film 20 and reach the inside of the single crystal silicon 10.

Since the portion where the photosensitive portion 46 is removed in the pattern of the ion implantation photoresist 45 usually has a predetermined width, the oxidation promoting ions are inclined with respect to the surface (high voltage element isolation region) of the single crystal silicon wafer 10. Injected at an angle. As a result, the oxidation promoting ions reach not only the high breakdown voltage element isolation region but also a portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region.
On the other hand, the silicon nitride film 30 is formed on the element region and the high-density element isolation region of the single crystal silicon wafer 10, and the pattern (mask portion 47) of the photoresist 45 for ion implantation is further formed thereon. Yes. Therefore, except for a portion adjacent to the high breakdown voltage element isolation region in the element region (below the end of the silicon nitride film 30), the oxidation promoting ions are blocked by the silicon nitride film 30 and the ion implantation photoresist 45 to be single crystal. The inside of the silicon 10 cannot be reached.

In addition, the angle of the oxidation promoting ion implantation angle θ 1, that is, the angle formed by the normal of the surface of the single crystal silicon wafer 10 and the direction of implantation of the oxidation promoting ions is increased, and the angle more inclined with respect to the surface of the single crystal silicon wafer 10 By implanting the oxidation promoting ions, the oxidation promoting ions can efficiently reach the portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region.
As a method for increasing the implantation angle of oxidation promoting ions, the thickness of the pattern (mask portion 47) of the photoresist 45 for ion implantation can be reduced as much as possible within a range in which oxidation promoting ions can be blocked.
Further, as another method for increasing the implantation angle of oxidation promoting ions, as shown in FIG. 16, in the pattern (mask portion 47) of the photoresist 45 for ion implantation, the boundary surface with the photosensitive portion 46 is used for ion implantation. A method (θ2> θ1) in which the width of the portion where the photosensitive portion 46 is removed is increased as the surface of the photoresist 45 is approached.

  When the ion implantation step (S1070) is completed, the process proceeds to a photoresist removal step for ion implantation (S1080).

As shown in FIG. 13, the ion implantation photoresist removal step (S 1080) is a step of removing the remaining ion implantation photoresist 45 (mask portion 47) from the single crystal silicon wafer 10.
In the ion implantation photoresist removing step (S1080), the photoresist 45 (mask portion 47) remaining on the single crystal silicon wafer 10 is oxidized and decomposed and removed by oxygen plasma.
In this embodiment, oxygen plasma is used to remove the remaining ion implantation photoresist 45 (mask portion 47) from the single crystal silicon wafer 10, but the photoresist removal process according to the present invention is limited to this. Alternatively, the ion implantation photoresist may be removed from the silicon substrate by other methods such as using a predetermined chemical (such as a remover).

  When the photoresist removal step for ion implantation (S1080) is completed, the second step (S1002) is completed. When the second step (S1002) is completed, the process proceeds to the third step (S1003).

  As described above, the second step (S1002) is a step of implanting oxidation promoting ions into the high breakdown voltage element isolation region (“predetermined position of the element isolation region” in this embodiment) on the surface of the single crystal silicon wafer 10. .

Below, a 3rd process (S1003) is demonstrated using FIG.1, FIG.14 and FIG.15.
As shown in FIG. 1, the third step (S1003) includes a field oxide film formation step (S1090) and a final removal step (S1100).

  As shown in FIG. 14, the field oxide film forming step (S1090) is a step of forming field oxide films 61 and 62 in the element isolation region on the surface of the single crystal silicon wafer 10.

In the field oxide film forming step (S1090), the single crystal silicon wafer 10 is accommodated in a heating furnace (not shown) and held at a temperature of about 1100 ° C. to 1200 ° C. for a predetermined time.
In addition, since the holding temperature (heat treatment temperature) of the heating furnace is appropriately selected according to the composition of the atmosphere and other conditions, it is not limited to about 1100 ° C. to 1200 ° C. as in this embodiment.
The composition of the atmosphere in the heating furnace may be the same as that of normal air, but the oxygen concentration is larger than that of the air, oxygen and water (water vapor) are mixed, or hydrogen and oxygen are mixed. good.

  When the single crystal silicon wafer 10 is maintained at a temperature of about 1100 ° C. to 1200 ° C. in the heating furnace, the portion of the surface of the single crystal silicon wafer 10 covered with the silicon nitride film 30, that is, the element region is silicon nitride. Since it is blocked by the film 30 and does not come into contact with the atmosphere in the heating furnace, it is not oxidized, but the portion of the surface of the single crystal silicon wafer 10 that is not covered with the silicon nitride film 30, that is, the element isolation region is the heating furnace The field oxide films 61 and 62 are formed by being oxidized to come into contact with the inner atmosphere.

  Oxygen that has entered the inside of the single crystal silicon wafer 10 corresponding to the element isolation region from the atmosphere of the heating furnace also diffuses in the plane direction of the single crystal silicon wafer 10. Therefore, the end portions of the field oxide films 61 and 62 grow in the direction of the surface of the single crystal silicon wafer 10 so as to sink under the silicon nitride film 30, and bird's beak portions 61a and 61a and bird's beak portions 62a and 62a are formed. The

At this time, oxidation-promoting ions are implanted into the high breakdown voltage element isolation region (the element isolation region on the left side in FIG. 14) and the portion adjacent to the high breakdown voltage element isolation region in the element region in the second step (S1002). Therefore, the bird's beak parts 61a and 61a of the field oxide film 61 formed in the high breakdown voltage element isolation region are more than the bird's beak parts 62a and 62a of the field oxide film 62 formed in the high density element isolation region. Growth in the surface direction is further promoted and becomes longer (L1> L2).
As a result, a field oxide film 61 having a relatively long bird's beak length is formed in the high breakdown voltage element isolation region where a high breakdown voltage is required, and a high breakdown voltage is required without requiring a high breakdown voltage. A field oxide film 62 having a relatively short bird's beak length and a small protrusion amount to an adjacent element region is formed in the density element isolation region.
In this way, by selectively injecting oxidation promoting ions into a predetermined position (high breakdown voltage element isolation region) in the element isolation region on the surface of the single crystal silicon wafer 10 subjected to the thermal oxidation treatment only once, Field oxide film 61 having a different bird's beak length (and thus a different breakdown voltage and influence on integration of adjacent element regions) even though the heat treatment is performed under the same conditions (heat treatment temperature, heat treatment time, and atmosphere). -62 can be formed.

  In the case of the present embodiment, the amount of oxidation promoting ions implanted into the high breakdown voltage element region and the portion adjacent to the high breakdown voltage element isolation region in the ion implantation step (S1070) is the implantation time by the ion implantation apparatus. It can be easily adjusted by adjusting the ionization voltage or the like. Accordingly, the bird's beak length L1 of the field oxide film 61 can be accurately adjusted by adjusting the implantation amount of the oxidation promoting ions.

  When the field oxide film formation step (S1090) is completed, the process proceeds to the final removal step (S1100).

As shown in FIG. 15, the final removal step (S 1100) is a step of removing the silicon nitride film 30 and the buffer oxide film 20 on the surface of the single crystal silicon wafer 10.
In the final removal step (S1100), first, the silicon nitride film 30 on the surface of the single crystal silicon wafer 10 is removed by wet etching using hot phosphoric acid, and then the buffer oxide film 20 is removed using buffered hydrofluoric acid or the like. Is done.
In this embodiment, the silicon nitride film 30 and the buffer oxide film 20 are removed using hot phosphoric acid and buffered hydrofluoric acid. However, the present invention is not limited to this. It may be removed by a method.

  When the final removal step (S1100) ends, the third step (S1003) ends.

As described above, in the third step (S1003), the single crystal silicon wafer 10 is subjected to a predetermined thermal oxidation process to form field oxide films 61, 62... In the element isolation region on the surface of the single crystal silicon wafer 10. It is.
Here, the “thermal oxidation process” according to the present invention refers to a process of oxidizing the surface (a desired position) of the substrate silicon by holding the substrate silicon at a predetermined temperature in an oxygen atmosphere. Note that oxygen existing in the oxygen atmosphere may be in any state (ion, atom, molecule, compound) as long as the substrate silicon can be oxidized.

  After the completion of the third step (S1003), a power semiconductor element (semiconductor element that handles high voltage) such as LDMOS is formed in the element region adjacent to the high breakdown voltage element isolation region on the surface of the single crystal silicon wafer 10, In the element region adjacent to the high-density element isolation region on the surface of the single crystal silicon wafer 10, for example, semiconductor elements such as CMOS are required to be integrated, and wiring between these semiconductor elements is applied to the semiconductor. The device is completed.

As described above, the first embodiment of the method of manufacturing a semiconductor device according to the present invention is as follows.
A first step (S1001) of forming a silicon nitride film 30 on the element region on the surface of the single crystal silicon wafer 10 (strictly speaking, sandwiching the buffer oxide film 20);
A second step (S1002) of implanting oxidation-promoting ions into a predetermined position of the element isolation region on the surface of the single crystal silicon wafer 10 (in this embodiment, a high breakdown voltage element isolation region);
A third step (S1003) for subjecting the single crystal silicon wafer 10 to a thermal oxidation treatment;
It comprises.
With this configuration, it is possible to form field oxide films 61 and 62 having different bird's beak lengths on the surface of the same single crystal silicon wafer 10 by a single thermal oxidation process, which improves the productivity of semiconductor devices. Contributes to improvement and reduction of energy required for production of semiconductor devices.

The second step (S1002) of the first embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A pattern (mask) of the ion implantation photoresist 45 in a shape covering the portion of the element isolation region of the single crystal silicon wafer 10 excluding a predetermined position (in this embodiment, a high density element isolation region) and the silicon nitride film 30. A photolithography process for ion implantation (S1060) for forming a portion 47);
An ion implantation step (S1070) for implanting oxidation-promoting ions into a predetermined position of the element isolation region of the single crystal silicon wafer 10 (in this embodiment, a high breakdown voltage element isolation region);
It comprises.
With this configuration, it is possible to reliably implant oxidation promoting ions only at predetermined positions in the element isolation region, and field oxide films 61 and 62 having different bird's beak lengths are formed on the surface of the single crystal silicon wafer 10. It can be easily and reliably formed.

The first embodiment of the semiconductor device manufacturing method according to the present invention is as follows:
In the ion implantation step (S1070), the oxidation promoting ions are implanted at an angle inclined with respect to the surface of the single crystal silicon wafer 10 (at an angle not orthogonal to the surface of the single crystal silicon wafer 10).
With this configuration, in the ion implantation step (S1070), the oxidation promoting ions are not limited to a predetermined position, that is, not only the high breakdown voltage element isolation region but also a portion adjacent to the high breakdown voltage element isolation region (silicon nitride film 30). (Below the end of the). As a result, in the third step (S1003), more strictly, in the field oxide film forming step (S1090), the bird's beak portions 61a and 61a of the field oxide film 61 formed in the element isolation region are directed in the plane direction of the single crystal silicon wafer 10. It is possible to further promote the growth of

The first embodiment of the semiconductor device manufacturing method according to the present invention is as follows:
Oxidation promoting ions contain oxygen ions.
With this configuration, oxygen ions implanted into a predetermined position, that is, the high breakdown voltage element isolation region in the ion implantation step (S1070) are used as elements (raw materials) constituting the field oxide film 61 by themselves. This contributes to the promotion of the formation of the field oxide film 61.
As a result, the bird's beak length L1 of the field oxide film 61 becomes longer than the bird's beak length L2 of the field oxide film 62 formed in the high-density element isolation region where oxygen ions are not implanted.

The first embodiment of the semiconductor device manufacturing method according to the present invention is as follows:
Boron ions are included in the oxidation promoting ions.
With this configuration, boron ions implanted into a predetermined position, that is, the high breakdown voltage element isolation region in the ion implantation step (S1070) contribute to the promotion of the formation of the field oxide film 61.
As a result, the bird's beak length L1 of the field oxide film 61 becomes longer than the bird's beak length L2 of the field oxide film 62 formed in the high-density element isolation region where oxygen ions are not implanted.

The first step (S1001) of the first embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A buffer oxide film forming step (S1010) for forming a buffer oxide film 20 on the surface of the silicon single crystal wafer 10;
Forming a silicon nitride film 30 on the buffer oxide film 20 (S1020);
A photolithography step (S1030) for forming a pattern (mask portion 42) of a photoresist 40 having a shape covering the element region on the silicon nitride film 30;
An etching step (S1040) for removing a portion of the silicon nitride film 30 corresponding to the element isolation region;
A photoresist removal step (S1050) for removing the photoresist 40 (mask portion 42) from the single crystal silicon wafer 10;
It comprises.
With this configuration, the first embodiment of the method of manufacturing a semiconductor device according to the present invention has a working process flow in the middle of the conventional LOCOS method shown in FIGS. 42 and 43 (photoresist removal process (S10500)). And the field oxide film forming step (S10600)) with the second step (S1002) sandwiched therebetween.
Therefore, it is possible to easily form field oxide films 61 and 62 having different bird's beak lengths using existing semiconductor manufacturing equipment. In other words, it contributes to the reduction of the introduction cost to the manufacturing site.

  The second embodiment of the semiconductor device manufacturing method according to the present invention will be described below with reference to FIGS. 2 and 17 to 31.

  As shown in FIG. 17, the second embodiment of the method for manufacturing a semiconductor device according to the present invention includes a first step (S2001), a second step (S2002), and a third step (S2003).

Hereinafter, the first step (S2001) will be described with reference to FIGS. 2 and 17 to 24.
As shown in FIG. 17, the first process (S2001) includes a buffer oxide film forming process (S2010), a polybuffer silicon film forming process (S2015), a silicon nitride film forming process (S2020), a photolithography process (S2030), and an etching process. Step (S2040) and photoresist removal step (S2050) are provided.

  As shown in FIG. 2, the buffer oxide film forming step (S2010) is a step of forming the buffer oxide film 20 on the surface of the silicon single crystal wafer 10.

  When the buffer oxide film forming step (S2010) is completed, the process proceeds to a polybuffer silicon film forming step (S2015).

  As shown in FIG. 18, the polybuffer silicon film forming step (S2015) is a step of forming a polybuffer silicon film 70 on the buffer oxide film 20.

  When the polybuffer silicon film forming step (S2015) is completed, the process proceeds to a silicon nitride film forming step (S2020).

  As shown in FIG. 19, the silicon nitride film forming step (S1020) is a step of forming the silicon nitride film 30 on the polybuffer silicon film.

  When the silicon nitride film forming step (S2020) is completed, the process proceeds to the photolithography step (S2030).

As shown in FIGS. 17 and 20 to 22, the photolithography process (S2030) includes a photoresist coating process (S2031) and a patterning process (S2032).
Since the photolithography process (S2030) is substantially the same as the photolithography process (S2030) in the first embodiment of the semiconductor device manufacturing method according to the present invention (see FIG. 1 and FIGS. 4 to 6), the description will be omitted. Omitted.

  When the photolithography process (S2030) is completed, the process proceeds to the etching process (S2040).

  As shown in FIG. 23, the etching step (S2040) is a step of removing the portion of the silicon nitride film 30 corresponding to the element isolation region.

In the etching step (S2040), when RIE (Reactive Ion Etching) is applied to the single crystal silicon wafer 10 on which the pattern of the photoresist 40 corresponding to the shape of the mask 50 is formed, the mask portion of the silicon nitride film 30 is masked. The silicon nitride film 30 corresponding to 42 (portion corresponding to the element region) is not removed because it does not contact the etchant, and the remaining portion, that is, the exposed portion of the photosensitive portion 41 is removed (corresponding to the element isolation region). The upper half of the silicon nitride film 30 and the poly buffer silicon film 70 below the silicon nitride film 30 are in contact with the etchant and are removed by decomposition.
In this embodiment, in the etching step (S2040), the silicon nitride film 30 corresponding to the element isolation region and the upper half of the polybuffer silicon film 70 corresponding to the element isolation region are removed. A configuration may be adopted in which all of the corresponding silicon nitride film 30 and the polybuffer silicon film 70 corresponding to the element isolation region are decomposed and removed.

  When the etching process (S2040) is completed, the process proceeds to a photoresist removing process (S1050).

  As shown in FIG. 24, the photoresist removing step (S2050) is a step of removing the photoresist 40 (mask portion 42) from the single crystal silicon wafer 10.

  When the photoresist removal step (S2050) is finished, the first step (S2001) is finished. When the first step (S2001) is completed, the process proceeds to the second step (S2002).

  As described above, the first step (S2001) is a step of forming the silicon nitride film 30 on the element region on the surface of the silicon single crystal wafer 10.

Hereinafter, the second step (S2002) will be described with reference to FIGS. 17 and 25 to 29. FIG.
As shown in FIG. 17, the second step (S2002) includes an ion implantation photolithography step (S2060), an ion implantation step (S2070), and an ion implantation photoresist removal step (S2080).
As shown in FIGS. 17 and 25 to 27, the ion implantation photolithography process (S2060) includes an ion implantation photoresist coating process (S2061) and an ion implantation patterning process (S2062).
The ion implantation photolithography process (S2060) is substantially the same as the ion implantation photolithography process (S1060) in the first embodiment of the method of manufacturing a semiconductor device according to the present invention (FIGS. 1 and 9 to 9). 11), description thereof is omitted.

  When the ion implantation photolithography process (S2060) is completed, the process proceeds to the ion implantation process (S2070).

  In the ion implantation photolithography step (S2060), the ion implantation photoresist 45 having a shape covering the portion of the element isolation region excluding the high breakdown voltage element region (that is, the high density element isolation region) and the silicon nitride film 30 is formed. This is a step of forming a pattern (mask part 47).

  As shown in FIG. 28, the ion implantation step (S2070) is a step of implanting oxidation promoting ions into the high breakdown voltage element isolation region (“predetermined position of the element isolation region” in this embodiment).

  In the ion implantation step (S2070), oxidation promoting ions are implanted into the single crystal silicon wafer 10 accommodated in the ion implantation apparatus. In addition, although the ion implantation apparatus of a present Example is an exclusive article, it is also possible to use a commercially available ion implantation apparatus. As a specific method of ion implantation, an existing method such as ion shower or plasma doping can be used.

  At this time, in the high breakdown voltage element isolation region of the single crystal silicon wafer 10, the upper half of the silicon nitride film 30 and the polybuffer silicon film 70 is removed, and the photosensitive portion 46 of the ion implantation photoresist 45 is also removed. Therefore, the oxidation promoting ions pass through the lower half of the polybuffer silicon film 70 and the buffer silicon film 20 and reach the inside of the single crystal silicon 10.

Since the portion where the photosensitive portion 46 is removed in the pattern of the ion implantation photoresist 45 usually has a predetermined width, the oxidation promoting ions are inclined with respect to the surface (high voltage element isolation region) of the single crystal silicon wafer 10. Injected at an angle. As a result, the oxidation promoting ions reach not only the high breakdown voltage element isolation region but also a portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region.
On the other hand, in the element region and the high-density element isolation region of the single crystal silicon wafer 10, the polybuffer silicon film 70 and the silicon nitride film 30 are formed thereon, and a pattern (mask portion) of the photoresist 45 for ion implantation is further formed thereon. 47) is also formed. Therefore, except for the portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region, the oxidation promoting ions are the polybuffer silicon film 70, the silicon nitride film 30, and the ion implantation photoresist 45. It is blocked by the pattern (mask portion 47) and cannot reach the inside of the single crystal silicon 10.

  In addition, the angle of the oxidation promoting ion implantation angle θ 1, that is, the angle formed by the normal of the surface of the single crystal silicon wafer 10 and the direction of implantation of the oxidation promoting ions is increased, and the angle is more inclined with respect to the surface of the single crystal silicon wafer 10. By implanting the oxidation promoting ions, the oxidation promoting ions can efficiently reach the portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region.

  When the ion implantation step (S2070) is completed, the process proceeds to an ion implantation photoresist removal step (S2080).

  As shown in FIG. 29, the ion implantation photoresist removal step (S2080) is a step of removing the remaining ion implantation photoresist 45 (mask portion 47) from the single crystal silicon wafer 10.

  When the photoresist removal process for ion implantation (S2080) is completed, the second process (S2002) is completed. When the second step (S2002) is completed, the process proceeds to the third step (S2003).

  As described above, the second step (S2002) is a step of implanting oxidation promoting ions into the high breakdown voltage element isolation region (“predetermined position of the element isolation region” in this embodiment) on the surface of the single crystal silicon wafer 10. .

Below, a 3rd process (S2003) is demonstrated using FIG.17, FIG.30 and FIG.31.
As shown in FIG. 17, the third step (S2003) includes a field oxide film formation step (S2090) and a final removal step (S2100).

  As shown in FIG. 30, the field oxide film forming step (S2090) is a step of forming field oxide films 63 and 64 in the element isolation region on the surface of the single crystal silicon wafer 10.

In the field oxide film forming step (S2090), the single crystal silicon wafer 10 is accommodated in a heating furnace (not shown) and held at a temperature of about 1100 ° C. to 1200 ° C. for a predetermined time.
In addition, since the holding temperature (heat treatment temperature) of the heating furnace is appropriately selected according to the composition of the atmosphere and other conditions, it is not limited to about 1100 ° C. to 1200 ° C. as in this embodiment.
The composition of the atmosphere in the heating furnace may be the same as that of normal air, but the oxygen concentration is larger than that of the air, oxygen and water (water vapor) are mixed, or hydrogen and oxygen are mixed. good.

  When the single crystal silicon wafer 10 is maintained at a temperature of about 1100 ° C. to 1200 ° C. in the heating furnace, a portion of the surface of the single crystal silicon wafer 10 covered with the silicon nitride film 30 and the polybuffer silicon film 70, That is, the element region is shielded by the silicon nitride film 30 and the polybuffer silicon film 70 and does not come into contact with the atmosphere in the heating furnace, so that it is not oxidized. The portion not covered with the buffer silicon film 70, that is, the element isolation region is oxidized to come into contact with the atmosphere in the heating furnace, and field oxide films 63 and 64 are formed.

  Oxygen that has entered the inside of the single crystal silicon wafer 10 corresponding to the element isolation region from the atmosphere of the heating furnace also diffuses in the plane direction of the single crystal silicon wafer 10. Therefore, the end portions of the field oxide films 63 and 64 grow in the direction of the surface of the single crystal silicon wafer 10 so as to sink under the silicon nitride film 30 and the polybuffer silicon film 70, and bird's beak portions 63a and 63a and bird's beak portions 64a. -64a is formed respectively.

At this time, oxidation promoting ions are implanted into the high breakdown voltage element isolation region (the element isolation region on the left side in FIG. 29) and the portion adjacent to the high breakdown voltage element isolation region in the element region in the second step (S2002). Therefore, the bird's beak parts 63a and 63a of the field oxide film 63 formed in the high breakdown voltage element isolation region are more than the bird's beak parts 64a and 64a of the field oxide film 64 formed in the high density element isolation region. Growth in the surface direction is further promoted and lengthened (L3> L4).
As a result, a field oxide film 63 having a relatively long bird's beak length is formed in the high breakdown voltage element isolation region where a high breakdown voltage is required, and a high breakdown voltage is not required but an integration of adjacent element regions is required. A field oxide film 64 having a relatively short bird's beak length and a small protrusion amount to an adjacent element region is formed in the density element isolation region.
In this way, by selectively injecting oxidation promoting ions into a predetermined position (high breakdown voltage element isolation region) in the element isolation region on the surface of the single crystal silicon wafer 10 subjected to the thermal oxidation treatment only once, Field oxide film 63 having a different bird's beak length (and hence a different breakdown voltage and influence on integration of adjacent element regions) even though the heat treatment is performed under the same conditions (heat treatment temperature, heat treatment time, and atmosphere). -64 can be formed.

  In the case of the present embodiment, in the ion implantation step (S2070), the amount of oxidation-promoting ions implanted into the high-breakdown-voltage element region and the portion adjacent to the high-breakdown-voltage element isolation region in the element region is the implantation time by the ion implantation apparatus It can be easily adjusted by adjusting the ionization voltage or the like. Therefore, the bird's beak length L3 of the field oxide film 63 can be accurately adjusted by adjusting the implantation amount of the oxidation promoting ions.

  When the field oxide film formation step (S2090) is completed, the process proceeds to the final removal step (S2100).

As shown in FIG. 31, the final removal step (S2100) is a step of removing the silicon nitride film 30, the poly buffer silicon film 70, and the buffer oxide film 20 on the surface of the single crystal silicon wafer 10.
In the final removal step (S1100), the silicon nitride film 30 on the surface of the single crystal silicon wafer 10 is first removed by wet etching using hot phosphoric acid, and then the polybuffer silicon film 70 and the buffered hydrofluoric acid are used. The buffer oxide film 20 is removed.
In this embodiment, the silicon nitride film 30, the polybuffer silicon film 70, and the buffer oxide film 20 are removed using hot phosphoric acid and buffered hydrofluoric acid. However, the present invention is not limited to this, and an antioxidant film, The polybuffer silicon film and the buffer oxide film may be removed by other methods.

  When the final removal step (S2100) is finished, the third step (S2003) is finished.

  As described above, the third step (S2003) is a step of subjecting the single crystal silicon wafer 10 to a predetermined thermal oxidation process and forming field oxide films 63 and 64 in the element isolation region on the surface of the single crystal silicon wafer 10.

  After the completion of the third step (S2003), a power semiconductor element (semiconductor element that handles high voltage) such as LDMOS is formed in the element region adjacent to the high breakdown voltage element isolation region on the surface of the single crystal silicon wafer 10, In the element region adjacent to the high-density element isolation region on the surface of the single crystal silicon wafer 10, for example, semiconductor elements such as CMOS are required to be integrated, and wiring between these semiconductor elements is applied to the semiconductor. The device is completed.

As described above, the second embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A first step (S2001) of forming a silicon nitride film 30 on the element region on the surface of the single crystal silicon wafer 10 (strictly speaking, sandwiching the buffer oxide film 20 and the polybuffer silicon film 70);
A second step (S2002) of implanting oxidation-promoting ions into a predetermined position of the element isolation region on the surface of the single crystal silicon wafer 10 (in this embodiment, a high breakdown voltage element isolation region);
A third step (S2003) for subjecting the single crystal silicon wafer 10 to a thermal oxidation treatment;
It comprises.
With this configuration, it is possible to form the field oxide films 63 and 64 having different bird's beak lengths on the surface of the same single crystal silicon wafer 10 by a single thermal oxidation process, which improves the productivity of the semiconductor device. Contributes to improvement and reduction of energy required for production of semiconductor devices.

The second step (S2002) of the second embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A pattern (mask) of the ion implantation photoresist 45 in a shape covering the portion of the element isolation region of the single crystal silicon wafer 10 excluding a predetermined position (in this embodiment, a high density element isolation region) and the silicon nitride film 30. A photolithography process for ion implantation (S2060) for forming a portion 47);
An ion implantation step (S2070) for implanting oxidation-promoting ions into a predetermined position of the element isolation region of the single crystal silicon wafer 10 (in this embodiment, a high breakdown voltage element isolation region);
It comprises.
With this configuration, it is possible to reliably implant oxidation promoting ions only at predetermined positions in the element isolation region, and field oxide films 63 and 64 having different bird's beak lengths are formed on the surface of the single crystal silicon wafer 10. It can be easily and reliably formed.

The second embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
In the ion implantation step (S2070), the oxidation promoting ions are implanted at an angle inclined with respect to the surface of the single crystal silicon wafer 10 (at an angle not orthogonal to the surface of the single crystal silicon wafer 10).
With this configuration, in the ion implantation step (S2070), the oxidation promoting ions are not limited to a predetermined position, that is, not only the high breakdown voltage element isolation region but also a portion adjacent to the high breakdown voltage element isolation region (silicon nitride film 30). (Below the end of the). As a result, in the third step (S2003), more strictly in the field oxide film forming step (S2090), the bird's beak portions 63a and 63a of the field oxide film 63 formed in the element isolation region in the plane direction of the single crystal silicon wafer 10. It is possible to further promote the growth of

The second embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
Oxidation promoting ions contain oxygen ions.
With this configuration, oxygen ions implanted into a predetermined position, that is, the high breakdown voltage element isolation region in the ion implantation step (S2070) are used as elements (raw materials) constituting the field oxide film 63 themselves. This contributes to the promotion of the formation of the field oxide film 63.
As a result, the bird's beak length L3 of the field oxide film 63 is longer than the bird's beak length L4 of the field oxide film 64 formed in the high-density element isolation region where oxygen ions are not implanted.

The second embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
Boron ions are included in the oxidation promoting ions.
With this configuration, boron ions implanted in a predetermined position, that is, in the high breakdown voltage element isolation region in the ion implantation step (S2070) contribute to the promotion of the formation of the field oxide film 63.
As a result, the bird's beak length L3 of the field oxide film 63 is longer than the bird's beak length L4 of the field oxide film 64 formed in the high-density element isolation region where oxygen ions are not implanted.

The first step (S2001) of the second embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A buffer oxide film forming step (S2010) for forming a buffer oxide film 20 on the surface of the silicon single crystal wafer 10;
A polybuffer silicon film forming step (S2015) for forming a polybuffer silicon film 70 on the buffer oxide film 20, and
A silicon nitride film forming step (S2020) for forming the silicon nitride film 30 on the polybuffer silicon film 70;
A photolithography step (S2030) for forming a pattern (mask portion 42) of the photoresist 40 having a shape covering the element region on the silicon nitride film 30;
An etching step (S2040) for removing a portion of the silicon nitride film 30 corresponding to the element isolation region;
A photoresist removal step (S2050) for removing the photoresist 40 (mask portion 42) from the single crystal silicon wafer 10;
It comprises.
With this configuration, the second embodiment of the method for manufacturing a semiconductor device according to the present invention has a working process flow in the middle of the conventional polybuffer LOCOS method shown in FIGS. 44 and 45 (photoresist removal process ( (Between S20500) and the field oxide film forming step (S20600)) with the second step (S2002) sandwiched therebetween.
Therefore, it is possible to easily form field oxide films 63 and 64 having different bird's beak lengths using existing semiconductor manufacturing equipment. In other words, it contributes to the reduction of the introduction cost to the manufacturing site.

  The third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 2 to 6 and FIGS.

  As shown in FIG. 32, the third embodiment of the method of manufacturing a semiconductor device according to the present invention includes a first step (S3001), a second step (S3002), and a third step (S3003).

Hereinafter, the first step (S3001) will be described with reference to FIGS. 2 to 6 and FIGS. 32 to 34. FIG.
As shown in FIG. 32, the first step (S3001) includes a buffer oxide film formation step (S3010), a silicon nitride film formation step (S3020), a photolithography step (S3030), an etching step (S3040), and a photoresist removal step ( S3050).

  As shown in FIGS. 2 to 6, the buffer oxide film forming step (S3010), the silicon nitride film forming step (S3020), and the photolithography step (S3030) are performed in the first embodiment of the semiconductor device manufacturing method according to the present invention. Since this is substantially the same as the buffer oxide film forming step (S1010), the silicon nitride film forming step (S1020), and the photolithography step (S1030), description thereof is omitted.

  When the photolithography process (S3030) is completed, the process proceeds to the etching process (S3040).

As shown in FIG. 34, the etching step (S3040) is a step of removing the portion of the silicon nitride film 30 corresponding to the element isolation region.
In the etching step (S3040), when RIE (Reactive Ion Etching) is performed on the single crystal silicon wafer 10 on which the pattern of the photoresist 40 corresponding to the shape of the mask 50 is formed, the mask portion of the silicon nitride film 30 is masked. The silicon nitride film 30 corresponding to 42 (portion corresponding to the element region) is not removed because it does not contact the etchant, and the remaining portion, that is, the exposed portion of the photosensitive portion 41 is removed (corresponding to the element isolation region). The single-crystal silicon wafer 10 having a predetermined depth (in this embodiment, about 50 nm) below the silicon nitride film 30, the buffer oxide film 20 and the buffer oxide film 20 in contact with the etchant is decomposed and removed.
As a result, a recess 10 a is formed in the element isolation region of the single crystal silicon wafer 10.

  When the etching process (S3040) is completed, the process proceeds to a photoresist removing process (S3050).

  As shown in FIG. 34, the photoresist removing step (S3050) is a step of removing the photoresist 40 (mask portion 42) from the single crystal silicon wafer 10.

  When the photoresist removal step (S3050) is finished, the first step (S3001) is finished. When the first step (S3001) is completed, the process proceeds to the second step (S3002).

Hereinafter, the second step (S3002) will be described with reference to FIG. 32 and FIG. 35 to FIG.
As shown in FIG. 32, the second step (S3002) includes an ion implantation photolithography step (S3060), an ion implantation step (S3070), and an ion implantation photoresist removal step (S3080).
The ion implantation photolithography process (S3060) includes an ion implantation photoresist coating process (S3061) and an ion implantation patterning process (S3062).
As shown in FIGS. 35 to 37, the ion implantation photolithography step (S3060) is substantially the same as the ion implantation photolithography step (S1060) in the first embodiment of the semiconductor device manufacturing method according to the present invention. Description is omitted.

  When the ion implantation photolithography process (S3060) is completed, the process proceeds to the ion implantation process (S3070).

  In the ion implantation photolithography step (S3060), the ion implantation photoresist 45 having a shape covering the element isolation region excluding the high breakdown voltage element region (that is, the high density element isolation region) and the silicon nitride film 30 is formed. This is a step of forming a pattern (mask part 47).

  As shown in FIG. 38, the ion implantation step (S3070) is a step of implanting oxidation promoting ions into the high breakdown voltage element isolation region (“predetermined position of the element isolation region” in this embodiment).

  In the ion implantation step (S3070), oxidation promoting ions are implanted into the single crystal silicon wafer 10 accommodated in the ion implantation apparatus. In addition, although the ion implantation apparatus of a present Example is an exclusive article, it is also possible to use a commercially available ion implantation apparatus. As a specific method of ion implantation, an existing method such as ion shower or plasma doping can be used.

  At this time, the silicon nitride film 30, the buffer oxide film 20, and the single crystal silicon wafer 10 having a predetermined depth are removed from the high voltage element isolation region of the single crystal silicon wafer 10, and the photosensitive portion of the photoresist 45 for ion implantation is removed. Since 46 is also removed, the recess 10a is exposed to the outside, and the oxidation promoting ions reach the inside of the single crystal silicon 10 from the recess 10a.

Since the portion where the photosensitive portion 46 is removed in the pattern of the ion implantation photoresist 45 usually has a predetermined width, the oxidation promoting ions are inclined with respect to the surface (high voltage element isolation region) of the single crystal silicon wafer 10. Injected at an angle. As a result, the oxidation promoting ions reach not only the high breakdown voltage element isolation region but also a portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region.
On the other hand, the silicon nitride film 30 is formed on the element region and the high-density element isolation region of the single crystal silicon wafer 10, and the pattern (mask portion 47) of the photoresist 45 for ion implantation is further formed thereon. Yes. Therefore, except for a portion adjacent to the high breakdown voltage element isolation region in the element region (below the end of the silicon nitride film 30), the oxidation promoting ions are blocked by the silicon nitride film 30 and the ion implantation photoresist 45 to be single crystal. The inside of the silicon 10 cannot be reached.

  In addition, the angle of the oxidation promoting ion implantation angle θ 1, that is, the angle formed by the normal of the surface of the single crystal silicon wafer 10 and the direction of implantation of the oxidation promoting ions is increased, and the angle is more inclined with respect to the surface of the single crystal silicon wafer 10. By implanting the oxidation promoting ions, the oxidation promoting ions can efficiently reach the portion adjacent to the high breakdown voltage element isolation region (below the end portion of the silicon nitride film 30) in the element region.

  When the ion implantation step (S3070) is completed, the process proceeds to a photoresist removal step for ion implantation (S3080).

  As shown in FIG. 39, the ion implantation photoresist removal step (S3080) is a step of removing the remaining ion implantation photoresist 45 (mask portion 47) from the single crystal silicon wafer 10.

  When the photoresist removal process for ion implantation (S3080) is completed, the second process (S3002) is completed. When the second step (S3002) is completed, the process proceeds to the third step (S3003).

  As described above, the second step (S3002) is a step of implanting oxidation promoting ions into the high breakdown voltage element isolation region (“predetermined position of the element isolation region” in this embodiment) on the surface of the single crystal silicon wafer 10. .

Hereinafter, the third step (S3003) will be described with reference to FIGS. 32, 40, and 41.
As shown in FIG. 32, the third step (S3003) includes a field oxide film formation step (S3090) and a final removal step (S3100).

  As shown in FIG. 40, the field oxide film forming step (S3090) is a step of forming field oxide films 65 and 66 in the element isolation region on the surface of the single crystal silicon wafer 10.

In the field oxide film forming step (S3090), the single crystal silicon wafer 10 is accommodated in a heating furnace (not shown) and held at a temperature of about 1100 ° C. to 1200 ° C. for a predetermined time.
In addition, since the holding temperature (heat treatment temperature) of the heating furnace is appropriately selected according to the composition of the atmosphere and other conditions, it is not limited to about 1100 ° C. to 1200 ° C. as in this embodiment.
The composition of the atmosphere in the heating furnace may be the same as that of normal air, but the oxygen concentration is larger than that of the air, oxygen and water (water vapor) are mixed, or hydrogen and oxygen are mixed. good.

  When the single crystal silicon wafer 10 is maintained at a temperature of about 1100 ° C. to 1200 ° C. in the heating furnace, the portion of the surface of the single crystal silicon wafer 10 covered with the silicon nitride film 30, that is, the element region is silicon nitride. Since it is shielded by the film 30 and does not come into contact with the atmosphere in the heating furnace, it is not oxidized, but a portion of the surface of the single crystal silicon wafer 10 that is not covered with the silicon nitride film 30, that is, an element isolation region (recessed portion) 10a) is oxidized to come into contact with the atmosphere in the heating furnace, and field oxide films 65 and 66 are formed.

  Oxygen that has entered the inside of the single crystal silicon wafer 10 corresponding to the element isolation region from the atmosphere of the heating furnace also diffuses in the plane direction of the single crystal silicon wafer 10. Therefore, the end portions of the field oxide films 65 and 66 grow in the surface direction of the single crystal silicon wafer 10 so as to sink under the silicon nitride film 30, and bird's beak portions 65a and 65a and bird's beak portions 66a and 66a are formed. The

At this time, oxidation promoting ions are implanted into the high breakdown voltage element isolation region (the element isolation region on the left side in FIG. 39) and the portion adjacent to the high breakdown voltage element isolation region in the element region in the second step (S3002). Therefore, the bird's beak portions 65a and 65a of the field oxide film 65 formed in the high breakdown voltage element isolation region are more than the bird's beak portions 66a and 66a of the field oxide film 66 formed in the high density element isolation region. Growth in the surface direction is further promoted and lengthened (L5> L6).
As a result, a field oxide film 65 having a relatively long bird's beak length is formed in the high breakdown voltage element isolation region where a high breakdown voltage is required, and a high breakdown voltage is not required but an integration of adjacent element regions is required. In the density element isolation region, a field oxide film 66 having a relatively short bird's beak length and a small protrusion amount to an adjacent element region is formed.
In this way, by selectively injecting oxidation promoting ions into a predetermined position (high breakdown voltage element isolation region) in the element isolation region on the surface of the single crystal silicon wafer 10 subjected to the thermal oxidation treatment only once, Field oxide film 65 having a different bird's beak length (and thus a different breakdown voltage and influence on integration of adjacent element regions) despite the fact that the heat treatment is performed under the same conditions (heat treatment temperature, heat treatment time, atmosphere). 66 can be formed.

  In the case of this embodiment, the amount of oxidation promoting ions implanted into the high breakdown voltage element region and the portion adjacent to the high breakdown voltage element isolation region in the ion implantation step (S3070) is determined by the implantation time of the ion implantation apparatus. It can be easily adjusted by adjusting the ionization voltage or the like. Therefore, the bird's beak length L5 of the field oxide film 65 can be accurately adjusted by adjusting the implantation amount of the oxidation promoting ions.

  When the field oxide film formation step (S3090) is completed, the process proceeds to the final removal step (S3100).

As shown in FIG. 41, the final removal step (S3100) is a step of removing the silicon nitride film 30 and the buffer oxide film 20 on the surface of the single crystal silicon wafer 10.
In the final removal step (S1100), first, the silicon nitride film 30 on the surface of the single crystal silicon wafer 10 is removed by wet etching using hot phosphoric acid, and then the buffer oxide film 20 is removed using buffered hydrofluoric acid or the like. Is done.
In this embodiment, the silicon nitride film 30 and the buffer oxide film 20 are removed using hot phosphoric acid and buffered hydrofluoric acid. However, the present invention is not limited to this, and an antioxidant film, a polybuffer silicon film, and a buffer are used. The oxide film may be removed by other methods.

  When the final removal step (S3100) is finished, the third step (S3003) is finished.

  As described above, the third step (S3003) is a step of subjecting the single crystal silicon wafer 10 to a predetermined thermal oxidation process to form field oxide films 65 and 66 in the element isolation region on the surface of the single crystal silicon wafer 10.

  After the completion of the third step (S3003), a power semiconductor element (semiconductor element that handles high voltage) such as LDMOS is formed in the element region adjacent to the high breakdown voltage element isolation region on the surface of the single crystal silicon wafer 10, In the element region adjacent to the high-density element isolation region on the surface of the single crystal silicon wafer 10, for example, semiconductor elements such as CMOS are required to be integrated, and wiring between these semiconductor elements is applied to the semiconductor. The device is completed.

As described above, the third embodiment of the semiconductor device manufacturing method according to the present invention is
A first step (S3001) of forming a silicon nitride film 30 on the element region on the surface of the single crystal silicon wafer 10 (strictly speaking, sandwiching the buffer oxide film 20);
A second step (S3002) of implanting oxidation-promoting ions into a predetermined position of the element isolation region on the surface of the single crystal silicon wafer 10 (in the case of this embodiment, the high breakdown voltage element isolation region);
A third step (S3003) for subjecting the single crystal silicon wafer 10 to a thermal oxidation treatment;
It comprises.
With this configuration, it is possible to form the field oxide films 65 and 66 having different bird's beak lengths on the surface of the same single crystal silicon wafer 10 by one thermal oxidation process, which improves the productivity of the semiconductor device. Contributes to improvement and reduction of energy required for production of semiconductor devices.

The second step (S3002) of the third embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A pattern (mask) of the ion implantation photoresist 45 in a shape covering the portion of the element isolation region of the single crystal silicon wafer 10 excluding a predetermined position (in this embodiment, a high density element isolation region) and the silicon nitride film 30. A photolithography process for ion implantation (S3060) for forming a portion 47);
An ion implantation step (S3070) for implanting oxidation-promoting ions into a predetermined position of the element isolation region of the single crystal silicon wafer 10 (in this embodiment, a high breakdown voltage element isolation region);
It comprises.
With this configuration, it is possible to reliably implant oxidation promoting ions only at predetermined positions in the element isolation region, and field oxide films 65 and 66 having different bird's beak lengths are formed on the surface of the single crystal silicon wafer 10. It can be easily and reliably formed.

The third embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows:
In the ion implantation step (S3070), the oxidation promoting ions are implanted at an angle inclined with respect to the surface of the single crystal silicon wafer 10 (at an angle not orthogonal to the surface of the single crystal silicon wafer 10).
With this configuration, in the ion implantation step (S3070), the oxidation promoting ions are not limited to a predetermined position, that is, not only the high breakdown voltage element isolation region but also a portion adjacent to the high breakdown voltage element isolation region (silicon nitride film 30). (Below the end of the). As a result, in the third step (S3003), more specifically, in the field oxide film forming step (S3090), the bird's beak portions 65a and 65a of the field oxide film 65 formed in the element isolation region are directed in the plane direction of the single crystal silicon wafer 10. It is possible to further promote the growth of

The third embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows:
Oxidation promoting ions contain oxygen ions.
With this configuration, oxygen ions implanted into a predetermined position, that is, the high breakdown voltage element isolation region in the ion implantation step (S3070) are used as elements (raw materials) constituting the field oxide film 65 by themselves. This contributes to the promotion of the formation of the field oxide film 65.
As a result, the bird's beak length L5 of the field oxide film 65 becomes longer than the bird's beak length L6 of the field oxide film 66 formed in the high-density element isolation region where oxygen ions are not implanted.

The third embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows:
Boron ions are included in the oxidation promoting ions.
With this configuration, boron ions implanted in a predetermined position, that is, in the high breakdown voltage element isolation region in the ion implantation step (S3070) contribute to the promotion of the formation of the field oxide film 65.
As a result, the bird's beak length L5 of the field oxide film 65 becomes longer than the bird's beak length L6 of the field oxide film 66 formed in the high-density element isolation region where oxygen ions are not implanted.

The first step (S3001) of the third embodiment of the method for manufacturing a semiconductor device according to the present invention is as follows.
A buffer oxide film forming step (S3010) for forming a buffer oxide film 20 on the surface of the silicon single crystal wafer 10;
Forming a silicon nitride film 30 on the buffer oxide film 20 (S3020);
A photolithography step (S3030) for forming a pattern (mask portion 42) of a photoresist 40 having a shape covering the element region on the silicon nitride film 30;
An etching step (S3040) for removing a portion of the silicon nitride film 30 corresponding to the element isolation region;
A photoresist removal step (S3050) for removing the photoresist 40 (mask portion 42) from the single crystal silicon wafer 10;
It comprises.
With this configuration, the third embodiment of the method for manufacturing a semiconductor device according to the present invention has a working process flow in the middle of the conventional R-LOCOS method shown in FIGS. (Between S30500) and the field oxide film forming step (S30600)) with the second step (S3002) sandwiched therebetween.
Therefore, it is possible to easily form field oxide films 65 and 66 having different bird's beak lengths using existing semiconductor manufacturing equipment. In other words, it contributes to the reduction of the introduction cost to the manufacturing site.

Furthermore, the third embodiment of the method of manufacturing a semiconductor device according to the present invention is
In the etching step (S3040), a portion of the silicon nitride film 30 corresponding to the element isolation region and the silicon single crystal wafer 10 having a predetermined depth below the silicon nitride film 10 are removed.
With this configuration, it is possible to promote the growth of the bird's beak portions 65a and 65a in the plane direction of the silicon single crystal wafer 10 in the field oxide film 65 having a shape deeply embedded in the single crystal silicon wafer 10. It is.

In addition, the semiconductor device manufactured by the first embodiment, the second embodiment, and the third embodiment of the semiconductor device manufacturing method according to the present invention,
A first step (S1001, S2001, S3001) of forming a silicon nitride film 30 on the element region on the surface of the silicon single crystal wafer 10,
A second step (S1002, S2002, S3002) of implanting oxidation promoting ions into a predetermined position of the element isolation region on the surface of the silicon single crystal wafer 10,
Third oxidation is performed on the silicon single crystal wafer 10 to form field oxide films 61 and 62, field oxide films 63 and 64, and field oxide films 65 and 66 in the element isolation region on the surface of the silicon single crystal wafer 10, respectively. Process (S1003, S2003, S3003);
It is manufactured through.
With this configuration, field oxide films 61 and 62, field oxide films 63 and 64, and field oxide films 65 and 66 having different bird's beak lengths are formed on the surface of the same single crystal silicon wafer 10 by a single thermal oxidation process. Therefore, it is possible to reduce the energy required for production.

The figure which shows the flow of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the buffer oxide film formation process of 1st Example, 2nd Example, and 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the silicon nitride film formation process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention, and a 3rd Example. The cross-sectional schematic diagram which shows the photoresist application process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention, and a 3rd Example. The cross-sectional schematic diagram which shows the exposure process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention, and a 3rd Example. The cross-sectional schematic diagram which shows the image development process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention, and a 3rd Example. The cross-sectional schematic diagram which shows the etching process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention, and a 3rd Example. The cross-sectional schematic diagram which shows the photoresist removal process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist application | coating process for ion implantation of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the exposure process for ion implantation of the 1st Example of the manufacturing method of the semiconductor device concerning this invention. The cross-sectional schematic diagram which shows the image development process for the ion implantation of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the ion implantation process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist removal process for ion implantation of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the field oxide film formation process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the final removal process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows another embodiment of the ion implantation process of the 1st Example of the manufacturing method of the semiconductor device which concerns on this invention. The figure which shows the flow of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the poly buffer silicon film formation process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the silicon nitride film formation process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist application | coating process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the exposure process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the image development process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the etching process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist removal process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist application | coating process for ion implantation of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the exposure process for ion implantation of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the image development process for ion implantation of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the ion implantation process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist removal process for ion implantation of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the field oxide film formation process of 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the final removal process of the 2nd Example of the manufacturing method of the semiconductor device which concerns on this invention. The figure which shows the flow of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the etching process of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist removal process of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist application | coating process for ion implantation of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the exposure process for ion implantation of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the image development process for ion implantation of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the ion implantation process of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the photoresist removal process for ion implantation of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the field oxide film formation process of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The cross-sectional schematic diagram which shows the final removal process of the 3rd Example of the manufacturing method of the semiconductor device which concerns on this invention. The figure which shows the flow of the manufacturing method (conventional LOCOS method) of the conventional semiconductor device. Schematic diagram showing a conventional method for manufacturing a semiconductor device (conventional LOCOS method). The figure which shows the flow of the manufacturing method (conventional polybuffer LOCOS method) of the conventional semiconductor device. FIG. 6 is a schematic diagram showing a conventional method for manufacturing a semiconductor device (conventional polybuffer LOCOS method). The figure which shows the flow of the manufacturing method (conventional R-LOCOS method) of the conventional semiconductor device. The schematic diagram which shows the manufacturing method (conventional R-LOCOS method) of the conventional semiconductor device.

Explanation of symbols

10 Single crystal silicon wafer (silicon substrate)
20 Buffer oxide film 30 Silicon nitride film (antioxidation film)
61 Field oxide film 62 Field oxide film

Claims (9)

A first step of forming an antioxidant film on the element region of the surface of the silicon substrate;
A second step of implanting oxidation promoting ions at a predetermined position of the element isolation region on the surface of the silicon substrate;
A third step of performing a thermal oxidation process on the silicon substrate and forming a field oxide film in an element isolation region on the surface of the silicon substrate;
A method for manufacturing a semiconductor device comprising: The second step includes
A photolithography process for ion implantation for forming a pattern of a photoresist for ion implantation having a shape covering the portion of the element isolation region excluding the predetermined position and the antioxidant film;
An ion implantation step of implanting oxidation promoting ions at a predetermined position of the element isolation region;
A method of manufacturing a semiconductor device according to claim 1. In the second step,
The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation promoting ions are implanted at an angle inclined with respect to a surface of the silicon substrate.   The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation promoting ions include oxygen ions.   The method for manufacturing a semiconductor device according to claim 1, wherein boron ions are included in the oxidation promoting ions. The first step includes
A buffer oxide film forming step of forming a buffer oxide film on the surface of the silicon substrate;
An antioxidant film forming step of forming the antioxidant film on the buffer oxide film;
A photolithography step of forming a photoresist pattern in a shape covering the element region on the antioxidant film;
An etching step of removing a portion of the antioxidant film corresponding to the element isolation region;
A photoresist removal step of removing the photoresist from the silicon substrate;
The manufacturing method of the semiconductor device as described in any one of Claim 1-5 which comprises these.   The method of manufacturing a semiconductor device according to claim 6, wherein in the etching step, a portion of the antioxidant film corresponding to the element isolation region and a silicon substrate having a predetermined depth below the antioxidant film are removed. The first step includes
A buffer oxide film forming step of forming a buffer oxide film on the surface of the silicon substrate;
A polybuffer silicon film forming step of forming a polybuffer silicon film on the buffer oxide film;
An antioxidant film forming step of forming the antioxidant film on the polybuffer silicon film;
A photolithography step of forming a photoresist pattern in a shape covering the element region on the antioxidant film;
An etching step of removing a portion of the antioxidant film corresponding to the element isolation region;
A photoresist removal step of removing the photoresist from the silicon substrate;
The manufacturing method of the semiconductor device as described in any one of Claim 1-5 which comprises these. A first step of forming an antioxidant film on the element region on the surface of the silicon substrate;
A second step of implanting oxidation promoting ions at a predetermined position of the element isolation region on the surface of the silicon substrate;
Applying a thermal oxidation process to the silicon substrate, and forming a field oxide film in an element isolation region on the surface of the silicon substrate;
A semiconductor device manufactured through the process.

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