JPS63117467A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form more than one region having different impurity concentration on a substrate in a single doping process by a method wherein masks having different effects against doping are formed on the substrate and the impurity is injected into the whole surface from above the mask. CONSTITUTION:A pad oxide film 33 is formed on the surface of a silicon substrate 31 after the silicon substrate 31 acting as a base has been processed by a thermal oxidation method. Then, a silicon nitride film 35 is formed on this pad oxide film 33 by a CVD method. A channel stopper region 39 and an active region 40 can be formed during an identical impurity-injecting process, and, at the same time, the impurity concentration at each region can be set to the respective desired impurity concentration.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device in which a large number of semiconductor elements, such as TfMO3FETs, are integrated, and in particular, it relates to a method for manufacturing a semiconductor device in which a large number of semiconductor elements, such as TfMO3FETs, are integrated. The present invention relates to a method in which regions having different resistivities, such as isolation regions and active regions of this FET, can be formed in the same impurity introduction step.

(Prior Art) A semiconductor device such as an IC memory, which is formed by integrating a large number of MOSFETs (metal oxide field effect transistors) on a single silicon substrate, is one of the electronic components that will become increasingly important in the future. In the manufacturing process of such semiconductor devices, element isolation regions (
It was necessary to form a channel stopper (channel stopper) and take measures to set the operating threshold voltage of this FET to a predetermined value.

The formation of the element isolation region and the control of the threshold voltage have generally been performed by introducing impurities into regions of the silicon substrate corresponding to the element isolation region and the active region to a predetermined concentration. Diffusion and ion implantation have been used to introduce this impurity.

Conventional semiconductor device manufacturing methods including such an impurity introduction step include, for example, the literature (Nikkei McGraw-Hill Co., Ltd. rM
There is one disclosed in O5LSI Manufacturing Technology JP, 29-31).

FIGS. 4A to 4E are manufacturing process diagrams mainly showing the above-mentioned ion implantation process in the conventional MOS process technology disclosed in this document. Note that these figures are cross-sectional views that focus on one FET and its surrounding area and show the wafer state of the surrounding area including this FET according to the progress of manufacturing the semiconductor device.

On the silicon substrate 11, the underlying 5in2 film 13 and Si3N
4 films 15 are sequentially formed from the substrate side (FIG. 4(A)
reference).

Next, a photoresist film is formed on the S i 3N4 B115. Thereafter, this photoresist film is patterned so that a region corresponding to the FET formation region (active region) of the silicon substrate 11 remains. Next, using this remaining resist 17 as a mask, the Si that is not covered with the resist mask 17 is etched by dry etching.
A partial region of the 3N4 film 15 is removed to obtain a remaining portion 15a of the Si3N4 film.

Furthermore, using this resist 17 as a mask, ions of boron (B), for example, are implanted in order to introduce impurities into a partial region of the silicon substrate 11 around the region where the FET is to be formed (see FIG. 4(B)). This ion implantation condition is F
It is set appropriately so that the ETs are electrically insulated and ions are not diffused into the FET formation region. In this step, a channel stop region 19 is obtained.

Next, a wet oxidation method using water vapor is used to oxidize a partial region of the silicon substrate that is not covered with the remaining portion 15a of the Si3N4 film, thereby obtaining a field SiO□ film 21. At this time, 5in2 invades the edge of the Si3N4 film 15a,
A so-called bird's peak is formed (Figure 4 (C)
reference).

Next, Si3N, the remaining portion 15a of the film, and the underlayer 5i02 film 13 are removed. Thereafter, a new oxidation process is performed on the FET formation region of the silicon substrate exposed by this removal to form a gate s i02 B23. Next, a second ion implantation of boron, for example, is performed to introduce impurities into the partial region 20 of the silicon substrate including the region corresponding to the channel region of the FET (
(See Figure 4(D)). The second ion implantation conditions are different from the implantation conditions for forming the channel stop region, and are set appropriately so that the threshold voltage vT of the FET becomes a predetermined value.

Next, the silicon substrate 1 is heated by thermal decomposition of SiH4 gas, etc.
Polycrystalline Si is formed on the first FET formation region. next,
This polycrystalline Si is patterned so that it remains on the area where the gate is to be formed. Using the gate 25 made of polycrystalline Si as a mask, ions of, for example, arsenic (As) are implanted into the region 27 of the silicon substrate 11 where the drain and source are to be formed (see FIG. 4(E)).

Next, although not shown, the S
An igegen nMOS transistor is obtained.

As mentioned above, in the conventional method, ion implantation for forming a channel stop region and ion implantation for controlling the threshold voltage of an FET are performed, even though the same material, such as boron, is used for ion implantation. was conducted separately.

(Problems to be Solved by the Invention) However, the conventional method of manufacturing a semiconductor device in which ion implantation is performed twice as described above has the problem that the process is long and complicated.

This causes problems such as longer manufacturing time and higher manufacturing costs.

An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a semiconductor device that can form a plurality of regions with different resistivities in a base such as a silicon substrate by -times of ion implantation. be.

(Means for solving the problem) In order to achieve this object, according to the method of manufacturing a semiconductor device of the present invention, when forming a plurality of regions having different resistivities by introducing impurities into the base, the above-mentioned The method is characterized in that masks having different impurity introduction blocking effects are formed on the base, and the impurity is introduced into the entire base from above the mask.

In carrying out the present invention, the base described above can be a silicon substrate, and the plurality of regions described above can be used, for example, as regions for electrically isolating semiconductor elements such as FETs, and active regions of FETs.

Furthermore, as the above-mentioned masks having different impurity introduction blocking effects, the above-mentioned mask on the active region is a silicon oxide film and a silicon nitride film, which are sequentially provided from the underlying side, and the above-mentioned mask on the element isolation region is a silicon oxide film and a silicon nitride film. It is preferable to do so.

(Function) According to such a method, impurities are also introduced into the active region, for example, in the step of introducing impurities into the element isolation region. Moreover, since there are mask layers having different impurity introduction blocking effects on each region, the amount of impurities introduced through these masks differs in each region.

Therefore, for example, impurities can be introduced into the element isolation region at a concentration that enables electrical isolation between elements, and at the same time, for example, the active region can be introduced at a concentration such that the threshold voltage of the FET exhibits a desired voltage value. Impurities can be introduced into the concentration.

(Example) An example of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. It should be noted that these figures are only schematic representations to the extent that the present invention can be understood, and the dimensions, shapes, and arrangement relationships of each component are not limited to the illustrated examples.

The following embodiment will be explained using an example of manufacturing a semiconductor device having a large number of MOSFETs on a substrate, but it is clear that the semiconductor device suitable for using the manufacturing method of the present invention is not limited to this embodiment. It is. Further, in the manufacturing method of the present invention, when forming a plurality of regions having different resistivities on a base, the formation is performed in the same impurity introduction step. Therefore, for example, steps other than the above-mentioned impurity introduction step in the manufacturing process of a semiconductor device are not limited to the following embodiments, and it is clear that other methods can be used.

Solution: 101 Examples FIGS. 1A to 1D are manufacturing process diagrams mainly showing the impurity introduction process according to the method of manufacturing a semiconductor device of the present invention. Note that these figures focus on one FET and its surrounding area, and the FET is
FIG. 3 is a cross-sectional view showing the state of the wafer in the peripheral portion including ET.

First, a thermal oxidation process is performed on, for example, a silicon substrate 31 as a base to form an underlying silicon oxide film 33 (sometimes referred to as a pad oxide film 33) on the surface of the silicon substrate 31. Next, a silicon nitride film 35 is formed on this pad oxide film 33 by the CVD method (see FIG.
See A).

Next, although not shown, a photoresist film is formed on the silicon nitride film 35. Thereafter, this photoresist film is patterned so that a region of the photoresist film corresponding to the FET formation region (active region) of the silicon substrate 31 remains. Next, using this remaining resist as a mask, the partial region of the silicon nitriding chamber 35 not covered by this resist mask is removed by a conventionally known suitable method to obtain a remaining portion 35a of the Si3N4 film.

Subsequently, the resist on this remaining portion 35a is removed.

This remaining portion 35a becomes part of a mask when introducing impurities and forming a field oxide film (see FIG. 1(B)).

In this embodiment, the thickness of the pad oxide film 33 is approximately 3
00 people, and the film thickness of silicon nitride 11i35 is about 100.
There are 0 people.

Next, the remaining portion 35a of the Si3N4 film and the pad oxide film 3 are
Impurities are introduced into the entire silicon substrate 31 from above. In this embodiment, this impurity introduction is performed by ion implantation. Further, the impurity can be selected appropriately depending on the conductivity type of the semiconductor device. For example nM
In the case of O3 Si gate process, boron (B) can be used as an impurity. Therefore, in this case,
The channel stop formation region (region indicated by S in FIG. 1(B)) is provided through the pad oxide film, while the active region (region indicated by P in FIG. 1(B)) is provided through the pad oxide film. is Si3
Boron (B) is added in the same process through the N, film and pad oxide film.
) ion implantation is performed (see FIG. 1(B)).

By the way, when introducing impurities into a substrate by ion implantation, the position (depth from the substrate surface) where the impurity concentration in the substrate peaks due to the acceleration energy of the ions.
is determined. FIG. 2 is a characteristic curve diagram schematically showing the impurity concentration distribution in the depth direction of the substrate, with the vertical axis representing the impurity concentration and the horizontal axis representing the depth from the substrate surface.

Here, in FIG. 2, the thickness of the pad oxide film 33 is set to 1
, and the thickness of the silicon nitride film 35 is denoted by t2, the peak value of the impurity concentration in the channel stop region of the silicon substrate is as indicated by C0 in FIG. On the other hand, in the active region of the silicon substrate, 1. +1
Since there is a mask with a film thickness of 2=13, the peak value of the impurity concentration in this region is indicated by 02 in FIG. In reality, the impurity profile differs somewhat from that shown in FIG. 2 depending on the substrate material and the like. For example, since the penetration of impurities in a silicon nitride film is smaller than that in silicon, the difference between CI and C2 is larger than that shown in FIG. 2. However, the principle of creating a difference in impurity concentration in each region in the same impurity process according to the present invention can be schematically explained with reference to FIG.

As described above, according to the present invention, the channel stop region 39 and the active region 40 can be formed in the same impurity introduction step, and the impurity concentration of each region can be set to a desired impurity concentration.

After the impurity introduction process is completed, a silicon nitride film (313
Using the remaining portion 35a of N4) as a mask, the exposed silicon substrate is oxidized using a conventionally known method to form a field oxide film 37 (FIG. 1(C)).

In this example, the thickness of the field oxide film is approximately 600 mm.
The number was set to 0.

Next, the remaining portion 35a of the silicon nitride film and the remaining portion of the pad oxide film are removed. Next, after the gate oxide film is formed, the source and drain are formed without introducing impurities into the active region, which is conventionally done, in order to control the threshold voltage of the transistor, as already explained using FIG. 4(E). Run a process like Since these processes are conventionally known, their explanation will be omitted.

FIG. 1(D) is a cross-sectional view schematically showing the formed nMO3(7)Si gate.

In FIG. 1(D), 41 indicates a gate oxide film;
3 indicates, for example, n1 polysilicon which becomes the gate electrode,
Reference numerals 45 and 47 respectively indicate source and drain electrode formation regions into which arsenic, for example, is introduced to form an n+ layer. Further, 39 indicates the channel stop region already explained, and 5
1 indicates a region into which impurities are introduced for the purpose of controlling the threshold voltage of the transistor.

Here, an example of an experiment will be explained.

The silicon substrate used in the experiment had a boron (B) concentration of 4
It was made of X1015/Cm3. In addition, the boron ion implantation conditions were set such that the ion acceleration energy was 30 eV.
The ion dose was set to 5xto'' ions/Cm2.

Under these conditions, the peak value of the impurity concentration in the region indicated by 51 in FIG. 1(D) corresponding to the gate electrode of the active region (the value corresponding to C2 in FIG. 2) is approximately 7×101
6/cm3, and the threshold voltage (VT) of the transistor at this time was set to about 0.7V.

In the case of conventional manufacturing and methods, in order to set VT to 0.7V, boron is applied to the corresponding area of the active region to a thickness of approximately 1×10”7cm.
It was necessary to implant ions at a dose of 2. However, according to the manufacturing method of the present invention, such V
The ion implantation process for ion control becomes completely unnecessary.

FIG. 3 is a sectional view showing a wafer with a modified mask for explaining the second embodiment of the invention.

In order to prevent the so-called bird's beak caused by the field oxide film entering the active region,
Special masks may be used. Even when such a mask is used, the manufacturing method of the present invention can be used.

After sequentially forming a pad oxide film and a silicon nitride film on a silicon substrate 31, a mask 3 is formed using a part of the silicon nitride film.
5a (see FIG. 1(B)). Next, using this mask 35a, the pad oxide film exposed from the mask 35a is removed to form a pad oxide film mask 33a (
(See FIG. 3) Next, a silicon nitride film is formed on the entire surface of the substrate 31 including the mask 35a, and then this silicon nitride film is removed by anisotropic etching. As a result of this anisotropic etching, sidewalls 61 can be formed on the sides of the masks 33a and 35a.

Even when a mask having such a sidewall 61 is used, impurities can be introduced into the channel stop region and the active region by the method and reason already explained using FIGS. 1 and 2. I can do it.

It is clear that the present invention is not limited to the above-described embodiments.

For example, in the above embodiment, impurities are introduced into two regions, the channel stop region and the active region, in the same process, but three or more regions are doped with impurities in the same process. You can also do that. In this case, masks having different impurity introduction blocking effects can be provided in each region.

Furthermore, masks with different impurity introduction blocking effects are not limited to the examples mentioned above, but include masks made of the same material with different film thicknesses, masks made of different materials, masks made of stacked layers of different materials, and masks made of the same material with different film thicknesses. It may be a combination or the like.

Further, the method of introducing impurities is not limited to ion implantation, but a diffusion method can also be used. for example,
A cylindrical horizontal diffusion furnace made of quartz glass and surrounded by a heat source such as an electric heater or a halogen lamp is used, and a substrate equipped with the above-mentioned masks having different impurity introduction prevention effects is placed in the diffusion furnace. . When a gas serving as a diffusion source is introduced into this diffusion furnace, desired impurities are introduced into the substrate through this mask. As the gas, if boron is introduced, for example, B2O3 vapor can be used. In addition, in the case of introducing phosphorus, for example, p
2o, steam can be used.

Furthermore, it is clear that the numerical conditions such as the film thickness, the underlying material, etc. explained in the above embodiments can be changed depending on the design of the semiconductor device. For example, the base may be composed of a substrate and a crystal-grown semiconductor layer.

(Effects of the Invention) As is clear from the above description, according to the impurity introduction method according to the semiconductor device manufacturing method of the present invention, a plurality of regions exhibiting mutually different impurity concentrations are formed in the impurity introduction step - times. It can be formed on the base.

Therefore, for example, the formation of a channel stop region and the introduction of impurities for controlling the operating threshold voltage of a transistor, which were previously performed separately, can be performed at once.

Therefore, the process can be simplified, and therefore,
It is possible to shorten the manufacturing time and reduce the manufacturing cost of the semiconductor device.

[Brief explanation of the drawing]

1(A) to (D) are manufacturing process diagrams mainly showing the impurity introduction step for explaining the method of manufacturing a semiconductor device of the present invention. FIG. 2 is a manufacturing process diagram of the method of manufacturing a semiconductor device of the present invention. A characteristic curve diagram showing the distribution of the impurity concentration of the base after impurity introduction is provided for explanation. FIG. 3 is an explanatory diagram of the second embodiment of the method for manufacturing a semiconductor device of the present invention. E) is a manufacturing process diagram mainly showing a conventional impurity introduction process to explain a method for manufacturing a semiconductor device. 31-... Base (silicon substrate) 33-... Silicon oxide M (pad oxide film) 35...
Silicon nitride film 35a---Silicon nitride film mask 37---Field oxide film 39---Element isolation region (channel stop) 40---
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Claims (5)

[Claims] (1) When manufacturing a semiconductor device by forming a plurality of regions with different resistivities by introducing impurities into a base, a mask having different impurity introduction blocking effects is formed on the base, and the base is formed from above the mask. A method of manufacturing a semiconductor device, characterized in that the impurity is introduced into the entire semiconductor device. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of regions are used as a semiconductor element isolation region and an active region. (3) A method of manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor device is a MOSFET integrated circuit. (4) The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the base is a silicon substrate. (5) The masks having different impurity introduction blocking effects include a silicon oxide film and a silicon nitride film provided sequentially from the underlying side for the mask on the active region, and a silicon oxide film and a silicon nitride film for the mask on the element isolation region. A method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: