KR0167253B1 - Manufacture of a semiconductor device - Google Patents

Manufacture of a semiconductor device Download PDF

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Publication number
KR0167253B1
KR0167253B1 KR1019950024980A KR19950024980A KR0167253B1 KR 0167253 B1 KR0167253 B1 KR 0167253B1 KR 1019950024980 A KR1019950024980 A KR 1019950024980A KR 19950024980 A KR19950024980 A KR 19950024980A KR 0167253 B1 KR0167253 B1 KR 0167253B1
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South Korea
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insulating film
forming
film pattern
region
semiconductor device
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KR1019950024980A
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Korean (ko)
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KR970013190A (en
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김영관
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 활성영역과 소자격리영역이 정의된 반도체 기판 상의 소자격리영역에 절연막 패턴을 형성하는 공정과; 상기 절연막 패턴을 포함한 기판에 산소 이온주입 후 상기 절연막 패턴을 제거하는 공정과; 열처리를 통하여 산소 이온주입영역에 격리막을 형성하는 공정 및; 활성영역에 트랜지스터를 형성하는 공정을 구비하여 소자 제조를 완료하므로서, 1) 공정 단순화를 기할 수 있을 뿐 아니라 이로 인해 공정 단가를 낮출 수 있게 되어 벌크 웨이퍼에 비해 가격면에서 차이가 커 양산공정에 적용하지 못했던 SOI 웨이퍼를 양산공정에 유리하게 적용할 수 있게 된다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an insulating film pattern in an isolation region on a semiconductor substrate in which an active region and an isolation region are defined; remind                 Removing the insulating film pattern after implanting oxygen ions into the substrate including the insulating film pattern; Forming a separator in the oxygen ion implantation region through heat treatment;                 Comprising the process of forming a transistor in the active region to complete the device manufacturing, 1) not only can simplify the process but also can reduce the cost of the process                 As a result, the SOI wafer, which was not applied to the mass production process because of the difference in price compared to the bulk wafer, can be advantageously applied to the mass production process.

Description

반도체 소자 제조방법             Semiconductor device manufacturing method         

제1(a)도 및 제1(b)도는 종래 기술에 따른 모스 전계효과트랜지스터의 제조공정을 도시한 공정수순도.1 (a) and 1 (b) are process flowcharts showing a manufacturing process of a MOS field effect transistor according to the prior art.

제2(a)도 내지 제2(g)도는 본 발명에 따른 모스 전계효과트랜지스터의 제조공정을 도시한 공정수순도.2 (a) to 2 (g) are process steps showing the manufacturing process of the MOS field effect transistor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100 : 반도체 기판 102 : 산화막100 semiconductor substrate 102 oxide film

102' : 산화막 패턴 104 : 산소 이온주입 영역102 ': oxide film pattern 104: oxygen ion implantation region

106 : 격리막 108 : 게이트 절연막106: isolation film 108: gate insulation film

110 : 게이트 112 : 소오스/드레인 영역110: gate 112: source / drain region

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 모스 전계효과트랜지스터(이하, MOSFET라 한다) 제조시 SOI(silicon on insulator) 웨이퍼와 동시에 격리막(field oxide)을 형성하므로서 공정 단가를 줄일 수 있도록 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to fabricating a MOS field effect transistor (hereinafter referred to as MOSFET), silicon on                 Insulator) A method for fabricating a semiconductor device that reduces process costs by forming a field oxide at the same time as a wafer                 will be.

종래 일반적으로 사용되어 오던 MOSFET는 SOI 웨이퍼를 이용하여 소자를 제조할 경우, 제1(a)도 및 제1(b)도에 도시된 공정수순도에서 알 수 있듯이 먼저, 실리콘 웨이퍼인 반도체 기판(10) 상에 산소 이온주입(oxygen implantation)을 실시한 후 열처리(heating)하여 기판(10)/매몰 산화막(12)/실리콘(14) 구조의 SOI 웨이퍼(A)를 제작한 후 상기 SOI 웨이퍼(A) 위에 산화막(16) 및 질화막(18)을 덮고 감광막 패턴을 마스크로 사용하여 소자격리영역의 질화막(18) 및 산화막(16)을 제거하고, 열공정을 실시하여 그 곳에 격리막(20)을 형성시킨 뒤, 액티브영역에 트랜지스터를 형성하는 수순으로 소자를 제조해 왔다.MOSFETs, which have been generally used in the past, can be found in the process flowcharts shown in FIGS. 1 (a) and 1 (b) when a device is manufactured using an SOI wafer.                 As shown in the drawing, first, oxygen implantation is performed on a semiconductor wafer 10, which is a silicon wafer, followed by heat treatment.                 After fabricating an SOI wafer A having a substrate 10 / embedded oxide film 12 / silicon 14 structure, an oxide film 16 and a nitride film 18 were deposited on the SOI wafer A.                 Covering the photoresist pattern as a mask to remove the nitride film 18 and the oxide film 16 in the device isolation region, and performing a thermal process to form the isolation film 20 therein.                 Later, devices have been manufactured in the order of forming transistors in the active region.

그러나 상기 공정을 거쳐 MOSFET를 제조할 경우에는 기 언급된 바와 같이 SOI 웨이퍼를 제작하고 나서 이 SOI 웨이퍼 위에 격리막을 형성하는 수순으로 공정이 진행되므로 감광막 패턴을 이용한 사진식각공정(photolithgraphy) 및 기타 식각(etch)공정이 요구되어 공정이 번거로워질 뿐만 아니라, 현재 SOI 웨이퍼가 특성이 좋은데도 불구하고 실리콘 웨이퍼를 대체하지 못하는 이유가 가격(cost)이라는 점을 감안해 볼때 이를 양산공정에 실용화시키기 위해서는 공정 스텝(step)의 단순화를 통한 공정 단가의 감소가 무엇보다도 시급한 문제임을 알 수 있다.However, in the case of manufacturing a MOSFET through the above process, as described above, after fabricating an SOI wafer, an isolation film is formed on the SOI wafer.                 As the process proceeds in order, the photolithgraphy and other etching processes using the photoresist pattern are required, which makes the process cumbersome.                 In addition, given that the current reason is that SOI wafers can not replace silicon wafers even though they have good characteristics, the cost is                 In order to put it to practical use in mass production, it can be seen that the reduction of the process cost through the simplification of the process step is an urgent problem.

이에 본 발명은 상기와 같은 문제점을 감안하여 이루어진 것으로, SOI 웨이퍼를 제조하면서 동시에 격리막을 형성하므로서 공정 단순화를 기할 수 있도록 한 반도체 소자 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in view of the above problems, so that the process can be simplified by forming an isolation film while manufacturing an SOI wafer.                 Its purpose is to provide a method for manufacturing a semiconductor device.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자 제조방법은 활성영역과 소자격리영역이 정의된 반도체 기판 상의 소자격리영역에 절연막 패턴을 형성하는 공정과; 상기 절연막 패턴을 포함한 기판에 산소 이온주입 후 상기 절연막 패턴을 제거하는 공정과; 열처리를 통하여 산소 이온주입영역에 격리막을 형성하는 공정 및; 활성영역에 트랜지스터를 형성하는 공정을 구비하여 형성되는 것을 특징으로 한다.In the semiconductor device manufacturing method according to the present invention for achieving the above object is an insulating film pattern on the device isolation region on the semiconductor substrate defined active region and device isolation region                 Forming step; Removing the insulating film pattern after implanting oxygen ions into the substrate including the insulating film pattern; Separation membrane in oxygen ion implantation area                 Forming step; And forming a transistor in the active region.

상기 제조공정 결과, 공정 단순화를 이룰 수 있게 된다.As a result of the manufacturing process, the process can be simplified.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

본 발명은 SOI가 기존 벌크 소자(bulk device)에 비해 래치-업(latch-up) 문제가 없고, 접합 용량(junction capacitance)이 작으며, 쇼트 채널 효과(short channel effect)를 개선시킬 수 있을 뿐 아니라 레디에이션(radiation)에 대한 내성이 우수하고, 단순하고 확실한 소자분리(isolation) 등의 장점을 갖는 특성을 이용하여 0.1㎛ 이하의 MOSFET 제작에 적용코자 한 것으로, 현재 SOI 웨이퍼 가격이 벌크 웨이퍼에 비해 매우 비싸기 때문에 실제 공정에 적용이 않되고 연구실 부분에서만 일부 사용되고 있으므로 공정을 단순화를 통한 단가 감소로 양산공정에 적용 가능토록 하는데 주안점을 두고 있다.In the present invention, SOI has no latch-up problem compared to a bulk device, and a junction                 Small capacitance, not only improve short channel effect, but also reduce radiation                 It is designed to be applied to the fabrication of MOSFETs of 0.1 ㎛ or less by using the characteristics of excellent resistance, simple and reliable isolation.                 Currently, SOI wafer price is very expensive compared to bulk wafer, so it is not applied to actual process and is used only in part of lab.                 The main focus is to reduce the cost through simplification and to be applicable to the mass production process.

이를 제2(a)도 내지 제2(g)도에 도시된 공정수순도를 참조하여 구체적으로 살펴보면 다음과 같다.This will be described in detail with reference to the process purity shown in FIGS. 2 (a) to 2 (g).

먼저, 제2(a)도에 도시된 바와 같이 반도체 기판인 실리콘 기판(100) 위에 절연막으로서 산화막(102)을 형성하고, 감광막 패턴을 마스크로 한 사진식각공정으로 제2(b)도에 도시된 바와 같이 액티브영역의 산화막을 제거하여 소자격리영역에만 산화막 패턴(102')을 남긴다.First, as shown in FIG. 2 (a), an oxide film 102 is formed as an insulating film on a silicon substrate 100 as a semiconductor substrate, and a photoresist pattern is used as a mask.                 In the photolithography process, as illustrated in FIG. 2B, the oxide layer of the active region is removed to leave the oxide layer pattern 102 ′ only in the device isolation region.

이어서, 제2(c)도에 도시된 바와 같이 상기 산화막 패턴(102') 및 실리콘 기판(100) 상에 소정 깊이로 산소 이온주입을 실시하고, 실리콘 기판(100) 위의 산화막 패턴(102')을 제거하여 제2(d)도에 도시된 바와 같이 실리콘 기판(100) 내에 산소 이온주입 영역(104)이 형성되도록 한다.Subsequently, as illustrated in FIG. 2C, oxygen ion implantation is performed on the oxide film pattern 102 ′ and the silicon substrate 100 at a predetermined depth, and silicon                 By removing the oxide layer pattern 102 ′ on the substrate 100, the oxygen ion implantation region 104 is formed in the silicon substrate 100 as shown in FIG. 2D.                 To form.

그 다음, 열처리를 실시하여 제2(e)도에 도시된 바와 같이 실리콘 기판(100) 내에 격리막(106)이 형성된 구조의 SOI 웨이퍼(A)를 형성하고, 제2(f)도에 도시된 바와 같이 상기 SOI 웨이퍼(A) 표면에 게이트 절연막(108)을 형성한 후, 게이트 절연막(108) 상의 액티브영역에 게이트(110)를 형성한다.Then, heat treatment is performed to form an SOI wafer A having a structure in which the isolation film 106 is formed in the silicon substrate 100 as shown in FIG.                 As shown in FIG. 2 (f), the gate insulating film 108 is formed on the surface of the SOI wafer A, and then the active region on the gate insulating film 108 is formed.                 The gate 110 is formed.

그 후, 상기 SOI 웨이퍼(A) 전면에 게이트(110)를 마스크로 한 소오스/드레인 이온주입 공정을 실시하여 제2(g)도에 도시된 바와 같이 소오스/드레인 영역(112)을 형성하므로서 본 공정에 의한 MOSFET 소자 제조를 완료한다.Thereafter, a source / drain ion implantation process using the gate 110 as a mask is performed on the entire SOI wafer A, as shown in FIG. 2 (g).                 The source / drain regions 112 are formed to complete the MOSFET device fabrication by this process.

상술한 바와 같이 본 발명에 의하면, 1) 격리막을 SOI 웨이퍼와 동시에 형성하므로서, 공정 단순화를 기할 수 있을 뿐 아니라 이로 인해 공정 단가를 낮출 수 있게 되어 벌크 웨이퍼에 비해 가격면에서 차이가 커 양산공정에 적용하지 못했던 SOI 웨이퍼를 양산공정에 유리하게 적용할 수 있게 되고, 또한 2) 상기 SOI를 MOSFET 제조에 이용하므로서 래치-업 제거, 접합 용량 감소, 쇼트 채널 효과 개선, 레디에이션에 대한 내성 증가 및, 단순하고 확실한 소자분리 등의 부가적인 효과를 얻을 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.As described above, according to the present invention, 1) the isolation film is formed at the same time as the SOI wafer, thereby not only simplifying the process but also reducing the process cost.                 As a result, the SOI wafer, which could not be applied to the mass production process due to the large difference in price compared to the bulk wafer, can be advantageously applied to the mass production process.                 2) The use of the SOI in MOSFET fabrication eliminates latch-up, reduces junction capacity, improves short channel effects, increases resistance to redundancy, and                 It is possible to implement a highly reliable semiconductor device that can obtain additional effects such as reliable device separation.

Claims (1)

활성영역과 소자격리영역이 정의된 반도체 기판 상의 소자격리영역에 절연막 패턴을 형성하는 공정과; 상기 절연막 패턴을 포함한 기판에 산소 이온주입 후 상기 절연막 패턴을 제거하는 공정과; 열처리를 통하여 산소 이온주입영역에 격리막을 형성하는 공정 및; 활성영역에 트랜지스터를 형성하는 공정을 구비하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.Forming an insulating film pattern in the device isolation region on the semiconductor substrate in which the active region and the device isolation region are defined; After oxygen ion implantation into the substrate including the insulating film pattern                 Removing the insulating film pattern; Forming a separator in the oxygen ion implantation region through heat treatment; By forming a transistor in the active region                 A semiconductor device manufacturing method characterized in that it is formed.
KR1019950024980A 1995-08-14 1995-08-14 Manufacture of a semiconductor device KR0167253B1 (en)

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