JP2966037B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an MIS (Metal Insulator Semiconducto
r) type semiconductor devices, especially fine MOSFETs (Metal Oxide S
The present invention relates to a method of manufacturing an emiconductor field effect transistor).

(Prior Art) To increase the degree of integration of a semiconductor integrated circuit, it is important to reduce the area occupied by individual semiconductor devices constituting the integrated circuit. The above reduction is also essential for MOSFETs incorporated in semiconductor integrated circuits. For this reason, the gate length has been shortened.

However, when the gate length is shortened, a so-called short channel effect such as a decrease in threshold voltage and generation of a leak current due to punch-through in the sub-threshold region occurs.

Then, in order to solve this problem, MOSFETs of various structures have been conventionally proposed.

As one example, there is a so-called buried gate transistor as disclosed in, for example, JP-A-61-263277. Hereinafter, the structure of this transistor will be described with reference to FIGS. 6 (A) and 6 (B). Here, FIG. 6 (A) is a plan view schematically showing the buried gate transistor as viewed from above the substrate, and FIG. 6 (B) shows this transistor in a line II in FIG. 6 (A). FIG. 3 is a cross-sectional view schematically taken along the line. However, in FIG. 6 (A), illustration of the intermediate insulating film 25 and the wiring 29 among the components shown in FIG. 6 (B) is omitted.

In this buried gate transistor, a shallow trench 17 is provided in a predetermined region in an active region 15 surrounded by a field oxide film 13 of a silicon substrate 11. Further, a gate oxide film 19 is provided on the bottom and side surfaces of the groove 17. Further, a gate electrode 21 is buried in the groove 17 in which the gate oxide film 19 is provided. Diffusion layers 23 (hereinafter, source / drain regions 23) serving as source / drain regions are provided on both sides of the active region 15 with the groove 17 interposed therebetween. Further, an intermediate insulating film 25 is provided on the field oxide film 13 and the active region 15, and a predetermined portion of the intermediate insulating film 25 in a region facing the source / drain region 23 has a contact hole.
27 are provided. And this contact hole 27
The wiring 29 is connected to the source / drain region 23 through the wiring.

According to this buried gate transistor, a channel is formed between one source / drain region 23 and the other source / drain region 23 along the side surface and bottom surface of the trench 17 in the silicon substrate 11. For this reason, even if the gate length is shortened, the channel becomes longer by the amount of bypassing the periphery of the groove, so that the short channel effect can be reduced.

Furthermore, in order to comply with the comparative reduction rule, it is necessary to reduce the junction depth between the source and the drain. However, according to this buried gate transistor, the effective junction depth can be controlled by the depth of the groove 17, so that This was also advantageous.

Other transistors that can reduce the short-channel effect include, for example, an LDD (Lightly Doped Drain) structure as disclosed in the literature (“Ultra-high-speed MOS device”, Kazuki Kayama, Baifukan (1986), pp. 40-43). MO with
There was an SFET. Hereinafter, a structure of a transistor having an LDD structure will be described together with a manufacturing method thereof. 7 (A) to 7 (F) are manufacturing process diagrams for explanation thereof, and are process diagrams showing a state of the MOSFET in a main process in the manufacturing process by a cross section cut along the gate length direction. It is.

First, LOCOS (L
A field oxide film 33 is formed by an ocal oxidation of silicon (FIG. 7A).

Next, a gate insulating film 35 is formed on the surface of the silicon substrate by a thermal oxidation method. Further, a gate electrode material is formed on the silicon substrate 31 by a known film forming method, and thereafter,
The gate electrode material is patterned by a known photolithography technique and etching technique to form a gate electrode 37 (FIG. 7B).

Next, impurity ions are implanted into substrate 31 using gate electrode 37 as a mask to form n ⁻ diffusion layer 39. Thereafter, a silicon oxide film 41 is formed on the entire surface of the sample by a suitable method such as a CVD method (FIG. 7C).

Next, the silicon oxide film 41 is etched by anisotropic etching such as the RIE (Reactive Ion Etching) method or the like, and a sidewall 43 is formed on the side surface of the gate electrode 37 (FIG. 7D). The width W of the sidewall 43 in the gate length direction (see FIG. 7D) is controlled by the thickness of the silicon oxide film 41 and the conditions of anisotropic etching.

Next, using the gate electrode 37 and the side walls 43 as a mask, impurity ions are implanted into the substrate 31 at a high concentration this time, and thereafter heat treatment is performed to form an n ⁺ diffusion layer 45. In this heat treatment, activation of n ⁻ diffusion layer 39 is also performed at the same time.
Next, formation of the intermediate insulating film 47 and formation of the contact hole 49 in the intermediate insulating film 47 are performed by a conventionally known method (FIG. 7E).

Thereafter, an Al wiring 51 is formed by a conventionally known method to obtain the transistor (FIG. 7F).

According to the MOSFET having the LDD structure, the short-channel effect can be reduced because the peak electric field intensity of the drain depletion layer generated in the pinch-off state can be reduced.

(Problems to be Solved by the Invention) However, in both of the conventional buried gate transistor and the transistor having the LDD structure, the contact hole for the source / drain wiring is formed from the intermediate insulating film. In consideration of the processing accuracy and the like at the time of fabrication, the plane area of the source / drain region had to be widened with a margin. For this reason, there has been a problem that the parasitic capacitance due to the source / drain increases, which hinders the high-speed operation of the semiconductor device.

In addition, since the element isolation is performed by the field oxide film, there is a problem that the oxide film extends to the active region when the field oxide film is formed, that is, a bird's beak occurs, which hinders miniaturization.

This application has been made in view of such points,
Accordingly, it is an object of the first invention of the present application to provide a method for easily manufacturing a buried-gate MOSFET which can reduce the plane area of a source / drain region and the plane area of an element isolation region.

Another object of the second invention of this application is to provide a method of manufacturing a MOSFET which can reduce the plane area of a source / drain region and the plane area of an element isolation region, and can easily manufacture a MOSFET having an LDD structure. It is in.

(Means for Solving the Problems) In order to achieve the object of the first invention, according to the method of manufacturing a semiconductor device of the first invention, a first insulating film and a first conductor are formed on a silicon substrate. And a step of forming a second insulating film in this order, and exposing a substrate portion to be an active region formation region of the semiconductor device to the second insulating film, the first conductor, and the first insulating film. A step of forming a window, a step of forming a sidewall made of a third insulating film portion on the side wall of the window, and a step of forming a groove in a region of the silicon substrate exposed from the window with the side wall; Forming a gate insulating film in the trench; forming a second conductor and a planarization layer in this order on the entire surface of the substrate including the trench in which the gate insulating film has been formed; A groove made of a second conductor portion is formed in the groove. Forming a gate electrode, and removing a part or all of the side wall portion parallel to the gate width direction of the side wall surrounding the gate electrode until the silicon substrate surface is exposed, Forming a source / drain region by introducing an impurity into the silicon substrate portion exposed by partially removing the side wall, using the second insulating film, the gate electrode, and the remaining side wall as a mask; Forming a fourth insulating film on the upper surface of the gate electrode and on the side surface exposed by the removal of the sidewall; and in the removal mark of the sidewall portion, on the gate electrode, on the remaining sidewall, and A third conductor and a planarization layer are sequentially formed on the above-mentioned second insulating film, and then these are etched back to remove the trace of the sidewall portion. Forming a source / drain lead-out wiring composed of a third conductor portion therein, and including a region of the aforementioned second insulating film and the aforementioned first conductor in contact with the aforementioned source / drain lead-out wiring. Removing a region other than the predetermined region.

Also, in order to achieve the object of the second invention of this application,
According to the method of manufacturing a semiconductor device of the second invention, a step of forming a first insulating film, a first conductor, and a second insulating film on a silicon substrate in this order; Forming, in the first conductor and the first insulating film, a window exposing a substrate portion to be an active region formation region of the semiconductor device; and a sidewall including a third insulating film portion in the window Forming a gate insulating film in a region of the silicon substrate exposed from the window with the sidewall; and forming the gate insulating film in the window where the gate insulating film is formed, on the sidewall, and in the Forming a second conductor and a planarization layer on the second insulating film, and then etching back the second conductor and the planarizing layer to form a gate electrode including a second conductor portion in the above-described window; Surrounding said sidewall Removing a part or all of the side wall part parallel to the gate width direction until the surface of the silicon substrate is exposed; and forming the second insulating layer on the silicon substrate part exposed by partially removing the side wall. Forming a low-concentration impurity layer by introducing impurities using the film, the gate electrode and the remaining sidewalls as a mask; and forming a fourth insulating film on the upper surface of the gate electrode and the side surfaces exposed by removing the sidewalls. A step of forming a film, and introducing an impurity into a portion of the silicon substrate on which the low-concentration impurity layer is formed, using the second insulating film, the fourth insulating film, and the remaining sidewalls as a mask. Forming a source / drain region, and removing the sidewall portion, on the gate electrode, and on the remaining sidewall. And the second
Forming a third conductor and a flattening layer on the insulating film described above, and thereafter, etching back these to form a source / drain lead-out wiring composed of the third conductor in the trace of removal of the sidewall portion And removing a region of the second insulating film and the first conductor other than a predetermined region including a region in contact with the source / drain lead-out wiring.

(Operation) According to the method of manufacturing a semiconductor device of the first invention of this application, after forming a sidewall in a window, a portion of the silicon substrate exposed from the window with the sidewall is removed to form a trench for embedding a gate electrode. Then, a gate electrode is buried in and on the groove while using the side wall.
Then, part or all of a portion of the sidewall parallel to the gate width direction is removed until the silicon substrate is exposed, and a source / drain region is formed in the exposed substrate portion. Further, a conductor is embedded in the sidewall removal mark. To form source / drain lead-out wiring. As described above, according to the method of the second invention, each of the buried gate electrode, the source / drain region, and the source / drain lead-out wiring is self-aligned to the minimum necessary by utilizing the side wall provided in the window. Respectively.

Further, according to the method of manufacturing a semiconductor device of the second invention of this application, after forming the side wall of the window, the gate insulating film is formed on the silicon substrate exposed from the window with the side wall, and the gate is further formed in this window. Embed the electrodes. Then, a part or all of a portion of the sidewall parallel to the gate width direction is removed until the silicon substrate is exposed, and a low-concentration impurity layer is first formed on the exposed substrate portion, and then a fourth insulating layer is formed on the gate electrode. By forming a film, a side wall is provided on the gate electrode, a source / drain region is formed using the side wall as a mask, and a conductor is buried in the trace for removing the side wall to form a source / drain lead wiring.
As described above, according to the method of the second invention, the gate electrode and the low-concentration impurity layer are formed in a self-aligned manner using the sidewall provided in the window, and the fourth insulating film is formed on the gate electrode. By utilizing this, the source / drain region and the source / drain lead-out wiring can be formed in a self-aligned manner.

(Embodiments) Hereinafter, embodiments of each invention of this application will be described with reference to the drawings. The drawings used in the description schematically show the dimensions, shapes, and arrangements of the components so that the present invention can be understood.

Description of First Embodiment First, the structure of the semiconductor device of the first embodiment will be described with reference to FIG. Here, FIG. 1 is a perspective view of the semiconductor device of the first reference example with a part cut away, and shows the semiconductor device of the first reference example in a direction parallel to the gate length direction and in the thickness direction of the substrate. FIG.

In the semiconductor device of the first reference example, a first insulating film 63 is provided on a surface of a silicon substrate 61. The first insulating film 63 has a window 65 on the silicon substrate 61 exposing the active region of the semiconductor device. The planar shape and area of the window 65 can be arbitrarily set according to the design of the semiconductor device. The plane shape of the window of the first reference example is rectangular.

Further, in this semiconductor device, the silicon substrate 61
A groove 67 having an opening smaller than the window 65 is provided in a region exposed from the window 65. Further, a gate insulating film 69 is provided on the inner wall of the groove 67. Here, the planar shape and the depth of the groove 67 can be arbitrary depending on the design of the semiconductor device. The planar shape of the groove 67 of the first reference example is rectangular, and the short side dimension of the rectangle is determined by the gate length, and the long side dimension is determined by the gate width. In addition, the depth of the groove 67 is a value at which characteristics suitable for a buried gate transistor are obtained.

Further, in the semiconductor device of the first reference example, the gate electrode is formed in and on the groove provided with the gate insulating film 69.
An insulating film 73 is provided on the upper surface of the gate electrode 71 and on the side wall above the groove. Further, the gate electrode 71
A conductor 75 is buried between the side wall parallel to the gate width direction and the side wall of the window 65 facing the side wall to a height protruding from the surface of the first insulating film 63. Then, a source region is formed in a region corresponding to the lower side of the conductor 75 of the silicon substrate 61.
A drain region 77 is provided.

Here, the conductor 75 functions as a source / drain lead wiring. The conductor 75 is a first insulating film.
The portion protruding from the surface of 63 is connected to wiring 79 provided on first insulating film 63 (hereinafter, this wiring may be referred to as horizontal wiring 79 for convenience of description). A contact hole 81a is provided on the horizontal wiring 79.
Is provided. And horizontal wiring 79
Are connected to a wiring 83 (for example, an Al wiring 83) through a contact hole 81a. The gate electrode 71 is connected to the wiring 85 through a contact hole 73a provided in the insulating film 73.

In FIG. 1, reference numerals 87 and 89 denote insulating films, respectively. In this case, the insulating films 87 and 89 are formed by oxidizing a part of the conductor 75 for the insulating film 87,
The insulating film 89 is formed by oxidizing a part of the horizontal wiring 79. These details will be described in the section of the first embodiment of the present invention.

In the semiconductor device of the first reference example, the wiring structure other than the source / drain lead-out line arrangement 75 (conductor 75) is not limited to the example described with reference to FIG. Obviously, you can change it to something like that.

Description of First Invention Next, a method of manufacturing a semiconductor device according to the first invention will be described. 2 (A) to 2 (I) and 3 (A) to 3 (C)
FIGS. 2A to 2I are views for explaining an embodiment of the manufacturing method according to the first invention, and FIGS. 2A to 2I correspond to FIGS. 3 (A) to 3 (C), each showing a process diagram shown by a cutaway perspective view at a position where
FIG. 2 is a plan view showing the semiconductor device viewed from above the substrate for better understanding of FIG. 2;

First, a silicon substrate 61 is formed by a conventionally known suitable method such as a CVD (Chemical Vapor Deposition) method or a thermal oxidation method.
In this embodiment, a silicon oxide film is formed as the first insulating film 63 on the (100) plane. The film thickness of the first insulating film 63 may be a film thickness capable of element isolation, for example, a film thickness of a field oxide film conventionally used for element isolation.

Next, for example, by a CVD method, on the first insulating film 63, as a first conductor, impurity-doped polysilicon 79x in this embodiment, and as a second insulating film, a silicon nitride film in this embodiment. 81x are formed in this order. Although details will be described later, a part of the first conductor 79x constitutes the horizontal wiring 79 described in the section of the first reference example, and a part of the second insulating film 81x is described in the section of the first reference example. The insulating film 81 will be formed.

Next, the portions of the second insulating film 81x, the first conductor 79x, and the first insulating film 63, which correspond to the active region forming region of the semiconductor device, are formed by known photolithography and etching techniques. By removing each of them, a window 65 exposing the active region is formed in the second insulating film, the first conductor, and the first insulating film (FIG. 2A).
And FIG. 3 (A). ).

Next, in this embodiment, a silicon oxide film (not shown) is formed as a third insulating film in the window 65 and on the second insulating film 81x by, for example, a CVD method. Etching the third insulating film by anisotropic etching,
Side wall comprising a third insulating film portion on the side wall of window 65
91 are formed (FIG. 2 (B)).

Next, the window 65 with the side wall 91 of the silicon substrate 61
The region exposed from the substrate is removed to a predetermined depth by anisotropic etching to form a groove 67 in the region (FIG. 2C).

Next, by subjecting this sample to heat treatment, a gate insulating film 69 made of a silicon oxide film is formed in the groove 67 (FIG. 2 (D)).

Next, a material suitable as a constituent material of a gate electrode as a second conductor is formed in the trench 67 in which the gate insulating film 69 has been formed, on the sidewalls 91 and on the second insulating film 81x, for example, by a CVD method. In the case of the example, polysilicon is formed (not shown), and then, for example, a thick resist is formed as a flattening layer on the second conductor (not shown). After that, the planarizing layer and the second conductor are removed until the surface of the second insulating film 81x is exposed under such a condition that the resist as the planarizing layer and the polysilicon as the gate electrode material are etched at the same etching rate. Etching (etch back) and groove
A gate electrode 71 made of a second conductor is formed on 67 (FIG. 2E).

Next, the removal of part or all of the side wall portion parallel to the gate width direction of the side wall 91 surrounding the gate electrode 71 until the surface of the silicon substrate 61 is exposed is performed as described below.

In this embodiment, the side wall surrounding the gate electrode 71
Of the 91, the end portion of the side wall portion parallel to the gate width direction is left, and the portion between them is removed. Therefore, a resist pattern is formed on the sample by a known photolithography technique so as to expose an end portion of the side wall portion parallel to the gate width direction. After the completion of this step, the positional relationship among the gate electrode 71, the side wall 91, and the resist 201 is as shown in FIG. 3 (B). In the plan view of FIG. 3B, the resist portion is hatched to emphasize the resist portion (FIG. 3C).
In the same way).

Next, the side wall portion not covered with the resist 201 is etched until the silicon substrate is exposed by an etching means capable of selectively etching only the silicon oxide film constituting the side wall 91 (FIG. 2 (F) )).

Next, the second insulating film 81x and the gate electrode 71 are formed on the silicon substrate portion exposed by the partial removal of the side wall.
Then, impurities are introduced using the remaining side walls 91 as a mask to form source / drain regions 77 (FIG. 2F). Source / drain regions formed in this way
77 has a width shorter than the width of the gate electrode because the sidewall remains at the end in the gate width direction.
For this reason, the current flowing between the source and the drain can be effectively prevented from passing through the side surface of the groove 67, so that the current can be flown only to the original channel (the lower path of the groove 67) of the buried gate structure. I can do it.

Next, in order to form a fourth insulating film on the upper surface of the gate electrode 71 and the side surface exposed by removing the side wall, in this case, the gate electrode 71 is made of polysilicon. I do. This allows
A fourth insulating film, that is, the insulating film 73 described in FIG. 1 is obtained. (FIG. 2 (G)).

Next, in the removal mark of the sidewall portion, the gate electrode 71 was removed.
Above, on the remaining sidewalls 91 and on the second insulating film 81x, for example, an impurity-doped polysilicon is formed as a third conductor (not shown), and then on the third conductor. For example, a resist is formed as a planarization layer (not shown). Thereafter, the planarizing layer and the third conductor are removed from the second insulating film 81x under the condition that the resist as the planarizing layer and the third conductor are etched at the same etching rate.
Etch (etch back) until the surface is exposed.
When this step is completed, the source / drain is drawn out to the height protruding from the surface of the first insulating film 63 within the removal mark of the side wall portion, that is, between the side wall of the gate electrode 71 and the side wall of the window 65 parallel to the gate width direction. The wiring 75 is embedded (second
(H).

Next, as shown in FIG. 3C, a second insulating film 81x is formed.
And the source / drain lead-out wiring 7 of the first conductor 79x
A resist 203 is formed on a predetermined region including a region in contact with 5, by a known photolithography technique. Then the second
The portions of the insulating film 81x and the first conductor 79x which are not covered with the resist 203 are removed by a known etching technique. As a result, an insulating film 81 and a lateral wiring 79 are obtained (FIG. 2 (I)). Next, a heat treatment is performed on this sample, and an insulating film made of a silicon oxide film is
87 and 89 are formed respectively (FIG. 2 (I)). In addition,
In the heat treatment at the time of forming the insulating films 87 and 89, the impurity diffusion layers constituting the source / drain regions 77 are simultaneously activated.

Thereafter, a contact hole 73a is formed in the insulating film 73 and the contact hole 8 is formed in the insulating film 81 by a conventionally known method.
1a, the wiring 83, and the wiring 85 were respectively formed, and the buried gate type MO of the first reference example shown in FIG.
Obtain SFET.

Next, a structure of a semiconductor device according to a second reference example will be described with reference to FIG. Here, FIG. 4 is a partially cutaway perspective view showing the semiconductor device of the second reference example, in which the semiconductor device of the second reference example is placed in a direction parallel to the gate length direction and the substrate is placed in the thickness direction. FIG. In this figure, the same components as those of the semiconductor device of the first reference example are denoted by the same reference numerals.

In the semiconductor device of the second reference example, a first insulating film 63 having a window 65 for exposing the active region of the semiconductor device of the silicon substrate 61 is formed on the surface of the silicon substrate 61 as in the first reference example. It is provided.

Further, in this semiconductor device, the silicon substrate 61
A gate insulating film 69 and a gate electrode 71 from the silicon substrate 61 side on a region smaller than the window opening in a region exposed from the window 65
Are provided in order. Further, an insulating film 73 is provided on the upper surface and the side wall of the gate electrode 71. The planar shape of the window 65 and the planar shape of the gate electrode 71 are not limited to these, but are each rectangular as in the case of the first reference example.

Further, in the semiconductor device of the second reference example, the gate electrode 71 protrudes from the surface of the first insulating film 63 between the side wall parallel to the gate width direction and the side wall of the window 65 facing the side wall. The conductor 75 is buried to the height. In the silicon substrate 61, a source / drain region 77 is provided in a region substantially below the conductor 75, and further, a region in the silicon substrate 61 below the end portion of the gate electrode 71 in the gate length direction. Is provided with a low-concentration impurity layer 77a to form a so-called LDD structure.

Here, the conductor 75 functions as a source / drain lead wiring. Then, as in the first reference example, the conductor 75 is connected to a horizontal wiring 79 provided on the first insulating film 63 at a portion protruding from the surface of the first insulating film 63. . Further, similarly to the first reference example, an insulating film 81 having a contact hole 81a is provided on the horizontal wiring 79. And the horizontal wiring 79 is a contact hole
It is connected to the wiring 83 through 81a. The gate electrode 71 is connected to the wiring 85 through a contact hole 73a provided in the insulating film 73. Further, similarly to the first reference example, an insulating film 87 is provided on the conductor 75, and an insulating film 89 is provided on an end of the lateral wiring 79, respectively.

In the semiconductor device of the second reference example, the wiring structure other than the source / drain lead-out line arrangement 75 (conductor 75) is not limited to the example described with reference to FIG. It is clear that something can be done.

Further, the second reference example described above is a MOSFET having an LDD structure.
Although the third embodiment is applied to the third embodiment, it is apparent that the second embodiment can be applied to a MOSFET having no low-concentration impurity layer.

Description of Second Invention Next, an embodiment of the second invention will be described with an example of manufacturing the semiconductor device described with reference to FIG. Fig. 5 (A)
FIGS. 7A to 7G are views provided for the description, and are process diagrams showing the state of the semiconductor device in the main process in the manufacturing process by a cutaway perspective view at a position corresponding to FIG. Among the technical means of the manufacturing method of the second invention, there are many similar technical means used in the manufacturing method of the first invention. Therefore, it is to be understood that description of such similar technical means may be omitted in the following description.

First, by the same method as in the first invention, the silicon substrate 61
A silicon oxide film as the first insulating film 63, doped polysilicon as the first conductor 79x, and a nitride film as the second insulating film 81x are sequentially formed thereon. Further, the first insulating film 63 and the first insulating film 63 are formed in the same manner as in the first invention.
A window 65 exposing a region where an active region is to be formed of the semiconductor device is formed in the conductor 79x and the second insulating film 81x (FIG. 5A). Further, a side wall 91 is formed on the side wall of the window 65 by a method similar to the first invention (FIG. 5B).

Next, this sample is subjected to a heat treatment,
Then, a gate insulating film 69 made of a silicon oxide film is formed in a region exposed from the window 65 on which the sidewall is formed (FIG. 5C).

Next, polysilicon as a second conductor is formed by, for example, a CVD method in the window 65 on which the gate insulating film 69 has been formed, on the sidewalls 91, and on the second insulating film 81x (not shown). Thereafter, a thick resist, for example, is formed as a planarizing layer on the second conductor (not shown). Thereafter, the flattening layer and the second conductor are etched back until the surface of the second insulating film 81x is exposed, and a window with a sidewall is formed.
A gate electrode 71 made of a second conductor portion is formed in 65 (FIG. 5D).

Next, part or all of the side wall portions of the side wall 91 surrounding the gate electrode 71, which are parallel to the gate width direction, are removed until the surface of the silicon substrate 61 is exposed. By the same method as in the invention, the end portion of the side wall portion parallel to the gate width direction is left, and the portion therebetween is removed (FIG. 5 (E)). Next, the second insulating film 81x, the gate electrode 71 and the remaining sidewalls 91 are used as a mask to introduce impurities into the silicon substrate portion exposed by the partial removal of the sidewalls, thereby forming the low-concentration impurity layers 77a. (FIG. 5 (E)).

Next, in order to form a fourth insulating film on the upper surface of the gate electrode 71 and the side surfaces exposed by removing the sidewalls, a heat treatment is performed on the sample as in the first invention.
Thus, a fourth insulating film, that is, the insulating film 73 described in FIG. 4 is obtained (FIG. 5F).

Next, using the gate electrode 71, the side wall 91, the second insulating film 81x, and the fourth insulating film 73 as a mask, impurities are introduced at a high concentration into the substrate portion where the low concentration impurity layer 77a is formed. Thus, source / drain regions 77 are formed (FIG. 5 (F)). When this step is completed, the silicon substrate 61
The low impurity concentration 77a is formed in a portion below the end in the gate length direction of the gate electrode 71, and the source / drain region 77 is formed in a portion below the portion where the sidewall is removed.

Next, in the removal mark of the sidewall portion, the gate electrode 71 was removed.
On the remaining sidewall 91 and the second insulating film
Impurity-doped polysilicon is formed on 81x as a third conductor (not shown), and thereafter, for example, a resist is formed as a planarization layer on the third conductor (not shown).
After that, the planarizing layer and the third conductor are formed on the second insulating film 81x.
Etch back until the surface is exposed. When this step is completed, the gate electrode is left within the trace of removal of the sidewall portion.
The source / drain lead-out wiring 75 is buried between the side wall parallel to the gate width direction of 71 and the side wall of the window 65 to a height protruding from the surface of the first insulating film 63 (FIG. 5 (G)).

Next, similarly to the method of the first invention, unnecessary portions of the second insulating film 81x and the first conductor 79x are removed to form the insulating film 81 and the horizontal wiring 79 (FIG. 5 (G)). ).

Thereafter, a heat treatment is performed on the sample to form insulating films 87 and 89 made of a silicon oxide film on the surface portion of the source / drain lead-out wiring 75 and the end portion of the lateral wiring 79, respectively (FIG. 5 (G)). ). Note that in the heat treatment at the time of forming the insulating films 87 and 89, activation of the low-concentration impurity layer 77a and activation of the impurity diffusion layer forming the source / drain region 77 are simultaneously performed.

Thereafter, the contact hole 73 is formed by a conventionally known method.
a, the contact hole 81a, the wiring 83 and the wiring 85 are formed to obtain the MOSFET shown in FIG.

It should be noted that the materials used in the embodiments of the invention of each of the above-described manufacturing methods can obviously be changed to other suitable materials within the scope of the present invention.

(Effects of the Invention) As is clear from the above description, according to the method of manufacturing a semiconductor device of the first invention of the present application, a buried gate electrode and a source
Since the drain region and the source / drain lead-out wiring can be formed in a self-aligned manner with a minimum necessary area, the semiconductor device of the first invention can be easily manufactured.

According to the method of manufacturing a semiconductor device of the second invention of this application, the gate electrode and the low-concentration impurity layer are formed in a self-aligned manner using the sidewall provided in the window, and the fourth insulating film is formed on the gate electrode. Since a film is formed and the source / drain region and the source / drain lead-out wiring can be formed in a self-aligned manner by using the film, a semiconductor device having an LDD structure can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a cutaway perspective view for explaining a semiconductor device of a first reference example, and FIGS. 2A to 2I are process diagrams for explaining an embodiment of a manufacturing method of the first invention. 3 (A) to 3 (C) are views for explaining an embodiment of the manufacturing method of the first invention, FIG. 4 is a cutaway perspective view for explaining a semiconductor device of a second reference example, FIG. (A) to (G) are process diagrams for explaining an embodiment of the manufacturing method of the second invention. FIGS. 6 (A) and (B) are plan views and cross sections for explaining the structure of a conventional semiconductor device. FIGS. 7 (A) to 7 (F) are diagrams for explanation of a conventional technique. 61 silicon substrate 63 first insulating film (silicon oxide film) 65 window 67 groove having an opening smaller than the window 69 gate insulating film 71 gate electrodes 73 81 87, 89 Insulating film 73a Contact hole 75 Conductor (source / drain lead-out wiring) 77 Source / drain region 77a Low-concentration impurity layer 79 Wiring (horizontal wiring) 79x First conductor (doped polysilicon) 81a Contact hole 81x Second insulating film (silicon nitride film) 91 Side walls 201, 203 Resist.

Claims (2)

(57) [Claims] A step of forming a first insulating film, a first conductor, and a second insulating film on a silicon substrate in this order; and forming a second insulating film, a first conductor, and a first insulating film. Removing portions of each of the insulating films corresponding to regions where active regions are to be formed in the semiconductor device, and exposing the active regions to the second insulating film, the first conductor, and the first insulating film. Forming a window; forming a third insulating film in the window and on the second insulating film; thereafter, etching the third insulating film by anisotropic etching to form a window on the side wall of the window. Forming a side wall made of a third insulating film portion, and forming a groove in the region by removing an area exposed from the side walled window of the silicon substrate to a predetermined depth by anisotropic etching. Forming a gate insulating film in the trench. Forming a second conductor in the trench in which the gate insulating film is formed, on the sidewalls and on the second insulating film, and then form a planarization layer on the second conductor. After that, the planarizing layer and the second conductor are
Forming a gate electrode comprising a second conductor portion in the trench by removing the insulating film surface until the surface of the insulating film is exposed; and sidewalls of the sidewalls surrounding the gate electrode parallel to the gate width direction. Removing part or all of the portion until the surface of the silicon substrate is exposed; and forming the second insulating film, the gate electrode, and the remaining sidewall on the silicon substrate portion exposed by partially removing the sidewall. Forming a source / drain region by introducing impurities using the mask as a mask; forming a fourth insulating film on the upper surface of the gate electrode and the side surface exposed by removing the sidewall; Forming a third conductor on the gate electrode, on the remaining sidewalls, and on the second insulating film; A planarization layer is formed on the conductor, and then the planarization layer and the third conductor are removed by etch-back until the surface of the second insulating film is exposed. 3
Forming a source / drain lead-out wiring composed of a conductor portion of the above, and removing a region other than a predetermined region of the second insulating film and the first conductor, including a region in contact with the source / drain lead-out wiring A method of manufacturing a semiconductor device. A step of forming a first insulating film, a first conductor, and a second insulating film on a silicon substrate in this order; and forming a second insulating film, a first conductor, and a first insulating film. Removing portions of each of the insulating films corresponding to regions where active regions are to be formed in the semiconductor device, and exposing the active regions to the second insulating film, the first conductor, and the first insulating film. Forming a window; forming a third insulating film in the window and on the second insulating film; thereafter, etching the third insulating film by anisotropic etching to form a window on the side wall of the window. Forming a sidewall made of a third insulating film portion; forming a gate insulating film in a region of the silicon substrate exposed from the window with the sidewall; On the sidewall and the second A second conductor is formed on the insulating film, a planarization layer is formed on the second conductor, and the planarization layer and the second conductor are then etched back by the second conductor.
Is removed until the surface of the insulating film is exposed, and the second
Forming a gate electrode made of a conductive portion of the above, and removing a part or all of the side wall portion parallel to the gate width direction of the side wall surrounding the gate electrode until the surface of the silicon substrate is exposed. Forming a low-concentration impurity layer by introducing impurities into a portion of the silicon substrate exposed by partially removing the sidewalls, using the second insulating film, the gate electrode, and the remaining sidewalls as a mask. Forming a fourth insulating film on the upper surface of the gate electrode and the side surface exposed by removing the sidewall; and forming the second insulating film on the silicon substrate portion where the low-concentration impurity layer is formed. Using the insulating film and the remaining sidewalls as masks to introduce impurities to form source / drain regions; Forming a third conductor on the gate electrode, on the remaining sidewalls, and on the second insulating film in the trace of removal of the rule portion, and thereafter planarizing the third conductor on the third conductor. After the layer is formed, the planarization layer and the third conductor are removed by etch back until the surface of the second insulating film is exposed, and the third conductor is removed in the removal mark of the sidewall portion.
Forming a source / drain lead-out wiring composed of a conductor portion of the above, and removing a region other than a predetermined region of the second insulating film and the first conductor, including a region in contact with the source / drain lead-out wiring A method of manufacturing a semiconductor device.