1 3 9 7 2 M2 Β 經濟部中央標準局貝工消費合作杜印製 五'發明説明（/) 〔發明領域〕 本發明為關於一半導體樓體電路結構及製造此形成有 自動對準電晶體結構之積體電路的方法。 〔習用技藝之說明〕 自動對準矽閘極場效應電晶體製法及形成之結構為工 業性標準已有多時。此製程為涉及成長一隔離層在半導體 基底及然後形成一複晶矽層於其上。光學及蝕刻技術已使 用做為去除積體電路結構該場效應電晶體閘極所在區域以 外之所有的複晶矽層。此形成之閘極結構此時即做為一供 形成稱為一自動對準結構之電晶體的源/汲極的遮罩。 已有對自動對準製程及結構改進的方案。此等改進方 案對於次微米稹體電路之製造格外重要。 其一種改進之方案為形成窄尺寸之方法，例如在一半 導體本體上之次微米區域。可參照I . T · Ho等人之美 國專利第4，209，349及第4，234，362號 案、K . RI SEMAN之美國專利第4 . 234 , 36 2號案及Η · B · P0GGE之美國專利第4，256 . 5 1 4號案，其揭露該區域之形成。此等專利案全部為涉 及在一矽本體形成約呈水平表面或約呈垂直表面，及然後 同時在該約呈水平或約呈垂直之之畏面上形成一極窄尺甘 之材料層。此層材料然後供做為一如離子反應蝕刻之非均 向性蝕刻製程使用•以約完全地去除該水平層，以曝露出 矽基底，然而該垂直層則毫不受損地保留下來。該垂直層 _3_ r 本紙張尺度逋用中國國家標率（CNS ) Α4规格（210Χ297公釐） 1 --------^ -裝-- (請先閲讀背面之注意事項再填寫本頁)1 3 9 7 2 M2 Β Du Gong Wu's description of the invention of the cooperation of the Belgian Consumer Standards Bureau of the Central Standards Bureau of the Ministry of Economic Affairs (/) [Field of the invention] The present invention relates to the circuit structure of a semiconductor building and the manufacture of self-aligned transistors Method of structured integrated circuit. [Explanation of conventional techniques] It has been an industrial standard that the method of automatically aligning silicon gate field effect transistors and the structure formed there have been industrial standards. This process involves growing an isolation layer on the semiconductor substrate and then forming a polycrystalline silicon layer thereon. Optical and etching techniques have been used to remove all polysilicon layers outside the area where the field effect transistor gate of the integrated circuit structure is located. The gate structure thus formed serves as a mask for forming the source / drain of a transistor called an auto-alignment structure. There have been plans to improve the automatic alignment process and structure. These improvements are particularly important for the manufacture of sub-micron lumped body circuits. An improved solution is to form narrow dimensions, such as sub-micron areas on the semiconductor body. Reference can be made to US Patent Nos. 4,209,349 and 4,234,362 of I. T. Ho et al., US Patent No. 4.234, 36 2 of K. RI SEMAN and Η · B · POGGE U.S. Patent No. 4,256. 514 case, which discloses the formation of this area. All of these patents involve the formation of an approximately horizontal surface or approximately vertical surface on a silicon body, and then simultaneously forming a very narrow scale material layer on the approximately horizontal or approximately vertical surface. This layer of material is then used as an anisotropic etching process like ion-reactive etching. • The horizontal layer is approximately completely removed to expose the silicon substrate, while the vertical layer remains without damage. The vertical layer _3_ r is based on the Chinese National Standard Rate (CNS) Α4 specification (210Χ297mm) 1 -------- ^ -installed-- (Please read the precautions on the back before filling in this page)
、1T ^1279 ^1279 ^__^_ 經濟部中央標準局貝工消费合作社印製 A7 B7 發明説明（>) 之尺寸則視該層原來的厚度而被調整。以此方法即可獲得 一微米或更低的窄尺寸區域。 另一改進的自動對準閘極結構為淺摻雜汲極或L D D 。例如，除了通道隔開之植入有N+之源極與汲極區域以 外，在一N通道MOSFET内即包含該LDD，而此區 域為次微米擴散之N -區域。此等N -區域即提昇通道崩 潰電壓及降低汲極接面電子碰撞離子化（即熱電子發射） 此為藉由在該汲極邊緣區域散佈高電場進入至N—區域 達成。一供製出該LDD裝置之改進製程為揭露在S·0 GURA等人之美國專利第4，366，613號案，其 中N —區域為使用複晶矽閘極做為光罩首先予以形成，然 後次微米側壁層為形成在複晶矽閘極之側壁•及N+源/ 及極區域為使用閘極及側壁層結構做為光罩離子植入形成 ，故形成該N — L D D結構者。其他淺摻雜汲極結構及方 法為顯示在I . T . H0等人之美國專利第4，209， 349 及第 4，209，350 號中》 相反之自對對準場效應電晶體製法為由此領域中少數 的人員所提出。參照授予THOMSON CSF之美國 專利第4，296，426號、授予 C . G · JAMB0 TKAR之美國專利第4，546，535號案。此等專 利概略為揭露以一如複晶矽或類似材料之重摻雜的導電層 形成在一矽基底或一在其上之絕緣層上方之相反製程》此 多層結構為蝕刻至矽基底位置•以形成圈形化之含有約呈 -4- 〆 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ΙΓ,------^ -裝------訂-----」4 (請先閱讀背面之注意事項再填寫本頁) S11279 A7 B7 五、發明説明（)） 垂直側壁層之導電複晶矽層或類似材料。此導電層之圖形 為選定在平面之源/汲極區域•及在該場效應電晶體通道 位置形成開□。一側壁絕縁層此時如前段之例子所述可形 成在垂宜側壁層上。此側壁層可以導電性摻雜劑予以摻雜 。該閘極介電層為形成在通道表面上。該源/汲極區域及 淺摻雜區域較宜同時藉熱能而分別由導電性第一複晶矽層 或類似材料與絕縁側壁層位置騸入所形成。該預期之閘極 即形成在閘極介電層上方及形成電性連接該場效應電晶體 裝置之不同元件。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 前述用以形成自動對準裝置之方法，因無法防止蝕刻 材料侵入基底位置，故可能導致位在裝置之通道上方的基 底表面關鍵區域受損。在以非均向性離子蝕刻形成側壁層 期間及在該相反自動對準技術之重摻雜導電層之蝕刻期間 •即難以控制在適當時間停止蝕刻而不損及基底。一解決 此形成雙極性電晶體問題之解決方案為顯示在F A V R E AU之美國專利第5，162，245號案中。然而此為 由FAVREAU所述之複晶矽選擇性成長技術可能無法 達到完全地選擇性，致使複晶矽或複晶矽殘餘物生成在氧 化層1 8之頂部上。此不需要的複晶矽可能導致後續之缺 陷、電性短路等之問題。 〔發明概要〕 因此本發明之目的在於改進自動對準製程及令最終形 成之結構可達到防止損及基底。 _ 5 _ " 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 311279 A7 B7 五、發明説明（γ) 本發明之另一目的在於提供可同時製出雙極性及場效 應電晶體之改進的自動對準製程。 本發明之又一目的在於提供可製出B I CMOS積體 電路之改進的自動對準製程。 經濟部中央揉準局身工消費合作杜印製 (請先閲讀背面之注意事項再填寫本頁) 依據本發明•為一種述及形成雙極性或場效應的自動 對準電晶體之方法。一第一絕緣層為形成在一單晶半導體 基底表面上。一第二絕緣層為形成在該第一絕縁層表面上 。一第三絕緣層為形成在該第二絕縁層表面上。該第一、 第二及第三絕緣層為圖形化形成為保護塊而覆蓋在電晶體 之第一元件位置上•在雙極性電晶體之例子中之射極位置 上及在一場效應電晶體之例子中為在閘極區域上。一導電 型式之重摻雜導電層為形成在有相反導電型式之單晶半導 電基底上及該保護塊之上。一第四絕緣層為形成在該重摻 雜導電層上。該重摻雜導電層之局部及位在第三絕緣層頂 部水平面上方之第四絕緣層然後被去除。該第三絕緣層為 由保護塊位置移除。此結構為被加熱以形成為一雙極性電 晶體之基極重摻雜部份*及形成為一場效應電晶體之重摻 雜源/汲極部份，藉由該重摻雜導電層向外擴散所形成。 該重摻雜導電層之曝露部份為氧化成為鄰接保護塊之氧化 側壁層。其餘的保護塊然後被去除。一第五絕緣層為在形 成為一場效應電晶體時，乃形成在閘極元件之位置上。一 第二導電層為形成及圖形化定義形成在該第五絕緣層上及 上方•而電晶體各元件為以電性連接至電晶體元件位置而 y -6- ^ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五 經濟部中央標準局員工消費合作杜印製 A7 B7 發明説明（1) 完成。 一自動對準電晶體樓體電路裝置結構亦可由本發明構 想出。此結構包括一矽半導體基底·具有場隔離區域以隔 離半導體各個表面區域。一導電性之重摻雜區域，至少具 有數個為相反導電率之半導體表面區域。直接位在該重摻 雜區域上方者|為相同導電率之重摻雜導電層及為重摻雜 區域之摻雜源。在該重摻雜導電層之内周邊位置上為氧化 側壁層。數個機構為提供電晶體其餘元件之連接。適當電 性連接機構為使元件形成完整的横體電路結構。雙極性及 場效應電晶體裝置結構均可被構想出。 〔圖面簡單說明〕 第一圖至第四圈：為表示防止損及基底之一場效應電 晶體改良的自動對準製程之第一實施例方法的剖面圖。 第五圖：為使用第一實施例方法製出一雙極電性電晶 體之結構剖面圖。 第六圖：為組合第一圈至第五圖之實施例以製出一 Β I CMOS結構之結構剖面圖。 第七圖及第八圖：為搭配有本發明之改良自動對準製 程之形成一場隔離區域之方法的剖面圖。 〔發明說明〕 現參照第一圖至第四圈所示•其顯示一自動對準電晶 體在一高密度積體電路結構。製程為描述形成一N通道Μ 0 S F Ε Τ樓體電路。然可瞭解的是，Ρ通道場效應電晶 -7- ' 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ___：------一-裝______訂______*·^ (請先閱讀背面之注意事項再填寫本頁) 311279 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（乂） 體可藉簡單地令電晶體及相關區域之不同元件為相反極性 予以形成。 該第一系列之步驟為涉及形成保護塊以防止損及基底 之閘極區域。該半導體基底1〇可由各式任何已知半導體 材料組成，但較宜為以具有一（1 〇 〇)矽晶特性之矽組 成。該基底1 0在此例中為如第一圖中為摻雜P—。 第一氧化矽層12為藉習知機構熱成長成為一厚度約 在2 5 0〜3 5 0A者。一氮化矽層1 4然後為藉化學氣 相沈積法沈積形成為一厚度約在1 〇 〇 〇〜1 5 0 0A者 。另一氧化矽層16為以四乙氧甲矽烷（TEOS)型式 藉由化學氣相沈積法沈横形成為一厚度約在3 5 0 0〜4 0 0A者。此三層絕緣層然後使用習知光學及蝕刻方式被 定義形成為如顯示在第一圖之0 — N-0 (二氧化矽一氮 化矽一二氧化矽）保護塊1 8。 一複晶矽20層此時即沈積覆蓋在該基底10及該保 護塊1 8上。複晶矽2 0然後以磷進行離子植入，而在此 實施例中為形成一N通道F ET裝置。倘若欲形成一 P通 道F ET時•而該離子植入為以適當P型摻雜劑如硼或氟 化硼（BF2 )實施。該複晶矽層之厚度為約在4500 〜5 5 0 0A之間。_氮化矽層2 2此時即藉化學氣相沈 横法沈稹至一約在1 0 0 0〜2 0 0 0A之厚度。 現參照第二圖所示，該層2 0及2 2為以一光阻平坦 化及回蝕刻製程進行蝕刻至氧化層1 6露出（圖面顯示為 -8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 丨裝. 訂 經濟部中央標準局貝工消費合作社印装 311279 A7 B7 五、發明説明（7 ) 已去除）。使用之蝕刻技術可為_使用如CF4 ' c 2 F 6 、〇2之化學成份之離子反應蝕刻（該氟成份對複晶矽 提供一高蝕刻率·而該氧氣則提供光阻一高蝕刻率〉，或 是使用化學機械研磨。在第二圖可看出，該複晶矽層2 0 之局部部份為在保護塊1 8及氮化矽2 2間之區域曝露出 。氧化層16為使用HF在一10 : 1比例及在一約2 5 °C之溫度下進行一濕蝕刻去除。該N +源/汲極區域2 3 此時為對第二圖結構在約9 0 0〜9 5 0 °C下退火直到該 N+接面在表面下方形成約〇·2〜0·3微米者。該退 火步驟為在一 5%氧氣及氮氣環境下進行約3 0〜4 0分 鐘完成。 現參照第三圖，氮化矽層2 2供做為在複晶矽2 0氧 化期間之光罩•其為形成氧化側壁層2 4。氧化步驟為在 —溫度約在9 0 0〜1 0 0 0 °C之氧氣環境進行約6 0〜 1 2 0分鐘者。 該形成之側壁層2 4有一約2 5 0 0〜3 5 0 0A之 厚度。此側壁層氧化可在通道邊緣位置造成一漸近接面輪 廓，即形成較未氧化之區域深約〇·05〜0.1微米。 此即形成一提供更佳熱載子效能之淺摻雜汲極（L D D ) 結構。第三_之虛線為顯示在複晶矽氧化之前的接面，而 實線顯示其在氧化期間移動後之接面。該側壁層之厚度可 藉改變製程參數之控制以形成一通道長度（即保護塊1 8 下方之基底區域）可小於光學極限與形成一對次微米裝置 -9- ^ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --------^ —裝------訂-----I 線 (請先閲讀背面之注意Ϋ項再填寫本頁) 經濟部中央揉準局貝工消費合作社印製 各11279 A7 ________ B7 _ 五、發明説明（/ ) 製造極重要的概念》 氮化矽層22提供一優於美國專利第5，1 26，2 4 5號案之習用技術為在於複晶矽2 0之厚度可在氧化期 閭可被保護住。此厚度對於複晶矽片狀阻抗而言極為重要 °然在習用技術無氮化矽層.故必須在片狀阻抗問題及在 複晶矽所需厚度之間做取捨.以產生所需之複晶矽氧化層 〇 現參照第四圖所示·其餘的保護塊、氮化矽層1 4及 氧化層12被蝕刻去除，而MOSFET裝置之閘極結構 即完成。氮化矽層1 4藉使用磷酸在約在1 60〜1 9 0 °C之溫度進行約40〜1 0 0分鐘實施濕蝕刻去除掉。薄 墊層氧化層1 2此時即以一濕蝕刻去除及一約1 5 0〜3 〇 0A厚度之成長的薄厚度的犧牲氧化層為在一乾氧環境 以去除任何位在通道區域之KO 0 I型缺陷。此犧牲氧化 層然後以50:1之氫氟酸溶液中濕蝕刻去除，而最後， 閘氧化層2 6為在一約在9 2 0〜9 6 0 °C溫度下使用異 構物（TRANS-LC) L C及氧氣環境下熱成長形成。 如第四圖所示之場效應電晶體的閘極2 6此時為藉習 知光學及蝕刻技術形成覆蓋在該閘極介電層及圖形之上。 該閘極為以複晶矽及藉由低壓化學氣相沈積法沈積形成。 此閘極層2 6之厚度約在3 0 0 0〜4 0 0 0 A之間。 一較高之冶金層（圖未示）為透過複晶矽層20及該 閘極2 6以與該源/汲極區域接觸。此冶金層較宜為以鋁 -10- 一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 一 潘裝 訂 * 線 (請先閱讀背面之注意事項再填寫本頁) A7 S11279 B7 五、發明説明（？） 或類似材料構成。冶金層之間之保護及絕縁，可藉濺鍍或 電漿法沈積氧化矽或類似材料完成。 本發明該F ET裝置之閘極區域均由氮化矽保護住， 而絕對不致曝露在外而導致複晶矽蝕刻或習用技術之氧化 層側壁受到離子反應蝕刻*如1即防止該FET裝置之主 要通道區域之基底區域受損。 現更參照第五圖所示，顯示一透過不同於第一圖至第 四圖實施例之製法形成垂直N P N雙極性積體電路結構^ 一垂直PNP雙極性結構為如熟習此技藝可得知者，當然 可透過改變該涉及製程之區域的導電特性而製出。 此雙極性實施例為以一類似於該第一實施例之方式施 行，並以相同數字顯示兩實施例之相同元件。然唯一不同 處為在於需要N —次集極3 2及N+磊晶層3 0位在該P —基底上，以形成該第五圖實施例之基底1 0。如已知技 術，此磊晶層為形在該整個P —基底上。一N —區域為在 該雙極性裝置形成位置及在該磊晶層成長前形成在基底内 ，而此N—次集極區域為在該磊晶層成長向外擴散期間形 成者。 此外，第一圈至第四圖之製程中，除了該層2 0摻雜 為以一相反導電性（P+)施加至第一實施例及藉由一類 似向外擴散製程形成該P +區域3 4以形成該雙極性電晶 體之外部基極34之外·其餘概呈相同於形成NPN結構 者。内部基極區域4 6亦為透過一硼離子植入通過該犠牲 -11- 〆 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） n ~ -- I In ml In m ^^1 m I I I I n J (請先閏讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（h) 氧化層所形成，此區域為在對薄墊層氧化層1 2蝕刻之後 所形成者。集極接觸區4 2為如射極接觸區4 4以相同於 第一實施例據以形成閘極之方式同時形成者。射極接觸區 44為以砷（或在一PNP結構之例子中以BF2材料） 離子植入，而射極區域4 8為透過一約9 0 0 °C進行3 0 分鐘之加熱週期以騸散該砷摻雜與形成該淺接面。 最後一個不同於F ET製程者為在該雙極性射極區 域内之閘氧化層為在早於形成該複晶矽射極接觸區4 4之 前以濕蝕刻去除。若以第一圖至第四圖之實施例·即造成 該第五圖實施例需要一較高位置之冶金層（圖未示）以接 觸電晶體元件•亦即為接觸射極4 4、基極接觸層2 0與 集極4 2。該冶金層較宜為鋁或類似材料。冶金層間則需 要類似於第一實施例之保護及絕緣。 在前述兩實施例之隔開各個主動電晶體結構之場隔離 區域可以其他習知方法形成。習知技術為本地矽層氧化（ LOCOS)及通常為在形成電晶體區域之前實施者。然 而如第七圖及第八圖所示，該場隔離區域可藉蝕刻該電晶 體區域之氮化矽層2 2的局部位置以形成開口6 0的形成 方式取代，而在氧化形成側壁層2 4期間，透過複晶矽氧 化形成該場隔離區域62。此即可免除LOCOS製程步 驟。 第一圖至第四圖及第五圖顯示之寅施例中，亦可組合 成如第六圖所示，而供運用於B I C Μ 0 S。其顯示為一 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） --------1 -裝------訂-----J 線 (請先閲讀背面之注意事項再填寫本頁) ^11279 * A7 B7 五、發明説明（i I) NMO S場效應電晶體在相同基底表面以視為_NP N雙 極性裝置。其他組合，如一PMOS FET及一PNP 雙極性裝置可如熟習此技藝人士得知亦可予以形成。 而本發明以參照較佳實施例做特別的顯示及說明，而 熟習此技藝人士在不脫離本發明精神及範圍下所為在型式 及細節上的各式變更均可予以暸解。 --I - I - I L I _ _ _ I n .^1 T I - - I _ j 泉 US. 、νδ 系 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 -13- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）, 1T ^ 1279 ^ 1279 ^ __ ^ _ Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 The size of the invention (>) is adjusted according to the original thickness of the layer. In this way, a narrow area of one micron or less can be obtained. Another improved self-aligned gate structure is shallow doped drain or LD D. For example, in addition to the N + source and drain regions where the channels are separated, the LDD is contained in an N-channel MOSFET, and this region is a sub-micron diffused N- region. These N-regions increase channel breakdown voltage and reduce electron impact ionization (ie, thermoelectron emission) at the drain junction. This is achieved by spreading a high electric field into the N-region of the drain edge region. An improved process for producing the LDD device is disclosed in US Patent No. 4,366,613 of S · GURA et al., Where the N-region is first formed by using a polycrystalline silicon gate as a photomask, Then the sub-micron sidewall layer is formed on the sidewall of the polycrystalline silicon gate, and the N + source / electrode region is formed using the gate and sidewall layer structure as a mask ion implantation, so the N-LDD structure is formed. Other shallowly doped drain structures and methods are shown in US Patent Nos. 4,209, 349 and 4,209,350 of I.T.H0 et al .. Contrary to the self-aligned field-effect transistor fabrication method is Proposed by a few people in this field. Refer to U.S. Patent No. 4,296,426 granted to THOMSON CSF and U.S. Patent No. 4,546,535 granted to C. G. JAMB0 TKAR. These patents outline the reverse process of forming a heavily doped conductive layer like polycrystalline silicon or similar material on a silicon substrate or an insulating layer above it. This multilayer structure is etched to the silicon substrate In a circle, the content is approximately -4- 〆The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ΙΓ, ------ ^ -installation ------ order- --- "4 (Please read the precautions on the back before filling in this page) S11279 A7 B7 5. Description of invention ()) Conductive polycrystalline silicon layer or similar material with vertical side wall layer. The pattern of this conductive layer is selected to be in the source / drain area of the plane • and formed at the position of the field effect transistor channel. A side wall insulating layer can be formed on the vertical side wall layer as described in the example in the previous paragraph. This sidewall layer can be doped with a conductive dopant. The gate dielectric layer is formed on the surface of the channel. The source / drain regions and the shallow doped regions are preferably formed by the thermal energy at the same time from the conductive first polycrystalline silicon layer or the like and the position of the insulating sidewall layer. The intended gate is formed above the gate dielectric layer and forms different elements electrically connected to the field effect transistor device. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) The above method for forming an automatic alignment device cannot prevent the etching material from invading the substrate location, so it may cause Critical areas of the substrate surface above the channel are damaged. During the formation of the sidewall layer by anisotropic ion etching and during the etching of the heavily doped conductive layer of the opposite auto-alignment technique, it is difficult to control to stop the etching at an appropriate time without damaging the substrate. A solution to the problem of forming bipolar transistors is shown in US Patent No. 5,162,245 of FAV R E AU. However, the selective growth technology of polycrystalline silicon described by FAVREAU may not achieve complete selectivity, resulting in the formation of polycrystalline silicon or polycrystalline silicon residue on top of the oxide layer 18. This undesired polysilicon may cause subsequent defects, electrical shorts, etc. [Summary of the Invention] Therefore, the object of the present invention is to improve the automatic alignment process and make the resulting structure prevent damage to the substrate. _ 5 _ " This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 311279 A7 B7 V. Description of the invention (γ) Another purpose of the invention is to provide bipolar and field effect electricity The improved automatic alignment process of the crystal. Another object of the present invention is to provide an improved automatic alignment process that can produce B I CMOS integrated circuits. According to the present invention, it is a method of automatically aligning transistors that form bipolar or field effects. A first insulating layer is formed on the surface of a single crystal semiconductor substrate. A second insulating layer is formed on the surface of the first insulating layer. A third insulating layer is formed on the surface of the second insulating layer. The first, second, and third insulating layers are patterned to form a protective block covering the first element position of the transistor. In the case of the bipolar transistor, the emitter position and the field effect transistor In the example, it is on the gate area. A heavily doped conductive layer of a conductive type is formed on a single crystal semiconductor substrate having the opposite conductive type and on the protection block. A fourth insulating layer is formed on the heavily doped conductive layer. The part of the heavily doped conductive layer and the fourth insulating layer located above the top level of the third insulating layer are then removed. The third insulating layer is removed by the protection block location. This structure is heated to form a heavily doped base part of a bipolar transistor * and a heavily doped source / drain part formed as a field effect transistor, through the heavily doped conductive layer outward Formed by diffusion. The exposed portion of the heavily doped conductive layer is oxidized into an oxidized sidewall layer adjacent to the protection block. The remaining protection blocks are then removed. A fifth insulating layer is formed at the position of the gate element when it is formed into a field effect transistor. A second conductive layer is formed on and above the fifth insulating layer for forming and patterning definitions; and each element of the transistor is electrically connected to the position of the transistor element and y -6- ^ (CNS) A4 specification (210X297mm) 5. The consumer consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs made the A7 B7 invention description (1) completed. An automatic alignment transistor circuit structure can also be conceived by the present invention. This structure includes a silicon semiconductor substrate with field isolation regions to isolate various surface regions of the semiconductor. A conductive heavily doped region has at least several semiconductor surface regions of opposite conductivity. The one directly above the heavily doped region | is a heavily doped conductive layer of the same conductivity and a doping source of the heavily doped region. At the inner periphery of the heavily doped conductive layer is an oxidized sidewall layer. Several mechanisms provide connections for the rest of the transistor. The proper electrical connection mechanism is to make the component form a complete horizontal circuit structure. Both bipolar and field-effect transistor device structures can be conceived. [Brief Description of Drawings] First to fourth circles: cross-sectional views showing a first embodiment method of an improved automatic alignment process for preventing damage to one of the substrate field effect transistors. Fig. 5 is a cross-sectional view of the structure of a bipolar electrical crystal produced by the method of the first embodiment. Figure 6: A cross-sectional view of a structure in which a B I CMOS structure is fabricated by combining the embodiments from the first circle to the fifth figure. Figures 7 and 8 are cross-sectional views of a method for forming a field isolation region in conjunction with the improved automatic alignment process of the present invention. [Description of the invention] Reference is now made to the first to fourth circles. It shows a self-aligning transistor in a high-density integrated circuit structure. The process is to describe the formation of an N-channel MOSFET circuit. However, it is understandable that the P channel field effect transistor-7- 'this paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) ___: ------ one-binding ______ binding ______ * · ^ (Please read the precautions on the back before filling out this page) 311279 Printed A7 B7 by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (Q) The body can simply make the difference between transistors and related areas The elements are formed with opposite polarities. The first series of steps involves the formation of protective blocks to prevent damage to the gate area of the substrate. The semiconductor substrate 10 may be composed of any known semiconductor materials of various types, but it is more preferably composed of silicon having a (100) silicon crystal characteristic. The substrate 10 in this example is doped P- as in the first figure. The first silicon oxide layer 12 is thermally grown by a conventional mechanism to a thickness of about 250-50A. A silicon nitride layer 14 is then deposited by chemical vapor deposition to a thickness of about 1,000 to 1,500 Å. The other silicon oxide layer 16 is formed by tetraethoxysilane (TEOS) type by chemical vapor deposition to a thickness of about 3500 ~ 400A. The three insulating layers are then defined using conventional optics and etching methods to form 0-N-0 (silicon dioxide-silicon nitride-silicon dioxide) protection blocks 18 as shown in the first figure. A layer 20 of polycrystalline silicon is now deposited overlying the substrate 10 and the protection block 18. Polycrystalline silicon 20 is then ion implanted with phosphorous, and in this embodiment an N-channel F ET device is formed. If a P channel F ET is to be formed, and the ion implantation is performed with an appropriate P-type dopant such as boron or boron fluoride (BF2). The thickness of the polycrystalline silicon layer is about 4500 ~ 5500A. _The silicon nitride layer 22 is now deposited by chemical vapor deposition to a thickness of approximately 1 0 0 0 ~ 2 0 0 0A. Referring now to the second figure, the layers 20 and 22 are etched with a photoresist planarization and etch-back process until the oxide layer 16 is exposed (the picture shows -8- This paper scale is applicable to Chinese national standards ( CNS) A4 specification (210X297mm) (Please read the precautions on the back before filling in this page) 丨 Packed. Ordered by the Central Bureau of Standards of the Ministry of Economic Affairs Printed by Beigong Consumer Cooperative 311279 A7 B7 V. Description of invention (7) has been removed . The etching technique used can be ion reaction etching using chemical components such as CF4 'c 2 F 6 and 〇2 (the fluorine component provides a high etching rate for polycrystalline silicon and the oxygen provides a photoresist and a high etching rate > Or use chemical mechanical polishing. In the second figure, it can be seen that a part of the polycrystalline silicon layer 20 is exposed between the protection block 18 and the silicon nitride 22. The oxide layer 16 is Use HF at a ratio of 10: 1 and a wet etch at a temperature of about 25 ° C. The N + source / drain region 2 3 is now about 9 0 0 ~ 9 for the second structure Annealing at 50 ° C until the N + junction forms about 0.2 to 0.3 microns below the surface. The annealing step is performed in a 5% oxygen and nitrogen environment for about 30 to 40 minutes. Referring to the third figure, the silicon nitride layer 22 is used as a photomask during the oxidation of polycrystalline silicon 20. It is used to form an oxidized sidewall layer 24. The oxidation step is at a temperature of about 9 0 0 ~ 1 0 0 It takes about 6 0 ~ 1 2 0 minutes in an oxygen environment at 0 ° C. The formed side wall layer 24 has a thickness of about 2 5 0 0 ~ 3 5 0 0A. This side wall layer can be oxidized at the edge of the channel The position results in an asymptotic junction profile, which forms a depth of about 0.05 ~ 0.1 microns deeper than the unoxidized area. This forms a shallow doped drain (LDD) structure that provides better hot carrier performance. The dashed line shows the junction before the polycrystalline silicon is oxidized, and the solid line shows the junction after it moves during oxidation. The thickness of the sidewall layer can be controlled by changing the process parameters to form a channel length (ie, the protection block 18 The base area below) can be smaller than the optical limit and form a pair of sub-micron devices -9- ^ This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -------- ^ —installed-- ---- Subscribe ----- I line (please read the note Ϋ on the back before filling in this page) 11279 A7 ________ B7 _ printed by the Peking Consumer Cooperative of the Ministry of Economic Affairs of the Central Government 5. ) Manufacturing extremely important concepts. The silicon nitride layer 22 provides a better technology than the US Patent No. 5, 1 26, 2 4 5 case is that the thickness of the polycrystalline silicon 20 can be protected during the oxidation period. This thickness is extremely important for the resistance of the polycrystalline silicon sheet. However, in the conventional technology, there is no silicon nitride It is necessary to choose between the impedance of the chip and the required thickness of the polycrystalline silicon to produce the required polycrystalline silicon oxide layer. Now refer to the fourth figure 1 4 and the oxide layer 12 are etched away, and the gate structure of the MOSFET device is completed. The silicon nitride layer 14 is carried out using phosphoric acid at a temperature of about 1 60 ~ 1 90 ° C for about 40 ~ 1 0 0 minutes Wet etching is carried out to remove. The thin pad oxide layer 12 is then removed by a wet etching and a thin sacrificial oxide layer with a thickness of about 150-50 A is grown in a dry oxygen environment to remove any bit Type KO 0 I defects in the channel area. This sacrificial oxide layer is then removed by wet etching in a 50: 1 hydrofluoric acid solution. Finally, the gate oxide layer 26 is used at a temperature of approximately 9 2 0 ~ 9 6 0 ° C (TRANS- LC) Thermal growth under LC and oxygen environment. The gate electrode 26 of the field-effect transistor shown in the fourth figure is formed overlying the gate dielectric layer and pattern by conventional optical and etching techniques. The gate electrode is formed of polycrystalline silicon and deposited by low-pressure chemical vapor deposition. The thickness of the gate layer 26 is about 3 0 0 0 ~ 4 0 0 0 A. A higher metallurgical layer (not shown) passes through the polycrystalline silicon layer 20 and the gate 26 to contact the source / drain region. This metallurgical layer is more suitable for aluminum -10- a paper standard applicable to the Chinese National Standard (CNS) A4 specifications (210X 297 mm) a pan binding * line (please read the precautions on the back before filling this page) A7 S11279 B7 V. Description of invention (?) Or similar material. The protection and insulation between the metallurgical layers can be accomplished by sputtering or plasma deposition of silicon oxide or similar materials. The gate area of the F ET device of the present invention is protected by silicon nitride, and it is absolutely not exposed to the outside, which will lead to polycrystalline silicon etching or the ion reaction etching of the oxide layer sidewall of the conventional technology. * 1 such as 1 to prevent the main FET device The base area of the channel area is damaged. Referring now to the fifth figure, a vertical NPN bipolar integrated circuit structure formed by a manufacturing method different from the first to fourth embodiments is shown. A vertical PNP bipolar structure is known by familiarity with this technique. Of course, it can be made by changing the conductive characteristics of the area involved in the process. This bipolar embodiment is implemented in a manner similar to the first embodiment, and shows the same elements of the two embodiments with the same numerals. However, the only difference is that the N-sub-collector 32 and the N + epitaxial layer 30 are required to be located on the P-substrate to form the substrate 10 of the fifth embodiment. As is known in the art, the epitaxial layer is formed on the entire P-substrate. An N-region is formed in the substrate at the location where the bipolar device is formed and before the epitaxial layer grows, and the N-sub-collector region is formed during the growth and outward diffusion of the epitaxial layer. In addition, in the processes from the first circle to the fourth figure, except that the layer 20 is doped with an opposite conductivity (P +) applied to the first embodiment and the P + region 3 is formed by a similar outward diffusion process 4. Except for forming the external base 34 of the bipolar transistor, the rest are the same as those forming the NPN structure. The internal base region 4 6 is also implanted through a boron ion. The paper size is 11- 〆This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) n ~-I In ml In m ^^ 1 m IIII n J (please read the precautions on the back before filling this page) Printed by the Ministry of Economy Central Standards Bureau employee consumer cooperatives Printed by the Ministry of Economics Central Standards Bureau employee consumer cooperatives A7 B7 5. Invention description (h) Oxide layer This area is formed after the thin pad oxide layer 12 is etched. The collector contact region 42 is formed as the emitter contact region 44 is formed at the same time in the same way as the gate electrode is formed in the first embodiment. The emitter contact region 44 is implanted with arsenic (or BF2 material in the case of a PNP structure), and the emitter region 48 is heated through a heating cycle of about 900 ° C for 30 minutes to disperse. The arsenic is doped and forms the shallow junction. The last one different from the F ET process is that the gate oxide layer in the bipolar emitter region is removed by wet etching before the polycrystalline silicon emitter contact region 44 is formed. If the embodiment of the first picture to the fourth picture is used, that means that the embodiment of the fifth picture requires a higher metallurgical layer (not shown) to contact the transistor element. That is, the contact emitter 44 The pole contact layer 20 and the collector 42. The metallurgical layer is preferably aluminum or similar material. The metallurgical layers need protection and insulation similar to the first embodiment. In the foregoing two embodiments, the field isolation region separating each active transistor structure may be formed by other conventional methods. Conventional techniques are local silicon oxide (LOCOS) and are usually implemented before the transistor regions are formed. However, as shown in the seventh and eighth figures, the field isolation region can be replaced by etching the local position of the silicon nitride layer 22 of the transistor region to form the opening 60, and the sidewall layer 2 is formed by oxidation During the 4th period, the field isolation region 62 is formed by polysilicon oxidation. This eliminates the LOCOS process steps. In the embodiments shown in the first picture to the fourth picture and the fifth picture, they can also be combined as shown in the sixth picture, and can be used for BIC MOS. It is shown as a paper standard applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) -------- 1 -installed ------ order ----- J line (please read first (Notes on the back and then fill in this page) ^ 11279 * A7 B7 V. Description of the invention (i I) NMO S field effect transistors are regarded as _NP N bipolar devices on the same substrate surface. Other combinations, such as a PMOS FET and a PNP bipolar device, can be formed as known to those skilled in the art. The present invention is specifically shown and described with reference to the preferred embodiments, and those skilled in the art can understand various changes in types and details without departing from the spirit and scope of the present invention. --I-I-ILI _ _ _ I n. ^ 1 TI--I _ j Quan US., Νδ system (please read the notes on the back before filling this page) Printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs -13- This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm)