JPH0774124A - Ion implantation prevention - Google Patents
Ion implantation preventionInfo
- Publication number
- JPH0774124A JPH0774124A JP3043595A JP4359591A JPH0774124A JP H0774124 A JPH0774124 A JP H0774124A JP 3043595 A JP3043595 A JP 3043595A JP 4359591 A JP4359591 A JP 4359591A JP H0774124 A JPH0774124 A JP H0774124A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- ion implantation
- silicon
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005468 ion implantation Methods 0.000 title abstract description 25
- 230000002265 prevention Effects 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 abstract description 31
- 230000007547 defect Effects 0.000 abstract description 10
- 230000000903 blocking effect Effects 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010419 fine particle Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造工程
に使用するイオン注入阻止方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation blocking method used in a semiconductor device manufacturing process.
【０００２】[0002]
【従来の技術】従来、高エネルギーイオン注入阻止物質
として、Ｗ（タングステン）、Ｔｉ（チタン）等の金属
材料が提案されているが、詳細な技術は明らかでない。2. Description of the Related Art Heretofore, a metal material such as W (tungsten) or Ti (titanium) has been proposed as a high energy ion implantation inhibiting substance, but the detailed technique is not clear.
【０００３】また、イオン注入を阻止すべき部分に、金
属膜やフォトレジストを形成する従来の方法では、以下
のような問題がある。Further, the conventional method of forming a metal film or a photoresist on a portion where the ion implantation should be blocked has the following problems.
【０００４】[0004]
【発明が解決しようとする課題】すなわち、上記フォト
レジストを使用する技術においては、フォトレジストの
厚さを薄くすることができないので、イオン注入阻止領
域および深さを正確に制御することができない。フォト
レジストをマスクとしてイオン注入するとフォトレジス
トが変質したり、不要な微粒子が混入する問題もある。That is, in the technique using the photoresist, the thickness of the photoresist cannot be reduced, so that the ion implantation blocking region and the depth cannot be accurately controlled. When ions are implanted using the photoresist as a mask, there are problems that the photoresist is deteriorated and unnecessary fine particles are mixed.
【０００５】また、ＷやＴｉ等の金属材料を使用する場
合は、当該金属と、窒化シリコン膜や酸化シリコン膜と
の各膨張係数が異なることにより、シリコンウェハに欠
陥が生じることがあった。さらに、阻止層である金属膜
を除去するときにウェハ表面に損傷が生じ、望む素子の
特性を得ることができないことがあった。Further, when a metal material such as W or Ti is used, a defect may occur in the silicon wafer due to the difference in expansion coefficient between the metal and the silicon nitride film or the silicon oxide film. Furthermore, when the metal film that is the blocking layer is removed, the wafer surface may be damaged and the desired device characteristics may not be obtained.
【０００６】本発明の目的は、上記の従来の問題を解消
し、イオン注入阻止領域および深さを正確に制御するこ
とができ、ウェハに欠陥や損傷が生じるのを抑制するこ
とができるイオン注入阻止方法を提供することにある。An object of the present invention is to solve the above-mentioned conventional problems, to accurately control the ion implantation blocking region and depth, and to suppress the occurrence of defects and damages on the wafer. To provide a blocking method.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明のイオン注入阻止方法は、シリコン基板上に
第１の酸化シリコン膜を設ける工程と、前記第１の酸化
シリコン膜上に第１の窒化シリコン膜を設ける工程と、
前記第１の窒化シリコン膜上に第２の酸化シリコン膜を
設ける工程と、前記第２の酸化シリコン膜上に第２の窒
化シリコン膜を設ける工程と、イオンを注入すべき部分
の前記第２の窒化シリコン膜と前記第２の酸化シリコン
膜を選択的に除去する工程と、前記シリコン基板表面に
イオンを注入する工程とを含むことを特徴とする。In order to achieve the above object, an ion implantation blocking method of the present invention comprises a step of providing a first silicon oxide film on a silicon substrate, and a step of providing the first silicon oxide film on the first silicon oxide film. Providing a first silicon nitride film,
Providing a second silicon oxide film on the first silicon nitride film; providing a second silicon nitride film on the second silicon oxide film; And a step of selectively removing the second silicon oxide film and a step of implanting ions into the surface of the silicon substrate.
【０００８】[0008]
【作用】本発明では、イオン注入阻止物質として窒化シ
リコン膜を使用するので、薄い厚さで阻止作用を行うこ
とができ、従って、イオン注入阻止領域および深さを正
確に制御することができる。また、膨張係数の差に起因
するウェハの欠陥の発生を抑制することができる。ま
た、阻止層を除去するときにウェハ表面に損傷が生じな
い。その結果、高エネルギーイオン注入時に発生した基
板表面の欠陥をなくすための別途の工程（アニール工
程）が不要となる。In the present invention, since the silicon nitride film is used as the ion implantation blocking material, the blocking action can be performed with a small thickness, and therefore the ion implantation blocking region and the depth can be accurately controlled. Further, it is possible to suppress the occurrence of wafer defects caused by the difference in expansion coefficient. Also, the wafer surface is not damaged when the blocking layer is removed. As a result, a separate process (annealing process) for eliminating defects on the surface of the substrate generated during high-energy ion implantation becomes unnecessary.
【０００９】[0009]
【実施例】以下、添付図面を参照して本発明の実施例を
詳細に説明する。図１Ａ〜図１Ｌは、本発明のイオン注
入阻止方法の一実施例を示す工程断面図である。Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 1A to 1L are process sectional views showing an embodiment of the ion implantation blocking method of the present invention.
【００１０】まず、公知の技術を使用して、シリコン基
板７上に応力緩和用の第１の酸化シリコン（ＳｉＯ2）
膜２を形成する。次に、選択酸化を行うための第１の窒
化シリコン（Ｓｉ3Ｎ4）膜３を選択的に形成する。次い
で、シリコン基板７の酸化を行い、フィールド酸化膜１
（ＳｉＯ2）を形成する（図１Ａ参照）。First, the first silicon oxide (SiO 2 ) for stress relaxation is formed on the silicon substrate 7 using a known technique.
The film 2 is formed. Next, the first silicon nitride (Si 3 N 4 ) film 3 for selective oxidation is selectively formed. Then, the silicon substrate 7 is oxidized to form the field oxide film 1.
(SiO 2 ) is formed (see FIG. 1A).
【００１１】次に、第１の酸化シリコン膜２と窒化シリ
コン膜３上に低温で形成した応力緩和用の第２の酸化シ
リコン膜４を蒸着する。第２の酸化シリコン膜４と第１
の窒化シリコン膜３との膜厚の比率は約４：１であっ
た。なお、第２の酸化シリコン膜４の厚さは、後の工程
のイオン注入のエネルギーに合わせて形成する（図１Ｂ
参照）。Next, a stress relieving second silicon oxide film 4 formed at a low temperature is vapor-deposited on the first silicon oxide film 2 and the silicon nitride film 3. The second silicon oxide film 4 and the first
The film thickness ratio to the silicon nitride film 3 was about 4: 1. Note that the thickness of the second silicon oxide film 4 is formed in accordance with the energy of ion implantation in a later step (FIG. 1B).
reference).
【００１２】次に、第２の酸化シリコン膜４上にイオン
注入阻止用の第２の窒化シリコン膜５を蒸着する。な
お、第２の窒化シリコン膜５の厚さも後の工程のイオン
注入のエネルギーに合わせて形成する（図１Ｃ参照）。Next, a second silicon nitride film 5 for blocking ion implantation is deposited on the second silicon oxide film 4. Note that the thickness of the second silicon nitride film 5 is also formed in accordance with the energy of ion implantation in a later step (see FIG. 1C).
【００１３】次に、第２の窒化シリコン膜５上に公知の
フォトリソグラフィー技術によってフォトレジスト６を
被せた後、露光、現像し、パタン化する（図１Ｄ参
照）。Next, the second silicon nitride film 5 is covered with a photoresist 6 by a known photolithography technique, and then exposed, developed and patterned (see FIG. 1D).
【００１４】次に、窒化膜チャンバにおいてフォトレジ
スト６をマスクとして第２の窒化シリコン膜５をドライ
エッチングにより除去する。このとき、第２の窒化シリ
コン膜５とフォトレジスト６とのエッチング比率は、約
1.5：１であった（図１Ｅ参照）。Next, in the nitride film chamber, the second silicon nitride film 5 is removed by dry etching using the photoresist 6 as a mask. At this time, the etching ratio of the second silicon nitride film 5 and the photoresist 6 is about
It was 1.5: 1 (see FIG. 1E).
【００１５】次に、酸化膜チャンバにおいて同じフォト
レジスト６をマスクとして第２の酸化シリコン膜４をド
ライエッチングにより除去する。このとき、第２の酸化
シリコン膜４は厚さ約1000Å残留した。また、第２の酸
化シリコン膜４とフォトレジスト６とのエッチング比率
は、約３：１であった（図１Ｆ参照）。Next, in the oxide film chamber, the second silicon oxide film 4 is removed by dry etching using the same photoresist 6 as a mask. At this time, the second silicon oxide film 4 remained with a thickness of about 1000Å. The etching ratio between the second silicon oxide film 4 and the photoresist 6 was about 3: 1 (see FIG. 1F).
【００１６】次に、高エネルギーイオン注入時にフォト
レジスタ６が変質したり、不要な微粒子が混入しないよ
うにするため、フォトレジスト６を除去する（図１Ｇ参
照）。Next, the photoresist 6 is removed in order to prevent the deterioration of the photoresist 6 and the inclusion of unnecessary fine particles during the high energy ion implantation (see FIG. 1G).
【００１７】次に、基板全面に高エネルギーイオンを注
入する（符号８で示す）。このとき、注入エネルギーは
第２の酸化シリコン膜４の厚さ（1000Å）と第１の窒化
シリコン膜３の厚さと第１の酸化シリコン膜２の厚さを
考慮する（図１Ｈ参照）。Next, high energy ions are implanted into the entire surface of the substrate (indicated by reference numeral 8). At this time, the implantation energy considers the thickness of the second silicon oxide film 4 (1000Å), the thickness of the first silicon nitride film 3 and the thickness of the first silicon oxide film 2 (see FIG. 1H).
【００１８】次に、第２の窒化シリコン膜５を除去する
（図１Ｉ参照）。Next, the second silicon nitride film 5 is removed (see FIG. 1I).
【００１９】次に、第２の酸化シリコン膜４を除去する
（図１Ｊ参照）。Next, the second silicon oxide film 4 is removed (see FIG. 1J).
【００２０】次に、第１の窒化シリコン膜３を除去する
（図１Ｋ参照）。Next, the first silicon nitride film 3 is removed (see FIG. 1K).
【００２１】最後に、第１の酸化シリコン膜２を除去す
る（図１Ｌ参照）。Finally, the first silicon oxide film 2 is removed (see FIG. 1L).
【００２２】このように、本発明では、図２に概略的に
示すように、２層の窒化シリコン膜３、５と、２層の酸
化シリコン膜２、４を形成するが、応力緩和用の第１の
酸化シリコン膜２と選択酸化用の第１の窒化シリコン膜
３は既存の構造であり（ＬＯＣＯＳ）、その上に、応力
を緩和し、ウェハ表面の圧力を減少させるための第２の
酸化シリコン膜４とイオン注入阻止用の第２の窒化シリ
コン膜５を形成する。As described above, according to the present invention, the two layers of the silicon nitride films 3 and 5 and the two layers of the silicon oxide films 2 and 4 are formed as schematically shown in FIG. The first silicon oxide film 2 and the first silicon nitride film 3 for selective oxidation have an existing structure (LOCOS), and on top of that, a second silicon oxide film 2 for relaxing stress and reducing pressure on the wafer surface is formed. A silicon oxide film 4 and a second silicon nitride film 5 for blocking ion implantation are formed.
【００２３】上記の実施例では、イオン注入阻止物質と
して窒化シリコン膜５を使用したので、既存の設備を使
用して容易に工程を進行することができる。また、他の
材料（アルミニウム、フォトレジスト、酸化シリコン
膜）を使用する場合に比べて、はるかに薄い厚さで阻止
作用を行うことができ、イオン注入阻止領域および深さ
を正確に制御することができる。また、阻止物質として
窒化シリコン膜５を使用するので、膨張係数の差に起因
するウェハの欠陥の発生を抑制することができる。ま
た、阻止層を除去するときにウェハ表面に損傷が生じな
い。さらに、ウェハの欠陥の発生を抑制することができ
るので、高エネルギーイオン注入時に発生した基板表面
の欠陥をなくすための別途の工程（アニール工程）が不
要となる。In the above embodiment, since the silicon nitride film 5 is used as the ion implantation blocking material, the process can be easily advanced using the existing equipment. Moreover, compared with the case of using other materials (aluminum, photoresist, silicon oxide film), the blocking action can be performed with a much smaller thickness, and the ion implantation blocking region and the depth can be accurately controlled. You can Further, since the silicon nitride film 5 is used as the blocking material, it is possible to suppress the occurrence of wafer defects caused by the difference in expansion coefficient. Also, the wafer surface is not damaged when the blocking layer is removed. Furthermore, since it is possible to suppress the generation of defects on the wafer, a separate process (annealing process) for eliminating defects on the surface of the substrate generated at the time of high energy ion implantation becomes unnecessary.
【００２４】以上本発明を実施例に基づいて具体的に説
明したが、本発明は上記実施例に限定されるものではな
く、その要旨を逸脱しない範囲において種々変更可能で
あることは勿論である。例えば、本発明の方法は、例え
ば、ＣＣＤデバイスにおける素子特性を改善するための
高濃度不純物層、ＤＲＡＭのウェル、バイポーラ埋込み
層等種々の不純物層を形成するときに適用することがで
きる。また、メガエレクトロンボルトの高エネルギーイ
オン注入にも適用することができる。Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention. . For example, the method of the present invention can be applied, for example, when forming various impurity layers such as a high-concentration impurity layer for improving element characteristics in a CCD device, a DRAM well, and a bipolar buried layer. It can also be applied to high-energy ion implantation of mega electron volts.
【００２５】[0025]
【発明の効果】以上説明したように、本発明のイオン注
入阻止方法では、イオン注入阻止領域および深さを正確
に制御することができる。また、ウェハの欠陥や損傷の
発生を抑制することができる。さらに、基板表面の欠陥
をなくすための別途の工程を不要にすることができる。As described above, according to the ion implantation blocking method of the present invention, the ion implantation blocking region and the depth can be accurately controlled. Further, it is possible to suppress the occurrence of defects and damages on the wafer. Furthermore, a separate process for eliminating defects on the substrate surface can be eliminated.
【図１Ａ】本発明の一実施例を示す工程断面図である。FIG. 1A is a process sectional view showing an embodiment of the present invention.
【図１Ｂ】本発明の一実施例を示す工程断面図である。FIG. 1B is a process sectional view showing an embodiment of the present invention.
【図１Ｃ】本発明の一実施例を示す工程断面図である。FIG. 1C is a process sectional view showing an embodiment of the present invention.
【図１Ｄ】本発明の一実施例を示す工程断面図である。FIG. 1D is a process sectional view showing an embodiment of the present invention.
【図１Ｅ】本発明の一実施例を示す工程断面図である。FIG. 1E is a process sectional view showing an embodiment of the present invention.
【図１Ｆ】本発明の一実施例を示す工程断面図である。FIG. 1F is a process sectional view showing an embodiment of the present invention.
【図１Ｇ】本発明の一実施例を示す工程断面図である。FIG. 1G is a process sectional view showing an embodiment of the present invention.
【図１Ｈ】本発明の一実施例を示す工程断面図である。FIG. 1H is a process sectional view showing an embodiment of the present invention.
【図１Ｉ】本発明の一実施例を示す工程断面図である。FIG. 1I is a process sectional view showing an embodiment of the present invention.
【図１Ｊ】本発明の一実施例を示す工程断面図である。FIG. 1J is a process sectional view showing an example of the present invention.
【図１Ｋ】本発明の一実施例を示す工程断面図である。FIG. 1K is a process sectional view showing an embodiment of the present invention.
【図１Ｌ】本発明の一実施例を示す工程断面図である。FIG. 1L is a process sectional view showing an embodiment of the present invention.
【図２】本発明の概略構成を示す断面図である。FIG. 2 is a sectional view showing a schematic configuration of the present invention.
１…フィールド酸化膜、２…第１の酸化シリコン膜、３
…第１の窒化シリコン膜、４…第２の酸化シリコン膜、
５…第２の窒化シリコン膜、６…フォトレジスト、７…
シリコン基板、８…イオン注入。1 ... Field oxide film, 2 ... First silicon oxide film, 3
... first silicon nitride film, 4 ... second silicon oxide film,
5 ... Second silicon nitride film, 6 ... Photoresist, 7 ...
Silicon substrate, 8 ... Ion implantation.
Claims (1)
設ける工程と、前記第１の酸化シリコン膜上に第１の窒
化シリコン膜を設ける工程と、前記第１の窒化シリコン
膜上に第２の酸化シリコン膜を設ける工程と、前記第２
の酸化シリコン膜上に第２の窒化シリコン膜を設ける工
程と、イオンを注入すべき部分の前記第２の窒化シリコ
ン膜と前記第２の酸化シリコン膜を選択的に除去する工
程と、前記シリコン基板表面にイオンを注入する工程と
を含むことを特徴とするイオン注入阻止方法。1. A step of forming a first silicon oxide film on a silicon substrate, a step of forming a first silicon nitride film on the first silicon oxide film, and a step of forming a first silicon nitride film on the first silicon nitride film. A step of providing a second silicon oxide film, and the second step
Providing a second silicon nitride film on the silicon oxide film, the step of selectively removing the second silicon nitride film and the second silicon oxide film in a portion where ions are to be implanted, And a step of implanting ions on the surface of the substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900003165A KR930000876B1 (en) | 1990-03-09 | 1990-03-09 | HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM |
| KR1990-3165 | 1990-03-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0774124A true JPH0774124A (en) | 1995-03-17 |
| JP2524431B2 JP2524431B2 (en) | 1996-08-14 |
Family
ID=19296842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3043595A Expired - Fee Related JP2524431B2 (en) | 1990-03-09 | 1991-03-08 | Ion implantation blocking method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2524431B2 (en) |
| KR (1) | KR930000876B1 (en) |
| DE (1) | DE4107149C2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19611512A1 (en) | 1996-03-23 | 1997-09-25 | Pierburg Ag | Electrically powered air pump |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56105651A (en) * | 1980-01-28 | 1981-08-22 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS56148823A (en) * | 1980-04-21 | 1981-11-18 | Toshiba Corp | Production of planer type semiconductor device |
| JPS57128921A (en) * | 1981-02-02 | 1982-08-10 | Nec Corp | Manufacture of semiconductor element |
| JPS60247922A (en) * | 1984-05-23 | 1985-12-07 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS63117467A (en) * | 1986-11-05 | 1988-05-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2832388C2 (en) * | 1978-07-24 | 1986-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Process for the production of MNOS and MOS transistors in silicon gate technology on a semiconductor substrate |
| DE3133841A1 (en) * | 1981-08-27 | 1983-03-17 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS |
| US4466174A (en) * | 1981-12-28 | 1984-08-21 | Texas Instruments Incorporated | Method for fabricating MESFET device using a double LOCOS process |
| DE3662627D1 (en) * | 1985-06-03 | 1989-05-03 | Siemens Ag | Method of simultaneously producing bipolar and complementary mos transistors as a common silicon substrate |
-
1990
- 1990-03-09 KR KR1019900003165A patent/KR930000876B1/en not_active IP Right Cessation
-
1991
- 1991-03-06 DE DE4107149A patent/DE4107149C2/en not_active Expired - Fee Related
- 1991-03-08 JP JP3043595A patent/JP2524431B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56105651A (en) * | 1980-01-28 | 1981-08-22 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS56148823A (en) * | 1980-04-21 | 1981-11-18 | Toshiba Corp | Production of planer type semiconductor device |
| JPS57128921A (en) * | 1981-02-02 | 1982-08-10 | Nec Corp | Manufacture of semiconductor element |
| JPS60247922A (en) * | 1984-05-23 | 1985-12-07 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS63117467A (en) * | 1986-11-05 | 1988-05-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4107149C2 (en) | 1997-04-03 |
| JP2524431B2 (en) | 1996-08-14 |
| KR910017599A (en) | 1991-11-05 |
| DE4107149A1 (en) | 1991-09-12 |
| KR930000876B1 (en) | 1993-02-08 |
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