JP2524431B2 - Ion implantation blocking method - Google Patents
Ion implantation blocking methodInfo
- Publication number
- JP2524431B2 JP2524431B2 JP3043595A JP4359591A JP2524431B2 JP 2524431 B2 JP2524431 B2 JP 2524431B2 JP 3043595 A JP3043595 A JP 3043595A JP 4359591 A JP4359591 A JP 4359591A JP 2524431 B2 JP2524431 B2 JP 2524431B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon
- silicon oxide
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造工程
に使用するイオン注入阻止方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation blocking method used in a semiconductor device manufacturing process.
【０００２】[0002]
【従来の技術】従来、高エネルギーイオン注入阻止物質
として、Ｗ（タングステン）、Ｔｉ（チタン）等の金属
材料が提案されているが、詳細な技術は明らかでない。2. Description of the Related Art Heretofore, a metal material such as W (tungsten) or Ti (titanium) has been proposed as a high energy ion implantation inhibiting substance, but the detailed technique is not clear.
【０００３】また、イオン注入を阻止すべき部分に、金
属膜やフォトレジストを形成する従来の方法では、以下
のような問題がある。Further, the conventional method of forming a metal film or a photoresist on a portion where the ion implantation should be blocked has the following problems.
【０００４】[0004]
【発明が解決しようとする課題】すなわち、上記フォト
レジストを使用する技術においては、フォトレジストの
厚さを薄くすることができないので、イオン注入阻止領
域および深さを正確に制御することができない。フォト
レジストをマスクとしてイオン注入するとフォトレジス
トが変質したり、不要な微粒子が混入する問題もある。That is, in the technique using the photoresist, the thickness of the photoresist cannot be reduced, so that the ion implantation blocking region and the depth cannot be accurately controlled. When ions are implanted using the photoresist as a mask, there are problems that the photoresist is deteriorated and unnecessary fine particles are mixed.
【０００５】また、ＷやＴｉ等の金属材料を使用する場
合は、当該金属と、窒化シリコン膜や酸化シリコン膜と
の各膨張係数が異なることにより、シリコンウェハに欠
陥が生じることがあった。さらに、阻止層である金属膜
を除去するときにウェハ表面に損傷が生じ、望む素子の
特性を得ることができないことがあった。Further, when a metal material such as W or Ti is used, a defect may occur in the silicon wafer due to the difference in expansion coefficient between the metal and the silicon nitride film or the silicon oxide film. Furthermore, when the metal film that is the blocking layer is removed, the wafer surface may be damaged and the desired device characteristics may not be obtained.
【０００６】本発明の目的は、上記の従来の問題を解消
し、イオン注入阻止領域および深さを正確に制御するこ
とができ、ウェハに欠陥や損傷が生じるのを抑制するこ
とができるイオン注入阻止方法を提供することにある。An object of the present invention is to solve the above-mentioned conventional problems, to accurately control the ion implantation blocking region and depth, and to suppress the occurrence of defects and damages on the wafer. To provide a blocking method.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明のイオン注入阻止方法は、シリコン基板
（７）上に、ＬＯＣＯＳ形成応力緩和用バッファ膜とし
て第１の酸化シリコン膜（２）を設ける工程と、前記第
１の酸化シリコン膜（２）上に、ＬＯＣＯＳ形成選択酸
化用の第１の窒化シリコン膜（３）を選択的に設ける工
程と、前記第１の窒化シリコン膜（３）を酸化マスクと
して前記シリコン基板（７）の酸化を行い、フィールド
酸化膜（１）を設ける工程と、前記第１の窒化シリコン
膜（３）上に、形成すべきイオン注入領域の深さを考慮
した膜厚を有する応力緩和用の第２の酸化シリコン膜
（４）を設ける工程と、前記第２の酸化シリコン膜
（４）上に、イオン注入阻止用の第２の窒化シリコン膜
（５）を設ける工程と、イオンを注入すべき部分を開口
したレジスト膜（６）をエッチングマスクとして、前記
第２の窒化シリコン膜（５）をエッチングして、イオン
を注入すべき部分を選択的に全膜厚除去する工程と、イ
オンを注入すべき部分の前記第２の酸化シリコン膜
（４）を所定の膜厚残存するように選択的に除去する工
程と、前記レジスト膜（６）を除去した後、前記第２の
窒化シリコン膜（５）をイオン注入マスクとして、前記
第１の酸化シリコン膜（２）、前記第１の窒化シリコン
膜（３）、前記第２の酸化シリコン膜（４）を通して、
前記シリコン基板（７）表面にイオンを注入する工程
と、前記第２の窒化シリコン膜（５）、前記第２の酸化
シリコン膜（４）、前記第１の窒化シリコン膜（３）、
前記第１の酸化シリコン膜（２）を除去する工程とを含
むことを特徴とする。In order to achieve the above object, the ion implantation blocking method of the present invention is a silicon substrate.
A buffer film for relaxing LOCOS formation stress is formed on (7).
Forming a first silicon oxide film (2),
LOCOS formation selective acid on the silicon oxide film (2) of No. 1
For selectively providing a first silicon nitride film (3) for chemical conversion
And the first silicon nitride film (3) as an oxidation mask.
Then, the silicon substrate (7) is oxidized to
Providing an oxide film (1) and the first silicon nitride
Consider the depth of the ion implantation region to be formed on the film (3)
Relaxation second silicon oxide film having different thickness
The step of providing (4), and the second silicon oxide film
(4) A second silicon nitride film for blocking ion implantation
Step (5) is provided, and the portion where ions are to be implanted is opened
Using the resist film (6) formed as an etching mask,
The second silicon nitride film (5) is etched to remove ions
The step of selectively removing the entire thickness of the portion where
The second silicon oxide film in a portion where ON should be injected
A process for selectively removing (4) so that a predetermined film thickness remains.
Then, after removing the resist film (6), the second film is removed.
Using the silicon nitride film (5) as an ion implantation mask,
First silicon oxide film (2), the first silicon nitride
Through the film (3) and the second silicon oxide film (4),
Step of implanting ions into the surface of the silicon substrate (7)
And the second silicon nitride film (5) and the second oxide film.
A silicon film (4), the first silicon nitride film (3),
And a step of removing the first silicon oxide film (2) .
【０００８】[0008]
【作用】本発明では、イオン注入阻止物質として窒化シ
リコン膜を使用するので、薄い厚さで阻止作用を行うこ
とができ、従って、イオン注入阻止領域および深さを正
確に制御することができる。また、膨張係数の差に起因
するウェハの欠陥の発生を抑制することができる。ま
た、阻止層を除去するときにウェハ表面に損傷が生じな
い。その結果、高エネルギーイオン注入時に発生した基
板表面の欠陥をなくすための別途の工程（アニール工
程）が不要となる。In the present invention, since the silicon nitride film is used as the ion implantation blocking material, the blocking action can be performed with a small thickness, and therefore the ion implantation blocking region and the depth can be accurately controlled. Further, it is possible to suppress the occurrence of wafer defects caused by the difference in expansion coefficient. Also, the wafer surface is not damaged when the blocking layer is removed. As a result, a separate process (annealing process) for eliminating defects on the surface of the substrate generated during high-energy ion implantation becomes unnecessary.
【０００９】[0009]
【実施例】以下、添付図面を参照して本発明の実施例を
詳細に説明する。図１Ａ〜図１Ｌは、本発明のイオン注
入阻止方法の一実施例を示す工程断面図である。Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 1A to 1L are process sectional views showing an embodiment of the ion implantation blocking method of the present invention.
【００１０】まず、公知の技術を使用して、シリコン基
板７上に応力緩和用の第１の酸化シリコン（ＳｉＯ2）
膜２を形成する。次に、選択酸化を行うための第１の窒
化シリコン（Ｓｉ3Ｎ4）膜３を選択的に形成する。次い
で、シリコン基板７の酸化を行い、フィールド酸化膜１
（ＳｉＯ2）を形成する（図１Ａ参照）。First, the first silicon oxide (SiO 2 ) for stress relaxation is formed on the silicon substrate 7 using a known technique.
The film 2 is formed. Next, the first silicon nitride (Si 3 N 4 ) film 3 for selective oxidation is selectively formed. Then, the silicon substrate 7 is oxidized to form the field oxide film 1.
(SiO 2 ) is formed (see FIG. 1A).
【００１１】次に、第１の酸化シリコン膜２と窒化シリ
コン膜３上に低温で形成した応力緩和用の第２の酸化シ
リコン膜４を蒸着する。第２の酸化シリコン膜４と第１
の窒化シリコン膜３との膜厚の比率は約４：１であっ
た。なお、第２の酸化シリコン膜４の厚さは、後の工程
のイオン注入のエネルギーに合わせて形成する（図１Ｂ
参照）。Next, a stress relieving second silicon oxide film 4 formed at a low temperature is vapor-deposited on the first silicon oxide film 2 and the silicon nitride film 3. The second silicon oxide film 4 and the first
The film thickness ratio to the silicon nitride film 3 was about 4: 1. Note that the thickness of the second silicon oxide film 4 is formed in accordance with the energy of ion implantation in a later step (FIG. 1B).
reference).
【００１２】次に、第２の酸化シリコン膜４上にイオン
注入阻止用の第２の窒化シリコン膜５を蒸着する。な
お、第２の窒化シリコン膜５の厚さも後の工程のイオン
注入のエネルギーに合わせて形成する（図１Ｃ参照）。Next, a second silicon nitride film 5 for blocking ion implantation is deposited on the second silicon oxide film 4. Note that the thickness of the second silicon nitride film 5 is also formed in accordance with the energy of ion implantation in a later step (see FIG. 1C).
【００１３】次に、第２の窒化シリコン膜５上に公知の
フォトリソグラフィー技術によってフォトレジスト６を
被せた後、露光、現像し、パタン化する（図１Ｄ参
照）。Next, the second silicon nitride film 5 is covered with a photoresist 6 by a known photolithography technique, and then exposed, developed and patterned (see FIG. 1D).
【００１４】次に、窒化膜チャンバにおいてフォトレジ
スト６をマスクとして第２の窒化シリコン膜５をドライ
エッチングにより除去する。このとき、第２の窒化シリ
コン膜５とフォトレジスト６とのエッチング比率は、約
1.5：１であった（図１Ｅ参照）。Next, in the nitride film chamber, the second silicon nitride film 5 is removed by dry etching using the photoresist 6 as a mask. At this time, the etching ratio of the second silicon nitride film 5 and the photoresist 6 is about
It was 1.5: 1 (see FIG. 1E).
【００１５】次に、酸化膜チャンバにおいて同じフォト
レジスト６をマスクとして第２の酸化シリコン膜４をド
ライエッチングにより除去する。このとき、第２の酸化
シリコン膜４は厚さ約1000Å残留した。また、第２の酸
化シリコン膜４とフォトレジスト６とのエッチング比率
は、約３：１であった（図１Ｆ参照）。Next, in the oxide film chamber, the second silicon oxide film 4 is removed by dry etching using the same photoresist 6 as a mask. At this time, the second silicon oxide film 4 remained with a thickness of about 1000Å. The etching ratio between the second silicon oxide film 4 and the photoresist 6 was about 3: 1 (see FIG. 1F).
【００１６】次に、高エネルギーイオン注入時にフォト
レジスタ６が変質したり、不要な微粒子が混入しないよ
うにするため、フォトレジスト６を除去する（図１Ｇ参
照）。Next, the photoresist 6 is removed in order to prevent the deterioration of the photoresist 6 and the inclusion of unnecessary fine particles during the high energy ion implantation (see FIG. 1G).
【００１７】次に、基板全面に高エネルギーイオンを注
入する（符号８で示す）。このとき、注入エネルギーは
第２の酸化シリコン膜４の厚さ（1000Å）と第１の窒化
シリコン膜３の厚さと第１の酸化シリコン膜２の厚さを
考慮する（図１Ｈ参照）。Next, high energy ions are implanted into the entire surface of the substrate (indicated by reference numeral 8). At this time, the implantation energy considers the thickness of the second silicon oxide film 4 (1000Å), the thickness of the first silicon nitride film 3 and the thickness of the first silicon oxide film 2 (see FIG. 1H).
【００１８】次に、第２の窒化シリコン膜５を除去する
（図１Ｉ参照）。Next, the second silicon nitride film 5 is removed (see FIG. 1I).
【００１９】次に、第２の酸化シリコン膜４を除去する
（図１Ｊ参照）。Next, the second silicon oxide film 4 is removed (see FIG. 1J).
【００２０】次に、第１の窒化シリコン膜３を除去する
（図１Ｋ参照）。Next, the first silicon nitride film 3 is removed (see FIG. 1K).
【００２１】最後に、第１の酸化シリコン膜２を除去す
る（図１Ｌ参照）。Finally, the first silicon oxide film 2 is removed (see FIG. 1L).
【００２２】このように、本発明では、図２に概略的に
示すように、２層の窒化シリコン膜３、５と、２層の酸
化シリコン膜２、４を形成するが、応力緩和用の第１の
酸化シリコン膜２と選択酸化用の第１の窒化シリコン膜
３は既存の構造であり（ＬＯＣＯＳ）、その上に、応力
を緩和し、ウェハ表面の圧力を減少させるための第２の
酸化シリコン膜４とイオン注入阻止用の第２の窒化シリ
コン膜５を形成する。As described above, according to the present invention, the two layers of the silicon nitride films 3 and 5 and the two layers of the silicon oxide films 2 and 4 are formed as schematically shown in FIG. The first silicon oxide film 2 and the first silicon nitride film 3 for selective oxidation have an existing structure (LOCOS), and on top of that, a second silicon oxide film 2 for relaxing stress and reducing pressure on the wafer surface is formed. A silicon oxide film 4 and a second silicon nitride film 5 for blocking ion implantation are formed.
【００２３】上記の実施例では、イオン注入阻止物質と
して窒化シリコン膜５を使用したので、既存の設備を使
用して容易に工程を進行することができる。また、他の
材料（アルミニウム、フォトレジスト、酸化シリコン
膜）を使用する場合に比べて、はるかに薄い厚さで阻止
作用を行うことができ、イオン注入阻止領域および深さ
を正確に制御することができる。また、阻止物質として
窒化シリコン膜５を使用するので、膨張係数の差に起因
するウェハの欠陥の発生を抑制することができる。ま
た、阻止層を除去するときにウェハ表面に損傷が生じな
い。さらに、ウェハの欠陥の発生を抑制することができ
るので、高エネルギーイオン注入時に発生した基板表面
の欠陥をなくすための別途の工程（アニール工程）が不
要となる。In the above embodiment, since the silicon nitride film 5 is used as the ion implantation blocking material, the process can be easily advanced using the existing equipment. Moreover, compared with the case of using other materials (aluminum, photoresist, silicon oxide film), the blocking action can be performed with a much smaller thickness, and the ion implantation blocking region and the depth can be accurately controlled. You can Further, since the silicon nitride film 5 is used as the blocking material, it is possible to suppress the occurrence of wafer defects caused by the difference in expansion coefficient. Also, the wafer surface is not damaged when the blocking layer is removed. Further, since it is possible to suppress the generation of defects on the wafer, a separate process (annealing process) for eliminating defects on the substrate surface generated at the time of high energy ion implantation becomes unnecessary.
【００２４】以上本発明を実施例に基づいて具体的に説
明したが、本発明は上記実施例に限定されるものではな
く、その要旨を逸脱しない範囲において種々変更可能で
あることは勿論である。例えば、本発明の方法は、例え
ば、ＣＣＤデバイスにおける素子特性を改善するための
高濃度不純物層、ＤＲＡＭのウェル、バイポーラ埋込み
層等種々の不純物層を形成するときに適用することがで
きる。また、メガエレクトロンボルトの高エネルギーイ
オン注入にも適用することができる。Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention. . For example, the method of the present invention can be applied, for example, when forming various impurity layers such as a high-concentration impurity layer for improving element characteristics in a CCD device, a DRAM well, and a bipolar buried layer. It can also be applied to high-energy ion implantation of mega electron volts.
【００２５】[0025]
【発明の効果】以上説明したように、本発明のイオン注
入阻止方法では、イオン注入阻止領域および深さを正確
に制御することができる。また、ウェハの欠陥や損傷の
発生を抑制することができる。さらに、基板表面の欠陥
をなくすための別途の工程を不要にすることができる。As described above, according to the ion implantation blocking method of the present invention, the ion implantation blocking region and the depth can be accurately controlled. Further, it is possible to suppress the occurrence of defects and damages on the wafer. Furthermore, a separate process for eliminating defects on the substrate surface can be eliminated.
【図１Ａ】本発明の一実施例を示す工程断面図である。FIG. 1A is a process sectional view showing an embodiment of the present invention.
【図１Ｂ】本発明の一実施例を示す工程断面図である。FIG. 1B is a process sectional view showing an embodiment of the present invention.
【図１Ｃ】本発明の一実施例を示す工程断面図である。FIG. 1C is a process sectional view showing an embodiment of the present invention.
【図１Ｄ】本発明の一実施例を示す工程断面図である。FIG. 1D is a process sectional view showing an embodiment of the present invention.
【図１Ｅ】本発明の一実施例を示す工程断面図である。FIG. 1E is a process sectional view showing an embodiment of the present invention.
【図１Ｆ】本発明の一実施例を示す工程断面図である。FIG. 1F is a process sectional view showing an embodiment of the present invention.
【図１Ｇ】本発明の一実施例を示す工程断面図である。FIG. 1G is a process sectional view showing an embodiment of the present invention.
【図１Ｈ】本発明の一実施例を示す工程断面図である。FIG. 1H is a process sectional view showing an embodiment of the present invention.
【図１Ｉ】本発明の一実施例を示す工程断面図である。FIG. 1I is a process sectional view showing an embodiment of the present invention.
【図１Ｊ】本発明の一実施例を示す工程断面図である。FIG. 1J is a process sectional view showing an example of the present invention.
【図１Ｋ】本発明の一実施例を示す工程断面図である。FIG. 1K is a process sectional view showing an embodiment of the present invention.
【図１Ｌ】本発明の一実施例を示す工程断面図である。FIG. 1L is a process sectional view showing an embodiment of the present invention.
【図２】本発明の概略構成を示す断面図である。FIG. 2 is a sectional view showing a schematic configuration of the present invention.
１…フィールド酸化膜、２…第１の酸化シリコン膜、３
…第１の窒化シリコン膜、４…第２の酸化シリコン膜、
５…第２の窒化シリコン膜、６…フォトレジスト、７…
シリコン基板、８…イオン注入。1 ... Field oxide film, 2 ... First silicon oxide film, 3
... first silicon nitride film, 4 ... second silicon oxide film,
5 ... Second silicon nitride film, 6 ... Photoresist, 7 ...
Silicon substrate, 8 ... Ion implantation.
フロントページの続き (56)参考文献 特開 昭56−148823（ＪＰ，Ａ) 特開 昭60−247922（ＪＰ，Ａ) 特開 昭57−128921（ＪＰ，Ａ) 特開 昭63−117467（ＪＰ，Ａ) 特開 昭56−105651（ＪＰ，Ａ)Continuation of the front page (56) Reference JP-A-56-148823 (JP, A) JP-A-60-247922 (JP, A) JP-A-57-128921 (JP, A) JP-A-63-117467 (JP , A) JP-A-56-105651 (JP, A)
Claims (1)
応力緩和用バッファ膜として第１の酸化シリコン膜
（２）を設ける工程と、 前記第１の酸化シリコン膜（２）上に、ＬＯＣＯＳ形成
選択酸化用の第１の窒化シリコン膜（３）を選択的に設
ける工程と、 前記第１の窒化シリコン膜（３）を酸化マスクとして前
記シリコン基板（７）の酸化を行い、フィールド酸化膜
（１）を設ける工程と、 前記第１の窒化シリコン膜（３）上に、形成すべきイオ
ン注入領域の深さを考慮した膜厚を有する応力緩和用の
第２の酸化シリコン膜（４）を設ける工程と、 前記第２の酸化シリコン膜（４）上に、イオン注入阻止
用の第２の窒化シリコン膜（５）を設ける工程と、 イオンを注入すべき部分を開口したレジスト膜（６）を
エッチングマスクとして、前記第２の窒化シリコン膜
（５）をエッチングして、イオンを注入すべき部分を選
択的に全膜厚除去する工程と、 イオンを注入すべき部分の前記第２の酸化シリコン膜
（４）を所定の膜厚残存するように選択的に除去する工
程と、 前記レジスト膜（６）を除去した後、前記第２の窒化シ
リコン膜（５）をイオン注入マスクとして、前記第１の
酸化シリコン膜（２）、前記第１の窒化シリコン膜
（３）、前記第２の酸化シリコン膜（４）を通して、前
記シリコン基板（７）表面にイオンを注入する工程と、 前記第２の窒化シリコン膜（５）、前記第２の酸化シリ
コン膜（４）、前記第１の窒化シリコン膜（３）、前記
第１の酸化シリコン膜（２）を除去する 工程とを含むこ
とを特徴とするイオン注入阻止方法。1. LOCOS formation on a silicon substrate (7)
First silicon oxide film as a buffer film for stress relaxation
(2) providing step and LOCOS formation on the first silicon oxide film (2)
A first silicon nitride film (3) for selective oxidation is selectively provided.
And using the first silicon nitride film (3) as an oxidation mask.
The silicon substrate (7) is oxidized to form a field oxide film.
The step of providing (1) and the ion to be formed on the first silicon nitride film (3).
For stress relaxation with a film thickness that considers the depth of the implanted region
A step of providing a second silicon oxide film (4), and ion implantation blocking on the second silicon oxide film (4)
A step of providing a second silicon nitride film (5) for use and a resist film (6) having an opening at a portion where ions should be implanted.
The second silicon nitride film as an etching mask
Etch (5) to select the part where the ions should be implanted.
Selectively removing the entire film thickness, and the second silicon oxide film in a portion where ions should be implanted
A process for selectively removing (4) so that a predetermined film thickness remains.
And extent, after removing the resist film (6), the second nitride Shi
Using the recon film (5) as an ion implantation mask, the first
Silicon oxide film (2), the first silicon nitride film
(3), through the second silicon oxide film (4),
The step of implanting ions into the surface of the silicon substrate (7), the second silicon nitride film (5), the second silicon oxide film.
Con film (4), the first silicon nitride film (3), the
And a step of removing the first silicon oxide film (2) .
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1990-3165 | 1990-03-09 | ||
| KR1019900003165A KR930000876B1 (en) | 1990-03-09 | 1990-03-09 | HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0774124A JPH0774124A (en) | 1995-03-17 |
| JP2524431B2 true JP2524431B2 (en) | 1996-08-14 |
Family
ID=19296842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3043595A Expired - Fee Related JP2524431B2 (en) | 1990-03-09 | 1991-03-08 | Ion implantation blocking method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2524431B2 (en) |
| KR (1) | KR930000876B1 (en) |
| DE (1) | DE4107149C2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19611512A1 (en) | 1996-03-23 | 1997-09-25 | Pierburg Ag | Electrically powered air pump |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2832388C2 (en) * | 1978-07-24 | 1986-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Process for the production of MNOS and MOS transistors in silicon gate technology on a semiconductor substrate |
| JPS56105651A (en) * | 1980-01-28 | 1981-08-22 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS56148823A (en) * | 1980-04-21 | 1981-11-18 | Toshiba Corp | Production of planer type semiconductor device |
| JPS57128921A (en) * | 1981-02-02 | 1982-08-10 | Nec Corp | Manufacture of semiconductor element |
| DE3133841A1 (en) * | 1981-08-27 | 1983-03-17 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS |
| US4466174A (en) * | 1981-12-28 | 1984-08-21 | Texas Instruments Incorporated | Method for fabricating MESFET device using a double LOCOS process |
| JPS60247922A (en) * | 1984-05-23 | 1985-12-07 | Hitachi Ltd | Manufacture of semiconductor device |
| ATE41836T1 (en) * | 1985-06-03 | 1989-04-15 | Siemens Ag | PROCESS FOR SIMULTANEOUS FABRICATION OF BIPOLAR AND COMPLEMENTARY MOS TRANSISTORS ON A COMMON SILICON SUBSTRATE. |
| JPS63117467A (en) * | 1986-11-05 | 1988-05-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1990
- 1990-03-09 KR KR1019900003165A patent/KR930000876B1/en not_active IP Right Cessation
-
1991
- 1991-03-06 DE DE4107149A patent/DE4107149C2/en not_active Expired - Fee Related
- 1991-03-08 JP JP3043595A patent/JP2524431B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0774124A (en) | 1995-03-17 |
| KR910017599A (en) | 1991-11-05 |
| KR930000876B1 (en) | 1993-02-08 |
| DE4107149C2 (en) | 1997-04-03 |
| DE4107149A1 (en) | 1991-09-12 |
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