KR910017599A - Nitride barrier structure and etching method for ion implantation - Google Patents

Nitride barrier structure and etching method for ion implantation Download PDF

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Publication number
KR910017599A
KR910017599A KR1019900003165A KR900003165A KR910017599A KR 910017599 A KR910017599 A KR 910017599A KR 1019900003165 A KR1019900003165 A KR 1019900003165A KR 900003165 A KR900003165 A KR 900003165A KR 910017599 A KR910017599 A KR 910017599A
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KR
South Korea
Prior art keywords
oxide film
nitride film
locos
low temperature
photoresist
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Application number
KR1019900003165A
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Korean (ko)
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KR930000876B1 (en
Inventor
정원영
권오경
Original Assignee
문정환
금성일렉트론주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론주식회사 filed Critical 문정환
Priority to KR1019900003165A priority Critical patent/KR930000876B1/en
Priority to DE4107149A priority patent/DE4107149C2/en
Priority to JP3043595A priority patent/JP2524431B2/en
Publication of KR910017599A publication Critical patent/KR910017599A/en
Application granted granted Critical
Publication of KR930000876B1 publication Critical patent/KR930000876B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Abstract

내용 없음No content

Description

이온 주입을 위한 질화막 저지 구조 및 식각 방법Nitride barrier structure and etching method for ion implantation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도 ㈎~㈙는 본 발명에 의한 이온 주입을 위한 질화막 저지 구조 및 식각 방법의 공정도.1 is a process chart of the nitride film blocking structure and etching method for ion implantation according to the present invention.

Claims (1)

필드 산화막(1)이 형성된 실리콘 서브스트레이트(7)의 위에 LOCOS버퍼용 산화막(2) 및 LOCOS용 질화막(3)을 형성하고, LOCOS용 질화막(3)의 위에 저온 산화막(4)을 주입 에너지에 따라 두께를 다르게하여 침전하고, 저온 산화막(4)의 위에 저지용 질화막(5)을 침전하고, 저지용 질화막(5)의 위에 포토 레지스터(6)를 입힌후 노출 성장하고, 저지용 질화막(5)과 포토 레지스터(6)를 질화막 챔버에서 건식 식각하고, 포토 레지스터(6)와 저온 산화막(4)을 산화막 챔버에서 저온 산화막 식각하고, 포토 레지스터(6)를 스트립하고, 고에너지 이온을 주입(I/I)하고, 저지용 질화막(5)을 제거하고, 저온 산화막(4)을 제거하고, LOCOS용 질화막(3)을 제거하고, LOCOS 버퍼용 산화막(2)을 제거하도록 하는 공정을 포함하여 이루어진 것을 특징으로 하는 이온 주입을 위한 질하막 저지 구조 및 식각 방법.The LOCOS buffer oxide film 2 and the LOCOS nitride film 3 are formed on the silicon substrate 7 on which the field oxide film 1 is formed, and the low temperature oxide film 4 is deposited on the LOCOS nitride film 3 on the injection energy. Precipitates with different thicknesses, precipitates the blocking nitride film 5 on the low temperature oxide film 4, coats the photoresist 6 on the blocking nitride film 5, and then grows the exposed nitride film 5 ) And the photoresist 6 are dry etched in the nitride film chamber, the photoresist 6 and the low temperature oxide film 4 are etched at a low temperature in the oxide film chamber, the photoresist 6 is stripped, and high energy ions are implanted ( I / I), the blocking nitride film 5 is removed, the low temperature oxide film 4 is removed, the LOCOS nitride film 3 is removed, and the LOCOS buffer oxide film 2 is removed. Sublingual membrane stop structure for ion implantation, characterized in that Etching method. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900003165A 1990-03-09 1990-03-09 HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM KR930000876B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019900003165A KR930000876B1 (en) 1990-03-09 1990-03-09 HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM
DE4107149A DE4107149C2 (en) 1990-03-09 1991-03-06 Blocking procedure when implanting high energy ions using a nitride film
JP3043595A JP2524431B2 (en) 1990-03-09 1991-03-08 Ion implantation blocking method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900003165A KR930000876B1 (en) 1990-03-09 1990-03-09 HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM

Publications (2)

Publication Number Publication Date
KR910017599A true KR910017599A (en) 1991-11-05
KR930000876B1 KR930000876B1 (en) 1993-02-08

Family

ID=19296842

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900003165A KR930000876B1 (en) 1990-03-09 1990-03-09 HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM

Country Status (3)

Country Link
JP (1) JP2524431B2 (en)
KR (1) KR930000876B1 (en)
DE (1) DE4107149C2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19611512A1 (en) 1996-03-23 1997-09-25 Pierburg Ag Electrically powered air pump

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2832388C2 (en) * 1978-07-24 1986-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Process for the production of MNOS and MOS transistors in silicon gate technology on a semiconductor substrate
JPS56105651A (en) * 1980-01-28 1981-08-22 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS56148823A (en) * 1980-04-21 1981-11-18 Toshiba Corp Production of planer type semiconductor device
JPS57128921A (en) * 1981-02-02 1982-08-10 Nec Corp Manufacture of semiconductor element
DE3133841A1 (en) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS
US4466174A (en) * 1981-12-28 1984-08-21 Texas Instruments Incorporated Method for fabricating MESFET device using a double LOCOS process
JPS60247922A (en) * 1984-05-23 1985-12-07 Hitachi Ltd Manufacture of semiconductor device
ATE41836T1 (en) * 1985-06-03 1989-04-15 Siemens Ag PROCESS FOR SIMULTANEOUS FABRICATION OF BIPOLAR AND COMPLEMENTARY MOS TRANSISTORS ON A COMMON SILICON SUBSTRATE.
JPS63117467A (en) * 1986-11-05 1988-05-21 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
DE4107149A1 (en) 1991-09-12
JP2524431B2 (en) 1996-08-14
DE4107149C2 (en) 1997-04-03
KR930000876B1 (en) 1993-02-08
JPH0774124A (en) 1995-03-17

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