KR930000876B1 - HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM - Google Patents

HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM Download PDF

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KR930000876B1
KR930000876B1 KR1019900003165A KR900003165A KR930000876B1 KR 930000876 B1 KR930000876 B1 KR 930000876B1 KR 1019900003165 A KR1019900003165 A KR 1019900003165A KR 900003165 A KR900003165 A KR 900003165A KR 930000876 B1 KR930000876 B1 KR 930000876B1
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nitride film
oxide film
blocking
ion implantation
film
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KR910017599A (en
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정원영
권오경
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금성일렉트론 주식회사
문정환
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Priority to DE4107149A priority patent/DE4107149C2/en
Priority to JP3043595A priority patent/JP2524431B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Abstract

A high energy ion implantation blocking method comprises (A) forming a field oxide film (1) on a part of field area of nitride film (3) eliminated selectively after forming a buffer oxide film (2) and nitride film (3) on a silicon substrate (7), (B) forming a low temperature oxide film (4) and blocking nitride film (5) by controlling the thickness according to the energy strength of ion implantation, (C) defining an area of ion implantation by a photography process after coating (5) with photoresists (6), (D) dry etching (6) and (5) in nitrogen atmosphere with a different etching ratio respectively, (E) dry etching (6) and (4) in oxygen atmosphere with a different etching ratio respectively, (F) eliminating the remaining (6) and high energy ion implanting, (G) eliminating (5), (4), (3) and (2).

Description

질화막을 이용한 고에너지 이온 주입 저지방법High energy ion implantation prevention method using nitride film

제1도 (a)-(l)는 본 발명에 따른 질화막을 이용한 고에너지 이온주입 저지 방법.Figure 1 (a)-(l) is a high energy ion implantation prevention method using the nitride film according to the present invention.

제2도는 제1도에서의 구성도시 참조도.2 is a reference view of the configuration diagram in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 필드산화막 2 : 버퍼산화막1: field oxide film 2: buffer oxide film

3 : 질화막 4 : 저온산화막3: nitride film 4: low temperature oxide film

5 : 저지용 질화막 6 : 포토래지스트5: nitride film for blocking 6: photoresist

7 : 실리콘기판 I/I : 이온주입7: silicon substrate I / I: ion implantation

본 발명은 질화막을 이용한 고에너지 이온주입 저지 방법에 관한 것으로, 특히 고에너지 이온 주입 저지(High Energy Ion Implantation Blocking)에 적당하도록 한 질화막을 이용한 고에너지 이온주임 저지 방법에 관한 것이다.The present invention relates to a high energy ion implantation blocking method using a nitride film, and more particularly, to a high energy ion implant blocking method using a nitride film made suitable for high energy ion implantation blocking.

일반적으로, 고에너지 이온주입 저지를 위하여 메탈 물질(W,Ti)등이 저지 물질로 거론되어지고 있으나 이 물질의 사용에 따른 세부적인 기술이나 저지 구조(Blockin g Structure) 및 저지 방법(Blocking method)에 따른 정보는 따로 있지 않았다.Generally, metal materials (W, Ti), etc. have been mentioned as blocking materials for the prevention of high energy ion implantation, but detailed techniques, blocking g structures, and blocking methods according to the use of these materials are mentioned. There was no information according to.

또, 종래에는 메탈 물질을 증착시키고 포토레지스트(Photo Resist)를 덮어( Coating) 저지부분에 이온이 침투하지 못하도록 하였는데 이 방법은 다음과 같은 문제점을 갖고 있었다.In addition, in the related art, a metal material is deposited and a photoresist is coated to prevent ions from penetrating into the coating barrier. This method has the following problems.

즉 포토레지스트를 사용하는 기존의 공정을 사용할시에는 포토레지스터의 두께가 너무 두꺼움으로 인하여 CD 콘트롤이 힘들며, 포토레지스트가 변질될 수 있고, 포토레지스트의 두께에도 한계가 있다.That is, when using a conventional process using a photoresist, the thickness of the photoresist is too thick, CD control is difficult, the photoresist may be deteriorated, the thickness of the photoresist is limited.

또한, 메탈 물질(즉, W,Ti등)을 사용할 경우에 메탈과 질화막 또는 산화막의 각 팽창계수가 서로 차이를 발생하게 되어 웨이퍼에 결함 또는 변휘가 유발될 수 있고 또 저지층 스트립시 웨이퍼(Water) 표면에 손상을 입게 되어 원하는 소자의 특성이 구현되지 않게 된다.In addition, in the case of using a metal material (ie, W, Ti, etc.), the expansion coefficients of the metal, the nitride film, or the oxide film may be different from each other, which may cause defects or variations in the wafer. ) The surface may be damaged and the desired device characteristics may not be realized.

따라서 상기한 문제점들을 해결한 본 발명의 질화막을 이용한 고에너지 이온 주입저지 방법을 첨부된 도면 제1도를 찹조하여 설명하면 다음과 같다.Therefore, the high energy ion implantation blocking method using the nitride film of the present invention which solves the above problems will be described with reference to FIG.

제1도 (a)와 같이 실리콘기판(7)에 LOCOS(Local Oxidation of Silicon)용 버퍼산화막(2)을 성장하고 그 위체 LOCOS용 질화막(3)을 형성하여 필드영역의 LOCO S용 질화막(3)을 선택적으로 제거한 다음 열산화공정으로 질화막(3)이 제거된 부위에 필드산화막(1)을 형성한다.As shown in FIG. 1 (a), a LOCOS buffer oxide film 2 is grown on a silicon substrate 7 and a LOCOS nitride film 3 is formed to form a local LOCOS nitride film 3 in the field region. ) Is selectively removed, and then a field oxide film 1 is formed at the site where the nitride film 3 is removed by a thermal oxidation process.

그리고 제1도 (b)와 같이 전면에 용액(Stress)을 감소시키기 위한 저온 산화막 (4; LTD : Low Temperature Oxide)을 증착한다.And as shown in Figure 1 (b) to deposit a low temperature oxide film (LT; Low Temperature Oxide) (4) to reduce the stress (Stress) on the front.

이때 저온산화막(4)과 LOCOS용 질화막(3)의 두께 비율을 약 4:1정도로 이온주입 에너지에 따라 저온산화막(4)의 두께를 적절히 증착한다.At this time, the thickness ratio of the low temperature oxide film 4 and the LOCOS nitride film 3 is about 4: 1, and the thickness of the low temperature oxide film 4 is appropriately deposited according to the ion implantation energy.

제1도 (c)와 같이 주입에너지에 맞추어 저온산화막(4) 위에 저지용 질화막(5)을 증착하고, 제1도 (d)와 같이 저지용 질화막(5) 위에 회로형성을 위한 포토레지스트 (6)를 입힌 후 포토리토그래피(Photo Lithography) 공정으로 이온주입 영역을 정의한 후 제1도 (e)와 같이 질화분위기 챔버(Nitride Chamber)에서 저지용 질화막(5)과 포토레지스트(6)의 식각비율을 약 1.5:1로 하여 포토레지스트(6)와 저지용 질화막(5)을 건식 식각한다.A resistive nitride film 5 is deposited on the low temperature oxide film 4 in accordance with the implantation energy as shown in FIG. 1 (c), and a photoresist for forming a circuit on the resistive nitride film 5 as shown in FIG. 6) After the ion implantation region is defined by the photolithography process, as shown in FIG. 1 (e), the etch nitride film 5 and the photoresist 6 are etched in the nitride chamber. The photoresist 6 and the blocking nitride film 5 are dry etched at a ratio of about 1.5: 1.

그 다음 제1도 (f)와 같이 산화분위기 챔버(Oxide Chamber)에서 저온산화막( 4)과 포토레지스트(6)의 식각 비율을 약 3:1로 하여 포토레지스트(6)와 저온산화막(4 )을 건식 식각한다.Next, as shown in FIG. 1 (f), the etch ratio of the low temperature oxide film 4 and the photoresist 6 in the oxide chamber is about 3: 1, and thus the photoresist 6 and the low temperature oxide film 4 Dry etch.

이때 잔류한 저온산화막(4)의 두께를 약 1,000[Å]으로 한다.At this time, the thickness of the remaining low-temperature oxide film 4 is about 1,000 [mm].

제1도 (g)와 같이 고에너지로 인하여 발생하는 포토레지스트(6)의 변질 및 미립자의 제거를 위하여 포토레지스트(6)를 스트립하고, 고에너지 이온을 주입(I/I)하면 이온주입 영역은 저지용 질화막(5)이 제거된 부분(B)이고 이온주입 저지영영은 저지용 질화막(5)이 남아 있는 부분(A)이 된다.As shown in FIG. 1 (g), when the photoresist 6 is stripped for the deterioration of the photoresist 6 generated by the high energy and the fine particles are removed, and the high energy ions are implanted (I / I), the ion implantation region Is the portion B from which the blocking nitride film 5 has been removed, and the ion implantation blocking film becomes the portion A from which the blocking nitride film 5 remains.

이때 주입에너지는 저온산화막(4; 1,000[Å])과 LOCOS용 질화막(3)과 LOC OS용 버퍼 산화막(2)의 두께를 고려하여야 한다.At this time, the implanted energy should take into account the thickness of the low temperature oxide film 4 (1,000 [Å]), the nitride film 3 for LOCOS and the buffer oxide film 2 for LOC OS.

이와 같은 본 발명의 일실시예로서, LOCOS용 질화막(3), 저온산화막(4), 저지용 질화막(5), 포토레지스트(6)의 두께를 각각 1500Å ; 6000Å ; 15,000Å ; 15,00 0Å ; 으로 한다.As an embodiment of the present invention, the LOCOS nitride film 3, the low temperature oxide film 4, the blocking nitride film 5, and the photoresist 6 each have a thickness of 1500Å; 6000 kPa; 15,000 kPa; 15,00 0 Hz; It is done.

그리고 제1도 (h)와 같이 저지용 질화막, 저온산화막(4), LOCOS용 질화막(3), LOCOS용 버퍼산화막(2)을 차례로 제거하므로 공정을 완성한다.As shown in FIG. 1 (h), the blocking nitride film, the low temperature oxide film 4, the LOCOS nitride film 3, and the LOCOS buffer oxide film 2 are sequentially removed, thereby completing the process.

따라서 본 발명은 제2도에 도시된 바와 같이 실리콘 기판(7) 위의 LOCOS용 버퍼산화막(2) 및 LOCOS용 질화막(3)은 LOCOS용으로 기존의 구조이며, 그 외의 저온산화막(4)은 응력 완화용으로 웨이퍼 표면의 압력을 감소시키기 위한 구조이고, 저지용 질화막(5)은 고에너지 저지용 구조이다.Therefore, in the present invention, as shown in FIG. 2, the LOCOS buffer oxide film 2 and the LOCOS nitride film 3 on the silicon substrate 7 have a conventional structure for LOCOS, and the other low temperature oxide film 4 It is a structure for reducing the pressure on the wafer surface for stress relaxation, and the blocking nitride film 5 is a high energy blocking structure.

이상에서 설명한 바와 같이 본 발명의 질화막을 이용한 고에너지 이온주입 저지방법은 질화막(5)을 저지물로 사용하였으므로 기존 장비로도 공정을 쉽게 진행할 수 있으며, 또한 이온주입 저지용 물질로 질화막(5)을 사용하였기 때문에 다른물질(Al, PR, Qxide)에 비하여 훨씬 더 얇은 두께로 저지작용을 할 수 있어서 CD 콘트롤이 쉽고, 정확하며, 이온주입시에 저온산화막(4)과 저지용 질화막(5) 및 LOCOS용 버퍼 산화막(2 )의 상단 전면에 주입함으로써 고에너지 이온주입시에 발생할 수 있는 표면의 결함을 별도의 공정없이도 없앨 수 있으며 고에너지 이온주입 저지의 효율을 높이고, 이에 따른 여러가지의 문제점을 쉽게 해결할 수 있는 효과를 갖게 된다.As described above, since the high energy ion implantation blocking method using the nitride film of the present invention uses the nitride film 5 as a blocking material, the process can be easily performed with existing equipment, and the nitride film 5 as an ion implantation blocking material. Because of this, it is possible to control the CD with much thinner thickness than other materials (Al, PR, Qxide), so CD control is easy, accurate, and low temperature oxide film (4) and blocking nitride film (5) during ion implantation. And by implanting the upper surface of the LOCOS buffer oxide film (2) to eliminate the surface defects that may occur during high-energy ion implantation without a separate process to increase the efficiency of the high-energy ion implantation blocking, and thus various problems It will have an effect that can be easily solved.

상기 본 발명의 서술 및 도면에서는 CCD 디바이스에서의 소자특성을 개선하기 위한 하이-C, P-레이어에 대하여 설명하였으나 본 발명의 기술방법을 응용하여 D-램 셀의 웰(retrograd well) 형성시, 바이폴라 매몰층 P-레이어 형성시에도 이용될 수 있는 동시에 메가일렉트론 볼트(MeV)급의 모든 고에너지 이온 주입공정에도 처리에도 적용할 수 있다.In the description and drawings of the present invention, the high-C and P-layers for improving device characteristics in a CCD device have been described. However, in the case of forming a well of a D-ram cell by applying the method of the present invention, It can be used to form bipolar buried layer P-layers, and can also be applied to all high-energy ion implantation processes in the class of megaelectron bolts (MeV).

Claims (1)

실리콘 기판(7) 위에 버퍼산화막(2)과 질화막(3)을 형성하고 필드영역의 질화막(3)을 선택 제거하여 필드영역에 필드산화막(1)을 형성하는 제1공정과, 전면에 이온 주입할 에너지의 세기에 따라 두께를 조절하여 저온산화막(4)과 저지용 질화막(5)을 차례로 형성하는 제2공정과, 저지용 질화막(5) 위에 포토레지스트(6)를 입힌 후 포토리토그래피 공정으로 이온주입 영역을 정의하는 제3공정과, 저지용 질화막(5)과 포토레지스트(6)를 질화분위기 챔버에서 서로 다른 식각비로 건식 식각하는 제4공정과, 포토레지스트(6)와 저온 산화막(4)을 산화분위기 챔버에서 서로 다른 식각 비욜로 건식 식각하는 제5공정과, 남아있는 포토레지스트(6)를 제거하고, 고에너지 이온을 주입(I/ I)하는 제6공정과, 저지용 질화막(5), 저온산화막(4), LOCOS용 질화막(3), LOCOS 버퍼용 산화막(2)을 차례로 제거하는 제7공정을 포함하여 이루어진 것을 특징으로 하는 질화막을 이용한 고에너지 이온주입 저지방법.A first process of forming a field oxide film (1) in the field region by forming a buffer oxide film (2) and a nitride film (3) on the silicon substrate (7) and selectively removing the nitride film (3) in the field region; A second step of sequentially forming the low temperature oxide film 4 and the blocking nitride film 5 by controlling the thickness according to the strength of the energy to be used, and applying a photoresist 6 onto the blocking nitride film 5 and then performing a photolithography step. A third step of defining the ion implantation region, a fourth step of dry etching the blocking nitride film 5 and the photoresist 6 at different etching ratios in the nitride atmosphere chamber, the photoresist 6 and the low temperature oxide film ( 4) dry etching of 4) with different etching rates in the oxidizing atmosphere chamber; a sixth step of removing the remaining photoresist 6 and implanting high energy ions (I / I); and a nitride film for blocking (5), low temperature oxide film (4), nitride film for LOCOS (3), oxide film for LOCOS buffer A high energy ion implantation blocking method using a nitride film, comprising a seventh step of sequentially removing (2).
KR1019900003165A 1990-03-09 1990-03-09 HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM KR930000876B1 (en)

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KR1019900003165A KR930000876B1 (en) 1990-03-09 1990-03-09 HIGH ENERGY ION BEAM BLOCKING METHOD USING Si3N4 FILM
DE4107149A DE4107149C2 (en) 1990-03-09 1991-03-06 Blocking procedure when implanting high energy ions using a nitride film
JP3043595A JP2524431B2 (en) 1990-03-09 1991-03-08 Ion implantation blocking method

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